Dhwani Sametriya

Knowmore CPH

With the prevalence of VLSI technology and electronics devices becoming smaller, denser, smarter and long lasting, the research in the field of low voltage applicability and low power consumption is turning omnidirectional among which one direction leads towards the depth of faster and precise clock generation which is achieved on the foundation of Phase Locked Loops. The time has come to break one of the famous Silicon Valley golden rules which states “Higher the clock frequency, Greater the power consumption”. Keeping the trivial relationship between power consumption and power dissipation in mind, lowering supply voltages is the most effective method to reduce power consumption. Digging deep into deep submicron CMOS technology, there are design and power management challenges present for Analog and Mixed Signal devices such as PLL. It is very much required to optimize PLL as it is one the most important blocks of clock generation system and one of the most power consuming blocks as well. Here, ALF CPPLL is designed operating at low supply voltage with active loop filter charge pump to avoid charge sharing effects and current mismatches in control voltage for 4-delay stage differential Ring-Voltage Controlled Oscillator to effectively produce higher VCO frequency at low reference crystal frequency.