D.F. Chiper

D.F. Chiper
Gheorghe Asachi Technical University of Iasi Technical Sciences Academy of Romania (ASTR)

PhD,Habil.

About

54
Publications
2,626
Reads
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398
Citations
Additional affiliations
June 2021 - November 2024
Romanian Scientists Academy (AOSR)
Position
  • Corespondent member
Description
  • Associate member
July 2021 - present
Technical Sciences Academy of Romania
Position
  • Associate member
Description
  • Associate member

Publications

Publications (54)
Article
An analytical synthesis technique in the frequency domain is proposed for a particular class of 2D filters, namely circular wide-band low-pass FIR filters. The design starts from a low-pass prototype filter which is ideally maximally flat, with specified bandwidth, based on hyperbolic tangent function. This is approximated as a trigonometric polyno...
Article
Full-text available
This work proposes an analytical design procedure for a particular class of 2D filters, namely anisotropic Gaussian FIR filters. The design is achieved in the frequency domain and starts from a low-pass Gaussian 1D prototype with imposed specifications, whose frequency response is efficiently approximated by a factored trigonometric polynomial usin...
Article
Full-text available
This paper proposes an analytical design procedure for 2D FIR circular filter banks and also a novel, computationally efficient implementation of the designed filter bank based on a polyphase structure and a block filtering approach. The component filters of the bank are designed in the frequency domain using a specific frequency transformation app...
Article
Full-text available
This paper introduces an efficient solution for designing a unified VLSI implementation for type IV DCT/DST while solving one challenging problem in obtaining high performance VLSI chips for common goods, which is solving the security of the hardware while obtaining a VLSI implementation with high performance. The new solution uses a new systolic a...
Article
Full-text available
In this paper, we present two systolic array algorithms for efficient Very-Large-Scale Integration (VLSI) implementations of the 1-D Modified Discrete Sine Transform (MDST) using the systolic array architectural paradigm. The new algorithms decompose the computation of the MDST into modular and regular computational structures called pseudo-circula...
Article
Full-text available
This paper presents a MATLAB implementation of the exact real Discrete Tchebichef Transform (DTT) and Integer Discrete Tchebichef Transform (IDTT) with their inverse functions. It is a simple and scalable package that is the first of its kind for MATLAB. This software provides an efficient way to advance research related to DTT, IDTT, and their inv...
Article
Full-text available
In this paper, we propose a new hardware algorithm for an integer based discrete cosine transform (IntDCT) that was designed to allow an efficient VLSI implementation of the discrete cosine transform using the systolic array architectural paradigm. The proposed algorithm demonstrates multiple benefits specific to integer transforms with efficient h...
Article
Full-text available
In the new era of digital revolution, the digital sensors and embedded designs become cheaper and more present [...]
Article
Full-text available
This paper aims to solve one of the most challenging problems in designing VLSI chips for common goods, namely an efficient incorporation of security techniques while maintaining high performances of the VLSI implementation with a reduced hardware complexity. In this case, it is very important to maintain high performance at a low hardware complexi...
Article
Full-text available
This paper aims to present a unified overview of the main Very Large-Scale Integration (VLSI) implementation solutions of forward and inverse discrete sine transforms using systolic arrays. The main features of the most important solutions to implement the forward and inverse discrete sine transform (DST) using systolic arrays are presented. One of...
Article
In this paper we propose a new VLSI algorithm for an integer based discrete sine transform (IntDST) that allows an efficient VLSI implementation using systolic arrays. The proposed algorithm have all the benefits of an integer transform as a good approximation of irrational transform coefficients and allows an efficient restructuring into a regular...
Article
Full-text available
This paper aims at solving one challenging problem in designing VLSI chips, namely, the security of the hardware, by presenting a new design approach that incorporates the obfuscation technique in the VLSI implementation of some important DSP algorithms. The proposed method introduces a new approach in obtaining a unified VLSI architecture for comp...
Article
Full-text available
The forward and inverse DCT has many applications in digital signal processing area, but, due to its high arithmetic complexity, it is necessary to find efficient software implementations or even to find VLSI implementations for them. Existing fast algorithms for IDCT or DCT have a SFG graph that is not very regular and modular and, even more impor...
Article
This work presents an efficient hardware implementation of a hardware accelerator for the computation of the Modified Discrete Sine transform (MDST) using a new VLSI algorithm based on a appropriate reformulation of the MDST algorithm using some auxiliary input and output sequences. The obtained hardware implementation is using a low complexity imp...
Article
This paper presents a new split-radix algorithm for DHT of length \({N}=2^{n}\), called the Dual Split-Radix DHT (DSR DHT), that allows an efficient parallel implementation using a dual core system. Moreover, as it is different from existing split-radix algorithms for DHT, it offers an efficient hardware implementation similar to that for FFT. It a...
Conference Paper
An efficient design approach to derive a unified high performance systolic array architecture for prime length type IV DCT and DST is proposed. This approach is based on a unified VLSI algorithm that uses a parallel restructuring of type IV DCT and DST. It uses parallel pseudo-circular correlation structures as basic computational forms. Most of th...
Article
A new very large scale integration (VLSI) algorithm for a 2N-length discrete Hartley transform (DHT) that can be efficiently implemented on a highly modular and parallel VLSI architecture having a regular structure is presented. The DHT algorithm can be efficiently split on several parallel parts that can be executed concurrently. Moreover, the pro...
Article
In this brief, a new efficient radix-2 fast algorithm for the computation of type-III discrete Hartley transform of length that has a small arithmetic cost and is well suited for a very large-scale integration (VLSI) implementation is presented. This recursive method requires a small number of arithmetic operations compared with existing methods, h...
Article
We present a new efficient method for the computation of the discrete Hartley transform of type II and radix-2 length N =2 n . This recursive method requires a reduced number of arithmetic operations compared with existing methods and can be easily implemented. A new efficient method for the direct computation of a length N type-II DHT from two adj...
Article
Full-text available
A new VLSI algorithm and its associated systolic array architecture for a prime length type IV discrete cosine transform is presented. They represent the basis of an efficient design approach for deriving a linear systolic array architecture for type IV DCT. The proposed algorithm uses a regular computational structure called pseudoband correlation...
Conference Paper
A new design approach to derive a systolic array architecture for a prime length type IV discrete sine transform based on a regular and modular computational structure is presented. This approach is based on a VLSI algorithm that uses an appropriate restructuring method of type IV DST into a regular computational structure. It uses a new computatio...
Article
Full-text available
Using a specific input-restructuring sequence, a new VLSI algorithm and architecture have been derived for a high throughput memory-based systolic array VLSI implementation of a discrete cosine transform. The proposed restructuring technique transforms the DCT algorithm into a cycle-convolution and a pseudo-cycle convolution structure as basic comp...
Conference Paper
An new design approach to derive a high throughput systolic array architecture for a prime length type IV discrete cosine transform based on parallel and pipeline processing is presented. This approach is based on a parallel VLSI algorithm that uses a parallel restructuring of type IV DCT. It uses parallel pseudo-circular correlation structures as...
Article
This paper presents a new design approach for the VLSI implementation of a prime-length discrete cosine transform DCT based on a new hardware algorithm for DCT that can be implemented using a multi-port ROM-based systolic array. The proposed algorithm is based on the idea of reformulating prime-length DCT into several cycle convolutions having the...
Conference Paper
In this paper a new memory-based VLSI algorithm for 1D-DST is proposed. This algorithm uses a new formulation of the DST into cyclic convolution forms that uses a new input restructuring sequence. This approach significantly reduces the overheads necessary to restructure the DST into cyclic convolution structures. We can further use this appropriat...
Article
In this paper, a unified design framework for prime-length forward and inverse discrete cosine transforms with a high throughput is presented. The proposed design facilitates trade-off between the throughput and hardware cost or power consumption, and is well suited for low-power applications. The VLSI structure is highly regular and modular with a...
Conference Paper
In this paper, we present a new systolic algorithm for an efficient design approach using a bi-port memory-based VLSI implementation of the DHT. Using auxiliary input and output sequences and appropriate permutations it is shown that it is possible to compute a prime-length DHT using two cyclic convolutions having the same form and length that can...
Article
Full-text available
In this paper, an efficient design approach for a unified very large-scale integration (VLSI) implementation of the discrete cosine transform/discrete sine transform/inverse discrete cosine transform/inverse discrete sine transform based on an appropriate formulation of the four transforms into cyclic convolution structures is presented. This formu...
Conference Paper
An efficient design approach for a systolic array VLSI implementation of a prime-length odd-squared generalized discrete Hartley transform is presented. It uses an appropriate hardware algorithm based on an efficient decomposition of the odd-squared GDHT into two circular correlation structures having the same form and length that can be computed i...
Article
Full-text available
An efficient approach to design very large scale integration (VLSI) architectures and a scheme for the implementation of the discrete sine transform (DST), based on an appropriate decomposition method that uses circular correlations, is presented. The proposed design uses an efficient restructuring of the computation of the DST into two circular co...
Article
Full-text available
An efficient approach to the design of a VLSI array for a prime-length type III generalized discrete Hartley transform (GDHT) is presented. The design makes use of an appropriate decomposition of the GDHT into two half-length circular correlation structures having the same length and form that can be concurrently computed and implemented on a singl...
Conference Paper
This paper presents a new design approach for a memory-based VLSI implementation of IDCT and lDST transforms. This approach is based on a new systolic array algorithm that uses a highly modular and regular computational structure as circular convolution and can be used to obtain a highly efficient unified VLSI chip for both IDCT and IDST with very...
Conference Paper
This paper presents a new design approach for the inverse discrete sine and cosine transforms based on a new unified systolic array algorithm that can be used to obtain VLSI array architectures with very small differences in the hardware structure for the two transforms and improved performances. This new algorithm is based on using highly regular...
Conference Paper
A new approach for a memory-based VLSI realization of the 1D discrete cosine transform (1D-DCT) that significantly improves the previous designs is presented. This approach is based on a new formulation of an odd prime-length DCT algorithm. It uses two half-length cyclic convolutions with the same form, which are such reformulated that multipliers...
Conference Paper
In this paper, a new approach for the realization of a unified VLSI array for discrete cosine and sine transforms (1D-DCT/DST) is presented. This approach is based on new computational relations for odd prime-length DST and DCT which uses two half-length cyclic convolutions having the same form and length which can be computed in parallel using har...
Conference Paper
A new systolic algorithm for memory-based parallel VLSI implementation of the inverse to discrete cosine transform (IDCT) is proposed. The new approach is based on a new formulation of an odd prime-length IDCT which uses two half-length cyclic convolutions with the same form which can be concurrently computed and were such reformulated that an effi...
Conference Paper
In this paper, an efficient approach to design VLSI arrays for prime length discrete Hartley transform (DHT) with high throughput and low hardware complexity is proposed. The presented approach is based on an adequate decomposition of the DHT transform in two related subproblems which are efficiently converted into similar cyclic convolution forms...
Conference Paper
In this paper a new approach for the realization of the inverse 1D discrete cosine transform (IDCT) is presented. This approach is based on a new formulation of an odd prime-length IDCT which uses two half-length cyclic convolutions with the same form which can be concurrently computed. Using this approach, a new efficient systolic array with a hig...
Conference Paper
In this paper, a new approach for the realization of 1D discrete cosine transform (1D-DCT) is presented. This approach is based on a new formulation of an odd prime-length DCT which uses two half-length cyclic convolutions with the same form which can be computed in parallel. Using this approach, a new efficient systolic array with outstanding perf...
Article
The problems in the field of design and verification of digital circuits are known to belong to the NP class. To overcome the inherent complexity involved in the solutions of such problems in what follows an efficient manner of operating based on the parallel operating mode is proposed.

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