Dengquan Li

Dengquan Li
Xidian University · School of Microelectronics

PhD

About

28
Publications
862
Reads
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156
Citations
Education
October 2016 - November 2017
University of Texas at Austin
Field of study
  • Microelectronics
September 2012 - June 2018
Xidian University
Field of study
  • Microelectronics
April 2008 - July 2012
Xidian University
Field of study
  • Microelectronics

Publications

Publications (28)
Article
Full-text available
This paper analyzes high-speed front-end samplers and presents a 1 × 4 × 8 three-stage sampler for time-interleaved analog-to-digital converters. The front-end sampler mitigates timing skew and extends bandwidth by adopting global sampling and hierarchical demultiplexing. Inductive peaking is employed in both the track-and-hold amplifier and the in...
Article
This paper presents a nonbinary 2b/cycle SAR ADC structure with two assistant loop-unrolled comparators. By using the reset time of 2-bit comparators, the proposed structure achieves extra single bit conversion after normal 2-bit conversions, thus removing one comparison period compared with conventional 2-bit SAR. A nonbinary decision scheme is re...
Article
This paper proposes a high-speed 7/8-bit 800-400 MS/s configurable SAR ADC. With simple control switches, the ADC can work under two different modes with configurable resolution and sampling speed. Nonbinary technique with built-in redundancy in capacitive DAC is used for better linearity as well as improving the conversion speed. Other high-speed...
Article
In this paper, a single-channel two-step voltage-time hybrid domain analog-to-digital converter (ADC) is proposed. To achieve high sampling rate and high accuracy, 3.5-bit voltage domain MDAC and 7-bit high-speed time domain ADC (TD-ADC) are combined into a 10-bit hybrid ADC. In the first stage MDAC, a low-power push-pull amplifier is used to impro...
Article
With emerging demands of wideband radios and wireless communication, radio frequency (RF) analog-to-digital converters (ADCs) are greatly required. In recent years, the advance in technology allows a rapid development of RF ADCs, especially boosting various hybrid architectures and backend digital signal processing circuitry. This paper reviews and...
Article
Full-text available
A four‐stage Operational transconductance amplifier (OTA) used in an infrared temperature sensor adopting the proposed Feed‐forward Gm‐stage and segmenting nested Miller compensation technique is presented. The purpose of the proposed segment compensation is primarily to make more amplifier stages concatenated. The circuit linked several transcondu...
Article
This paper presents a statistical offset calibration technique for 1.5-bit/cycle successive approximation register (SAR) analog-to-digital converters (ADCs). It estimates the offset polarity by comparing the number of 0 and 1 in specific conversion cycles and performs compensation in the analog domain. Compared to prior works based on zero input in...
Article
This paper presents a 32-GS/s front-end sampling circuit (FESC) in 65-nm CMOS. The FESC is designed for a 32-channel time-interleaved analog-to-digital converter (ADC), and the [Formula: see text] two-stage interleaving structure leads to a good trade-off between bandwidth and linearity. The analysis and cancellation of charge injection, clock feed...
Article
A high-speed time domain analog-to-digital converter (ADC) customized for impulse radio ultra-wideband (IR-UWB) radars is proposed in this brief. It adopts a power efficient architecture combining time domain implementation and equivalent sampling technology. The equivalent sampling rate is high up to 8 GS/s. Compared to time interleaved (TI) ADC,...
Article
This article presents a 7-bit 900-MS/s multi-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with background offset calibration. Unlike prior works that adopt either four capacitive DACs (CDACs) or interpolated resistive DAC to enable 3-bit/cycle operation, the proposed technique uses only two CDACs to realize th...
Article
This paper presents a compact and robust opamp-free noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC). The proposed NS SAR ADC adopts extra one passive feed-forward path summing in realizing second-order noise shaping with the minimum modification to a standard SAR. Compared with previous works, the noise...
Article
This brief presents an 8-bit 350-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with 1.5 b/cycle redundancy in 65-nm CMOS. With 12.5% redundancy in conversion cycles, conversion errors caused by capacitor mismatch, offset and DAC settling errors can be addressed. Compared to the conventional 1.5 b/cycle operation, th...
Article
This paper introduces a low-power noise-shaping SAR ADC which is suitable for biomedical sensor applications. In this ADC, a low power consumption and area-efficient integrator is proposed, which is comprised of several switches, replica capacitors and a dynamic amplifier (DA). With a mode control logic circuit, the comparator in the ADC is reused...
Article
In this brief, a dual-supply two-stage op-amp is proposed for a 12-b 1 GS/s pipeline ADC, which is composed of a low-voltage supply pre-amplifier and a high-voltage supply amplifier. Its closed-loop bandwidth reaches to 5.2 GHz, and the phase margin is larger than 60∘. The closed-loop amplifier can settle to 99.95% accuracy within 230 ps, which sat...
Article
A 10-bit 100 MS/s energy-efficient successive-approximation analog-to-digital converter (SAR ADC) is presented in this paper. In order to improve the conversion rate and reduce power consumption as well, a modified spilt-capacitor VCM-based switching scheme is proposed. By utilizing the LSB capacitors to obtain the last-bit, the proposed switching...
Article
This brief presents a 10-bit 600 MS/s 4-channel time-interleaved (TI) successive approximation register analog-to-digital converter (ADC). A background calibration algorithm using Lagrange polynomial interpolation is introduced to calibrate timing skew. It consists of digital detection and adaptive derivative-based correction, employing low filter...
Article
This brief presents a high-speed successive approximation register (SAR) analog-to-digital converter (ADC) with nonbinary searching technique. By inserting redundancy in the first five decision steps, the digital-to-analog converter (DAC) settling errors can be tolerated and settling time can thus be reduced. In addition, split capacitor technology...
Article
This paper presents a 10-GS/s 6-bit track-and-hold amplifier (THA), which is designed for a 16-way time-interleaved successive approximation register (SAR) analog to digital converter (ADC). To extend the bandwidth, a differential source-degenerated common-source amplifier with peaking inductance is adopted as an input buffer. A switched source fol...
Article
Time-interleaved analog-to-digital converters (TI ADCs) suffer offset mismatch, gain mismatch, bandwidth mismatch and timing skew, of which timing skew degrades the performance most severely. In this paper, a background fast convergence calibration algorithm for timing skew is proposed. With known the range of input frequency, the algorithm employs...
Article
In a time-interleaved analog-to-digital converter (TI ADC), several individual ADCs operate in parallel to achieve a higher sampling rate. Low power consumption as well as good linearity can be obtained by applying successive approximation register (SAR) converters as sub-channel ADCs. In spite of the advantages, this structure suffers from three m...
Article
This paper presents an 8-bit configurable time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). By using a mode selection circuit, four modes of sampling rate are provided: Single channel at 333.3 MS/s, 2-channel at 666.7 MS/s, 3-channel at 1 GS/s and 6-channel at 2 GS/s. An on-chip delay-locked loop (DLL)...
Article
This paper presents an 8-bit 500-MS/s asynchronous single-channel successive approximation register analog-to-digital converter (SAR ADC). A split capacitor array technique is applied to decrease the digital-to-analog converter (DAC) settling time. Moreover, the design optimizes the logic delay of the SAR controller, resulting in a better match bet...

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