Degang Chen

• PhD
• Chair at Iowa State University

Waveform generation as part of on-chip built-in self-test (BIST) circuitry often necessitates sufficient linearity without expensive hardware overhead. Achieving high linearity is critical for accurate signal generation, especially in applications requiring high precision, such as biomedical and instrumentation applications. Currently, achieving th...

This paper introduces a compact NMOS-based temperature sensor designed for precise thermal management in high-performance integrated circuits. Fabricated using the TSMC 180 nm process with a 1.8 V supply, this sensor employs a single diode-connected NMOS transistor, achieving a significant size reduction and improved voltage headroom. The sensor’s...

In this paper, we present a novel digital-like defect-oriented built-in self-test (BIST) methodology for analog and mixed-signal (AMS) circuits. The core idea of this approach centers around the segmentation of complex AMS circuits into smaller, more manageable units for analysis. Emphasizing resource utilization efficiency, we highlight the necess...

This paper introduces a systematic approach to the design of Direct Current-to-Digital Converter (DIDC) specifically engineered to overcome the limitations of traditional current measurement methodologies in System-on-Chip (SoC) designs. The proposed DIDC addresses critical challenges such as high power consumption, large area requirements, and the...

Waveform generation as part of an on-chip built-in self-test (BIST) circuitry often necessitates sufficient linearity without expensive hardware overhead. Achieving high linearity is critical for accurate signal generation, especially in applications requiring high precision, such as biomedical and instrumentation. Currently, achieving the high lin...

Operational amplifiers (op amps) are fundamental blocks that find wide application both as stand-alone devices and as crucial blocks embedded in various Systems on Chips (SoCs). Achieving high defect coverage, as well as performing defect localization in these circuits, has proven to be a difficult/expensive task, even with sophisticated testing ci...

Increasing complexity of integrated circuits (ICs) is making post-production tests expensive and cumbersome. Approximate testing can help alleviate these issues. The paper proposes a BIST based approximate testing approach for linearity testing of embedded data converters. The methodology does not require any external equipment and counts on the fa...

This paper presents a systematic approach to generate layouts for two devices, with an arbitrary integer ratio of device sizes, that cancels up to at least 3rd order gradient effects. A new analysis leads to mathematical constraints on 1-dimensional layouts that meet the required integer ratio and cancel 2nd -order gradients. From those layouts, we...

p>In this paper, we present a novel digital-like defect-oriented Built-In Self-Test (BIST) methodology for Analog and Mixed-Signal (AMS) circuits. The core idea of this approach centers around the segmentation of complex AMS circuits into smaller, more manageable units for analysis. Emphasizing resource utilization efficiency, we highlight the nece...

p>In this paper, we present a novel digital-like defect-oriented Built-In Self-Test (BIST) methodology for Analog and Mixed-Signal (AMS) circuits. The core idea of this approach centers around the segmentation of complex AMS circuits into smaller, more manageable units for analysis. Emphasizing resource utilization efficiency, we highlight the nece...

Parallel (multi-site) testing tests multiple chips simultaneously, increasing throughput and reducing test costs per chip. As the number of test sites is increased (to further maximize throughput), pronounced variations are often observed in the measurements from site to site, plaguing test accuracy. This paper presents a survey of recent research...

In AMS circuits, the defect simulation time is increasing prohibitively as the circuits are becoming more and more complex. In addition to this, as the need for high defect coverage is increasing due to standards such as ISO26262, the defect simulation time is further increasing. In this chapter, we further improve the time-efficiency of the framew...

Defect-oriented testing is becoming increasingly popular in recent times, especially in safety-critical applications in automotive, space, and medical industries. The stringent quality requirements from these industries such as zero defective parts per million (DPPM) necessities a need to have efficient defect testing methods with reduced defect si...

Operational amplifiers (op amps) are fundamental blocks that find wide application both as stand-alone devices and as crucial building blocks embedded in various Systems on Chips (SoCs). Achieving high defect coverage as well as performing diagnosis and defect localization in these circuits has been proven to be a difficult/expensive task even with...

Higher complexity in recent chip designs, module integration, and increasing test quality requirements have expanded measurement needs and further increased chip test costs. Multi-site testing (parallel measurement) solves this issue by taking test measurements from multiple chips simultaneously, massively increasing throughput, and significantly r...

Field deployment is critical to developing numerous sensitive impedance transducers. Precise, cost-effective, and real-time readout units are being sought to interface these sensitive impedance transducers for various clinical or environmental applications. This paper presents a general readout method with a detailed design procedure for interfacin...

Multi-site measurement (testing) increases throughput and reduces production test costs by simultaneously testing multiple chips. However, as the number of test sites is increased (to maximize throughput further), site-to-site variation in analog and mixed-signal circuits test measurement inevitably increases to levels causing mis-trim and/or miscl...

Defect-oriented testing is becoming increasingly popular in recent times, especially in safety-critical applications in automotive, space and medical industries. The stringent quality requirements from these industries such as zero defective parts per million (DPPM) necessities a need to have efficient defect testing methods. Furthermore, the overa...

A general approach based on a natural basis function expansion to cancel the temperature-curvature of the base-emitter voltage in the bipolar transistors embedded in bandgap references is presented. The proposed method can be applied to the widely used Banba, Kuijk, and Brokaw structures to build references with sub-ppm/°C temperature coefficients....

Extensive use of electronic components in mission critical applications has brought reliability concerns in VLSI to the forefront. Ageing related reliability effects such as Time Dependent Dielectric Breakdown (TDDB) might lead to in-field chip failures, thereby degrading the functional safety of the modules. Thus, on-chip monitoring and fast chara...

The rising analog content in mixed-signal integrated circuits (ICs) is driving an increased need for measurement of analog parametric specifications during manufacturing test, thereby significantly increasing overall chip cost. Multisite (parallel) measurement alleviates this issue by measuring multiple chips at the same time, hence massively incre...

This paper presents an analog duty cycle corrector with feedback. A differential charge pump with fast startup is used to detect the duty cycle error and outputs a control voltage for current-starved inverters to adjust the pulse width. The pump current is designed to be adaptive to the input frequency, so a wide frequency range is achieved without...

Increasing demand for higher data transfer rates is bringing 4 level pulse amplitude modulation (PAM4) scheme to the forefront of high-speed serial link design. Jitter estimation is an important part of high-speed serial link design and testing. This paper presents a least square based algorithm for jitter decomposition in a PAM4 link. The pro...

This paper introduces a 12 bit 2.5 bit/cycle SAR-based pipeline ADC employing a self-bias gain boosting amplifier. The single-stage amplifier achieves a low-frequency gain of 37 dB, while consuming 1.3 mW of power consumption with 1.3 V of analog power supply. A 2.5 bit/cycle SAR ADC realizes as the sub-ADC in each stage, and reduces both power con...

An output-capacitorless low-dropout regulator (OCL-LDO) with simple structure and fast transient response is proposed for system-on-chip (SoC) applications. A super source follower is inserted into a cascoded flipped voltage follower to drive the power transistor, which forms a fast-local loop for quick turn-on. A robust overshoot detection circuit...

This paper presents a capacitive differential bridge structure with both AC and DC excitation and balancing capability for low cost electrode-solution interfacial capacitance biosensing applications. The proposed series RC balancing structure offers higher sensitivity, lower susceptibility to common-mode interferences, and drift control. To evaluat...

Resistor string is one of the classic digital-to-analog converter (DAC) architectures and has dominant applications where guaranteed monotonicity is important. For high-resolution string DACs, gradient errors limit the linearity performance by causing mismatch in the resistor arrays. In this paper, a low-cost practical string DAC structure with gra...

Achieving coherent sampling has always been a great challenge in the spectral test of analog and mixed-signal integrated circuits. It becomes more difficult in multi-tone spectral test, because all the fundamental tones should be precisely controlled to maintain stringent synchronization with sampling clock simultaneously. If coherent sampling is n...

State-of-the-art analog-to-digital converter (ADC) built-in self-test (BIST) methods relax the test stimulus linearity but require a constant voltage shift during testing. A low-cost on-chip BIST solution with a modified R2R digital-to-analog converter (DAC) structure is developed as a signal generator and a voltage shift generator for ADC linearit...

This paper presents a general approach to extract V GO from the base emitter voltage of a bipolar transistor. V GO is the silicon bandgap voltage at zero Kelvin and it is a physical constant voltage independent of temperature. The proposed method can be implemented on any of the widely used Banba, Kuijk, Brokaw or resistorless structures to build v...

A novel ultrafast and low-cost pipelined analog-to-digital converter (ADC) testing and calibration method is proposed. The ADC nonlinearities are modeled as segmented parameters with interstage gain errors. During the test phase, a pure sine wave is sent as input and the model parameters are estimated from the output data with the system identifica...

An integrated circuit solution to Johnson noise thermometry (ICJNT) using a low-cost and fast complementary metal–oxide–semiconductor (CMOS) technology is investigated in this paper. Benefits from both noise thermometry and integrated circuits (ICs) can be maintained in ICJNTs, which cost significantly less, work orders of magnitude faster than dis...

Digital-to-analog converter (DAC) is one of the circuits with increasing demands on high-accuracy requirements. However, the cost of existing high-precision DACs is high and difficult to reduce because implementation hardly benefits from the scaling of digital circuits. In this paper, a low-cost, high-precision DAC structure based on ordered elemen...

Jitter decomposition is a key tool to identify root causes of jitters in a high-speed digital communication system. It is a huge challenge in balancing the test cost and precision for conventional decomposition methods implemented in instruments where the time interval error (TIE) data are necessary. In this paper, we propose a deterministic jitter...

A fully integrated low-dropout regulator (LDO) with ultra-fast transient settling is proposed to provide a clean supply for digital circuits in nano-scale technology. A super source follower (SSF) is inserted into the cascode flipped voltage follower (FVF) topology to drive the power transistor for fast turn-on. The proposed positive transient dete...

This paper presents a Concurrent Sampling (CS) method for measuring a multitude of analog DC voltages concurrently using local digitization. Boolean results after digitization are routed in an IJTAG compatible fashion. Analog quantities are no longer routed across the die, thus overcoming several limitations of Analog Test Buses. Furthermore, the p...

The multi-tone test has gained popularity among current test methods, since it offers flexibility in characterizing systems whose nonlinearities vary over signal frequency. Thus, it is impractical to test using the single-tone test. For multi-tone, non-coherent sampling is the major issue to perform accurate spectral testing, since precise control...

Accurately characterizing linearity performance of high-resolution analog-to-digital converters (ADCs) has been a challenging task for many years, since providing input signals whose purity is beyond ADC under test becomes more difficult as the ADC performance becomes better. Previously, the stimulus error identification and removal (SEIR) method u...

Accurate spectral testing plays a crucial role in modern high-precision ADCs’ evaluation process. One of the challenges is to be able to test the continually higher-resolution ADCs accurately and cost-effectively. Due to its stringent test requirement, the standard test method for ADCs can be difficult to implement with low cost. This chapter propo...

As data acquisition systems’ performance continues to increase, so does the need for a test and characterization solution that exceeds the currently available state-of-the-art instruments. This chapter presents a new method for generating ultrapure sine waves used in such applications. The pure sine wave is generated by readily available digital-to...

In spectral analysis, achieving coherent sampling, especially when signals have large distortion, has been a challenge for many years. This chapter introduces three algorithms to resolve this issue. In comparison to previous algorithms, and two widely used methods in industry (windowing and four-parameter sine wave fit), these new algorithms are ca...

Data converters are among the most widely used components in modern integrated devices and systems. A major challenge is to characterize their performances accurately and cost-effectively. The ADC standard test requires the input sinusoidal signal to be 3–4 bits better than the ADC under test. Such high-quality sine waves are extremely difficult to...

Analog-to-digital converters (ADCs) are among one of the world’s largest volume devices. ADCs are a necessary, vital mixed-signal integrated circuit (IC) component in almost every electrical device and system. One of the challenges is to accurately and cost-effectively test the continually better performance ADCs. For spectral testing of the ADC, o...

Multi-tone signals have been widely used in various applications. One of the bottlenecks is how to maximize the signal power given a ecertain peak range, namely, achieving the minimum peak-to-average power ratio (PAPR). In this chapter, a novel strategy is proposed to achieve the minimum PAPR for multi-tone sine waves. By properly selecting each to...

This book introduces a family of new methods for accurate and robust spectral testing and fills an information gap, as the requirements in standard test have grown increasingly challenging in recent high precision testing, especially as the device performance has continued to improve. Test engineers will be enabled to accurately set their devices &...

In a high-speed digital communication system, jitter performance plays a crucial role in bit-error rate. It is important to accurately derive each type of jitter as well as total jitter and to identify root causes of jitter by jitter decomposition as a key tool. In this paper, we extend our previously reported algorithm to decompose duty cycle dist...