Debiprasad Priyabrata Acharya

National Institute of Technology Rourkela | NITR · Department of Electronics and Communication Engineering (EC)

The conventional Shannon-Nyquist sampling theory sets the goal for a signal to be sampled at a rate twice the highest frequency component present in the signal. This requires high sampling Analog to Digital Converter (ADC) for measuring high frequency signals like Radio Frequency (RF) signals. Compressed Sensing (CS) is a recently developed samplin...

Compressed sensing-based radio frequency signal acquisition systems call for higher reconstruction speed and low dynamic power. In this study, a novel low power fast orthogonal matching pursuit (LPF-OMP) algorithm is proposed for faster reconstruction of sparse signals from their compressively sensed samples and the reconstruction circuit consumes...

An efficient architecture of Orthogonal Matching Pursuit (OMP) algorithm is proposed to recover signals compressively measured at sub-Nyquist rate. The proposed architecture is implemented on Field Programmable Gate Array (FPGA) for performance validation. In place of matrix factorization based pseudoinverse computation, Gaussian Elimination (GE) i...

A novel hardware architecture of orthogonal matching pursuit (OMP) is presented here, and the test is implemented on a field-programmable gate array (FPGA). The performance is evaluated by taking RADAR pulses that are compressively sampled synthetically using the random modulation preintegrator (RMPI). Basic test signals such as Gaussian pulse and...

The read instability of conventional 6T-SRAM cell has made the 8T-SRAM cell a substitute for high data reliability. But the single ended nature of read operation demands a complete Vdd swing of high capacitive read bit lines leading to large energy consumption. A novel assist technique using charge recycling concept is proposed here which reduces t...

The impact of alpha particle and exposure to cosmic radiation has multifold the existing stability issue associated with modern sub-100 nm SRAM cell design. Noise insertion in the half selected cell of a SRAM array is another serious issue which degrades the stability of a cell as well as waste energy through the half selected cells. The proposed h...

In SRAM cell design, the energy consumption and cell stability are the major performance indices which need to be improved. Several techniques reported earlier attempt to improve either of the stability or the energy consumption. In this paper, a scheme is proposed which uses current starving on conventional SRAM cell to improve cell stability and...

Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumptio...

Blind zone of a phase frequency detector (PFD) enhances the phase noise in a Charge Pump PLL. This paper presents a novel technique to reduce the blind zone which reduces the reference spur as well. In this proposed work a variable delay element is incorporated in the Reset path of the PFD. The overall PFD delay is maintained at a small positive va...

Energy consumption and data stability are vital requirement of cache in embedded processor. SRAM is a natural choice for cache memory owing to their speed and energy efficiency. Noise insertion to the SRAM cell during read is a serious problem which reduces its stability. A read disturbance free differential SRAM cell consisting of seven transistor...

Leakage current contribution to the power consumption cannot be ignored in the sub-100nm technology. Drastic reduction of channel length of the modern highly scaled device enhances the leakage current significantly. Two novel 8T-SRAM cells low-leakage-current SRAM cell (LLC-SRAM cell) and low-leakage-current high-threshold-voltage SRAM cell (LLC-HV...

This paper deals with the development of robust diffusion strategy for wireless sensor networks using minimum-Wilcoxon-norm. The Wilcoxon norm based robust estimation now-a-days has drawn the attention of the signal processing community for its scale equivariant property and simplicity. Exhaustive mathematical analysis has been presented to obtain...

The performance of nanoscale radio frequency integrated circuits (RFIC) is influenced by the circuit parasitics and device dimensions. The present work predicts the design parameters of CMOS ring oscillator (CMOS RO) for its optimal performance and designs the CMOS RO using these parameters in Cadence Virtuoso Analog Design Environment with GPDK 90...

A distributed Block LMS estimate strategy is developed by appealing to collaboration techniques that exploits both space and time structures of data. In diffusion strategies, information are exchanged among the nodes, usually containing noisy links. The weight combination of the neighboring nodes play a crucial role in adaptation and tracking abili...

Address Decoder is an important digital block in SRAM which takes up to half of the total chip access time and significant part of the total SRAM power in normal read/write cycle. To design address decoder need to consider two objectives, first choosing the optimal circuit technique and second sizing of their transistors. Novel address decoder circ...

Charge Pump in a phase locked loop (PLL) generates non-ideal effects such as current mismatches at the output node and switching errors at the pull up and pull down networks. This work presents a novel transmission gate cascode current mirror charge pump circuit. The switches incorporated in this work are Transmission Gates which help to reduce var...

1kb static random access memory (SRAM) is designed and tested for correct read and write operation. Novel Sense Amplifier (SA) circuit for 1kb SRAM are presented and analysed in this paper. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology....

Low power consumption, low phase noise and dead zone free operation are the vital performance parameters in a high performance Phase Locked Loop (PLL). These parameters are tailored by using a variable controlled delay element in the reset path of the Phase Frequency Detector (PFD) of a Charge Pump PLL (CPLL). The overall PFD delay is maintained at...

This paper presents a novel design methodology for design of optimal and robust current starved voltage controlled oscillator (CSVCO) circuit. A recently developed multiobjective optimization technique infeasibility driven evolutionary algorithm is used to minimize the power and the phase noise of the circuit at its schematic and physical level. Th...

Conventionally the integrated circuit designer first carries out the design to achieve the required performance specifications and observes the worst case performance through simulations. If the worst case performance falls well inside the acceptable range then that design is designated as a process variation tolerant design. In such case the desig...

Phase locked loops find wide application in several modern applications mostly in advance communication and instrumentation systems. PLL being a mixed signal circuit involves design challenge at high frequency. This work analyses the design of a mixed signal phase locked loop for faster phase and frequency locking. The PLL is designed in GPDK090 li...

Though CMOS logic inverter is widely appreciated because of its negligible static power consumption still sometimes it is deprecated because of the high dynamic power consumption. The high dynamic power consumption is because of the charging and discharging of the load capacitor and also because of the unwanted short-circuits current from Vdd to gr...

This work presents the design of an inductively source degenerated CMOS Differential Low Noise Amplifier (LNA) operating at 2 GHz. LNA is designed using UMC 0.18 μm technology and simulated in Cadence Spectre_RF tool to validate its performance. Power constrained methodology is used for the design of CMOS Differential Low Noise Amplifier. At 1.8V s...

The k-tier heterogeneous wireless networks (kHWN) deployment focused on the needs of the users. Many challenges exist in integrating kHWN architectures into one seamless flow of voice, data and multimedia. The handoff's between kHWN that allows user equipment (UE) to continuously find seamless connectivity with the transceivers is complex and chall...

CMODE (Combining Multi-objective Optimization with Differential Evolution) technique has been proved to be very efficient to design a low power low phase noise LC Voltage Controlled Oscillator (VCO). The proposed technique optimizes the power consumption and phase noise of the 3.3-4 GHz LC-VCO for GSM-900 standard. The performance indices are optim...

FOM (Figure Of Merit) is a novel performance yardstick of VCOs. Designing LC VCO circuit with desired specifications is highly time consuming and tedious job. In this paper CMODE (Combining Multi objective Optimization with Differential Evolution) optimization technique is used to design an LC VCO of optimal FOM with a target frequency of 2.5 GHz....

The design of optimal analog and mixed signal (AMS) very large scale integrated circuits (VLSI) with lesser design cycle time is a challenging task for the integrated circuit (IC) designers. Voltage Controlled Oscillator (VCO) is a radio frequency integrated circuit (RFIC) having wide range of applications. This paper presents a new approach to des...

The Verification is a vital step of any ASIC development process. 8B/10B encoder is a very widely used block in communication systems. The RTL code of an 8B/10B encoder is simulated in Questasim environment. The 8B/10B encoder is put to formal verification process in this work. Coverage analysis gives a view of the efficiency of the code. The repor...

Presently the design of the optimal analog and mixed signal (AMS) circuits with lesser design cycle time is a great challenge for the designers. This paper describes the optimization of the current starved voltage controlled oscillator (CSVCO) circuit. The objective functions and constraints of the CSVCO circuit are in the form of posynomial functi...

A wide band two stage CMOS voltage controlled ring oscillator (VCRO) based on fully differential delay cells proposed by Yan and Luong has been analyzed. The two stage and three stage VCO circuits are realized using GPDK 90 nm CMOS technology. The design parameters are varied widely and performance of the circuit is evaluated in this work. This sca...

Field programmable gate array (FPGA) is a widely used programmable integrated circuit (IC) for fast realization of digital circuits in all electronic systems. Its reconfigurability has made this mode of digital circuit synthesis more popular among the system designers. But unlike other ICs it provides a restricted hardware structure for circuit imp...

Digital ICs for electronic systems are fast realized on Field programmable gate array (FPGA). The reconfigurability of FPGA has made this mode of digital circuit synthesis more popular among the system designers. But unlike other ICs it provides a restricted hardware structure for circuit implementation and hence the computer aided design (CAD) sof...

Independent component analysis (ICA) technique separates mixed signals blindly without any information of the mixing system. Fast ICA is the most popular gradient based ICA algorithm. Bacterial foraging optimization based ICA (BFOICA) and constrained genetic algorithm based ICA (CGAICA) are two recently developed derivative free evolutionary comput...

Independent Component Analysis, a computationally efficient blind statistical signal processing technique, has been an area of interest for researchers for many practical applications in various fields of science and engineering. The present paper attempts to treat the fundamental concepts involved in the independent component analysis (ICA) techni...

Independent Component Analysis (ICA) technique separates mixed signals blindly without any information of the mixing system. bacterial foraging optimization based ICA (BFOICA) and constrained genetic algorithm based ICA (CGAICA) are two recently developed derivative free evolutionary computational ICA techniques. In BFOICA the foraging behavior of...

The present paper proposes a bacteria foraging optimization based independent component analysis (BFOICA) algorithm assuming a linear noise free model. It is observed that the proposed BFOICA algorithm overcomes the long standing permutation ambiguity and recovers the independent components(IC) in a fixed order which depends on the statistical char...

Independent component analysis, a computationally efficient statistical signal processing technique, has been an area of interest for researchers for many practical applications in various fields of science and engineering. The present paper proposes a constrained genetic algorithm optimization based independent component analysis assuming a noise...

Independent component analysis (ICA) technique separates mixed signals blindly without any information of mixing system. The present work evaluates the error performance of fast ICA and algebraic ICA algorithms for their fixed-point implementations. Simulation study is carried on both fixed and floating point ICAs. It is observed that the word leng...

Abstract-Independent Component Analysis (ICA) technique separates mixed signals blindly without any information of mixing system. The present work studies and analyses the issues involved ininterference rejection in direct sequence spread spectrum

Real world problems very often provide minimum information regarding their causes. This is mainly due to the system complexities and noninvasive techniques employed by scientists and engineers to study such systems. Signal and image processing techniques used for analyzing such systems essentially tend to be blind. Earlier, training signal based te...