Debashish Nandi- PhD
- PMRF at Indian Institute of Technology Kanpur
Debashish Nandi
- PhD
- PMRF at Indian Institute of Technology Kanpur
Pursuing PhD
About
10
Publications
563
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23
Citations
Introduction
My research interest is semiconductor device modelling and Characterization of Nanoscale devices. I am also interested in RFIC and my current research work is primarily focused on modelling of SOI-MOSFETs for Radio Frequency applications in advanced communication standards.
Skills and Expertise
Current institution
Additional affiliations
January 2022 - present
July 2017 - June 2021
Education
July 2013 - June 2017
Publications
Publications (10)
This study proposes improved compact models for impact ionization in the intrinsic and drift regions of Laterally-Diffused-Metal-Oxide-Semiconductor (LDMOS) transistors. These models are rigorously validated across a wide range of high drain and gate voltages for different channel widths, demonstrating their robustness and applicability. The model...
In this work, we have explored the influence of back-gate voltage on the terminal characteristics of Fully Depleted Silicon-On-Insulator (FDSOI) Varactors, which are crucial for RF applications. We characterized 28 nm FDSOI Varactors in terms of both AC and RF performance. Experimental results highlight the significant effect of back-gate voltage o...
In this work, we have explored the influence of back-gate voltage on the terminal characteristics of fully depleted silicon-on-insulator (FDSOI) varactors, which are crucial for RF applications. We characterized 28-nm FDSOI varactors in terms of both ac and RF performance. Experimental results highlight the significant effect of back-gate voltage o...
In this work, we present a physical understanding and a robust surface potential coupling relationship essential to accurately capture the transconductance in body-contacted (BC) dynamically depleted silicon-on-insulator (DDSOI) MOSFETs for varied body biases. It is observed that the crossover of transconductance for varied body biases occurs befor...
In this part, we present a new charge-based symmetric compact model of partially depleted silicon-on-insulator (PDSOI) technology. The model’s core charge calculations are based on the industry-standard Berkeley short-channel IGFET model (BSIM)-BULK platform and fully utilize its speed, robustness, and symmetry properties. Further, the SOI-specific...
In this paper, we present the symmetric BSIM-SOI compact model, tailored for Dynamically Depleted Silicon-on-Insulator (DDSOI) MOSFETs, with a primary focus on optimizing their performance in RF Transmit/Receive (T/R) switch applications. This surface potential-based model offers a comprehensive characterization of device behavior, encompassing bot...
In this article, we present a symmetric surface-potential-based model for dynamic depletion (DD) device operation of silicon-on-insulator (SOI) FETs for RF and analog IC design applications. The model accurately captures the device behavior in partial depletion (PD) and full depletion (FD) modes, as well as in the transition from PD to FD, based on...
In this paper, we present the symmetric BSIM-SOI compact model, specifically designed for Dynamically Depleted Silicon-on-Insulator (DDSOI) MOSFETs, with an emphasis on optimizing their performance in RF Transmit/Receive (T/R) switch applications. This surface potential-based model provides a comprehensive characterization of the device’s behavior,...
