Daniel Llamocca

Oakland University · Department of Electrical and Computer Engineering

The Discrete Periodic Radon Transform (DPRT) has been extensively used in applications that involve image reconstructions from projections. Beyond classic applications, the DPRT can also be used to compute fast convolutions that avoids the use of floating-point arithmetic associated with the use of the Fast Fourier Transform. Unfortunately, the use...

We introduce a dynamically reconfigurable framework for implementing single-pixel operations. The system relies on a multiobjective optimization scheme that generates Pareto-optimal realizations in the power/energy-performance-accuracy (PPA/EPA) spaces. The Pareto-optimal realizations and their PPA/EPA values are stored in DDR-SDRAM and can be chos...

There is strong interest in the development of dynamically reconfigurable systems that can meet real-time constraints on energy, performance, and accuracy. The generation of real-time constraints will significantly expand the applicability of dynamically reconfigurable systems to new domains, such as digital video processing. We develop a dynamica...

The original hyperbolic CORDIC (Coordinate Rotation Digital Computer) algorithm (Walther, 1971) imposes a limitation to the inputs' domain which renders the algorithm useless for certain applications in which a greater range of the function is needed. To address this problem, Hu et al. (1991) have proposed an interesting scheme which increments the...

The Discrete Periodic Radon Transform (DPRT) has been extensively used in applications that involve image reconstructions from projections. This manuscript introduces a fast and scalable approach for computing the forward and inverse DPRT that is based on the use of: (i) a parallel array of fixed-point adder trees, (ii) circular shift registers to...

The manuscript describes fast and scalable architectures and associated algorithms for computing convolutions and cross-correlations. The basic idea is to map 2D convolutions and cross-correlations to a collection of 1D convolutions and cross-correlations in the transform domain. This is accomplished through the use of the Discrete Periodic Radon T...

We present a self-reconfigurable embedded system for a switched beam smart antenna that can steer the beam pattern into a desired direction, handle arithmetic overflow, and respond to user-specified constraints on accuracy and resources. The main component (adaptive beamforming) is implemented as a fully customized hardware in fixed-point arithmeti...

Real-time measurement or estimation of crank-angle-resolved engine cylinder pressure may become commonplace in the next generation of engine controllers to optimize spark, valve timing, or compression ratio. Toward the development of a real-time cylinder pressure estimator, this work presents a crank-angle-resolved engine cylinder pressure estimati...

This work introduces a run-time reconfigurable system for HEVC Forward and Inverse Transforms that can adapt to time-varying requirements on resources, throughput, and video coding efficiency. Three scalable designs are presented: fully parallel, semi parallel, and iterative. Performance scalability is achieved by combining folded/unfolded 1D Trans...

We introduce Dynamic Dual Fixed Point (DDFX) CORDIC, that relies on run-time alteration of the numerical format of the Dual Fixed Point (DFX) CORDIC hardware. This allows for enhanced dynamic range and accuracy. Fixed Point, Dual Fixed Point, Floating Point, and Dynamic Dual Fixed Point CORDIC units are compared in terms of resources and accuracy....

The manuscript describes fast and scalable architecturesand associated algorithms for computing convolutions and cross-correlations. The basic idea is to map 2D convolutions and cross-correlations to a collection of 1D convolutions and cross-correlations in the transform domain. This is accomplished through the use of the Discrete Periodic Radon Tr...

We introduce Dual Fixed Point CORDIC, that provides a compromise between Fixed Point and Floating Point CORDIC hardware implementations. A fully parameterized hardware is presented that allows for extensive exploration of the resources-accuracy design space, from which we generate optimal (in the multi-objective sense) realizations. We compare Fixe...

We present a fixed-point architecture for adaptive beamforming that optimizes resource consumption by utilizing a Look-Up-Table (LUT) approach suitable for FPGA designs. The hardware design is fully customized and allows the user to switch to different beam patterns and adapt hardware resources to requirements on accuracy. Experimental results are...

We present a fixed point architecture (source VHDL code is provided) for powering computation. The fully customized architecture, based on the expanded hyperbolic CORDIC algorithm, allows for design space exploration to establish trade-offs among design parameters (numerical format, number of iterations), execution time, resource usage and accuracy...

This work describes the implementation of a Reconfigurable Computing course for both senior undergraduate students and graduate students. This class provides students with the theory and techniques to design hardware/software systems that can be reconfigured (usually at running time). Students were evaluated in their ability to successfully partiti...

This work presents an architecture for powering computation in floating point arithmetic that is based on an expanded hyperbolic CORDIC algorithm, where the user can select the 2-D domain of convergence that suits their application. The fully parameterized hardware implementation allows us to explore trade-offs among design parameters (numerical fo...

This work presents a novel scalable and fully pipelined digital hardware implementation for a biomimetic vision sensor that mimics the compound eye of the common house fly. The hardware includes IIR filters, FIR filters, and arithmetic units. By employing techniques such as scattered look-ahead decomposition, retiming, and distributed arithmetic, a...

Field-programmable wiring systems refer to methods and hardware that can maintain the interconnection of components of different types. Generally, field-programmable wiring systems support the use of multidomain fabrics that can be used to route analog, power, digital signals, optical, microwave signals, etc. This paper reviews fundamental concepts...

The Discrete Periodic Radon Transform (DPRT) has many important applications in image processing that are associated with reconstructing objects from projections (e.g., computed tomography [1]) or image restoration (e.g., [2]). Thus, there is strong interest in the development of fast algorithms and architectures for computing the DPRT. This paper...

The first prototype of an adaptive wiring panel was recently introduced that implemented a reconfigurable switch fabric that allows dynamic routing of analog, digital, and power signals for space system applications. In this paper, a complete redesign and reimplementation of the adaptive wiring panel system is considered to address issues associate...

We introduce a dynamically reconfigurable 2D filterbank that supports both real and complex-valued inputs, outputs, and filter coefficients. This general purpose filterbank allows for the efficient implementation of 2D filterbanks based on separable 2D FIR filters that support all possible combinations of input and output signals. The system relies...

he paper introduces the Fast Discrete Periodic Radon Transform (FDPRT) which represents a new algorithm and associated architecture for computing Discrete Periodic Radon Transforms. For square images of size p × p, p prime, the Discrete Periodic Radon Transform (DPRT) requires p2(p−1) additions for calculating image projections along a minimal numb...

The High Efficiency Video Coding (HEVC) standard can achieve significant improvements in coding performance over H.264/AVC. To achieve significant coding improvements in intrapredictive coding, HEVC relies on the use of an extended set of intra-prediction modes and prediction block sizes. This paper presents a unified hardware architecture for impl...

Digital systems capable of altering their hardware configuration on the fly are labeled dynamically reconfigurable. Proteus is an OpenRISC-based computer optimized for Xilinx's FPGAs that can dynamically reconfigure itself. Proteus was conceived as a platform to facilitate the study of reconfigurable computing architectures by providing a turn-key...

There is a strong need in the United States to increase the number of students from underrepresented groups who pursue careers in Science, Technology, Engineering, and Mathematics. Drawing from sociocultural theory, we present approaches to establishing collaborations between computer engineering and mathematics/bilingual education faculty to addre...

We present a first approach for developing the concept of a manifold of adaptive wiring cells connected as a single overall adaptive wiring panel. The main use of the adaptive wiring panel is related to affordable plug-and-play space applications, but the concept can be used for different applications. A reconfigurable switch fabric enables dynamic...

We present a dynamic framework for 2D complex filter implementation that is based on a multi-objective optimization scheme that generates Pareto-optimal realizations from the Energy-Performance-Accuracy (EPA) space. The EPA space is created by evaluating the 2D complex filter realizations in terms of their required energy, accuracy, and performance...

We present a framework for the implementation of self-reconfigurable 2D Discrete Cosine Transforms (DCTs). Dynamic Partial Reconfiguration (DPR) and Dynamic Frequency Control lead to a multi-objective optimization scheme that generates Pareto-optimal realizations from the Power-Performance-Accuracy (PPA) space. The PPA space is created by evaluatin...

There is strong interest in the development of dynamically reconfigurable systems that can meet real-time constraints in energy/power-performance-accuracy (EPA/PPA). In this dissertation, I introduce a framework for implementing dynamically reconfigurable digital signal, image, and video processing systems. The basic idea is to first generate a col...

We present a first approach for developing the concept of a manifold of adaptive wiring cells connected as a single overall Adaptive Wiring Panel (AWP). The main use of the AWP is related to affordable plug-and-play space applications but the concept can be used for different applications. A reconfigurable switch fabric enables dynamic routing of s...

Dynamic partial reconfiguration (DPR) allows us to adapt hardware resources to meet time-varying requirements in power, resources, or performance. In this paper, we present two new DPR systems that allow for efficient implementations of 1D FIR filters on modern FPGA devices. To minimize the required partial reconfiguration region (PRR), both implem...

We cast anomalous change detection as a binary classification problem, and use a support vector machine (SVM) to build a detector that does not depend on assumptions about the underlying data distribution. To speed up the computation, our SVM is implemented, in part, on a graphical processing unit. Results on real and simulated anomalous changes ar...

We introduce a novel dynamically reconfigurable 2D filterbank that is based on separable, one-dimensional filters. At the lowest level, each 2D filter is implemented using dynamic reconfiguration between two one-dimensional filters. Then, at a higher level, filterbanks are implemented using dynamic partial reconfiguration of efficient 1D filter blo...

Dynamic Partial Reconfiguration is a technique that allows a portion of the FPGA to be reprogrammed while the rest of the device keeps working, and as such, it offers enormous possibilities for adaptive systems. The usual design flow involves storing the pre-generated partial bitstreams on a flash memory for its further streaming to the FPGA config...

We present a dynamic computing platform that allows for rapid prototyping of image and video processing applications systems. Here, an Ethernet MAC is used to stream video in and out of the FPGA. The output video is also sent to a video port for display. The system features a simple way to specify the dynamic video processing modules that are going...

We introduce an idealized dynamically reconfigurable computing model that is suitable for applications in video processing applications. Dynamically reconfigurable computing is characterized by a dynamic data path which has been made possible with the partial reconfiguration feature available in modern FPGA devices. Dynamically reconfigurable compu...

Many DSP, image and video processing applications use finite impulse response (FIR) filters as basic computing blocks. Our paper introduces an efficient dynamically reconfigurable FIR system that can adapt the number of filter coefficients, and their values, in real time. Here, dynamic reconfiguration is used to switch between different, pre-comput...

We describe a dynamically reconfigurable image processing system that reaches real time video processing performances despite reconfiguration time overhead. The system is composed of reconfigurable pixel processing units set to process several pixels in parallel. We present a scheme for optimizing a LUT-based architecture by directly mapping it int...

The results of ionizing dose rate experiments on XC5VLX50T FPGAs demonstrate the most susceptible upset mechanism of commercial devices and provide insight into the effectiveness of dose rate hardening of nano-scale technology by using epi substrates.

The following paper describes the results of ionizing dose rate investigations into upset, supply photocurrent, latch-up, and burnout susceptibility of the Xilinx Virtex IV XC4VFX12. All investigations were performed on a commercial version of the device. The maximum no-upset dose rate was 2.8times10⁸ rad(Si)/s. Photocurrent amplitudes a...

This work presents a fixed-point hardware implementation of the natural logarithm (ln) function. The natural logarithm approximation is based on a expanded hyperbolic CORDIC algorithm, which allows an efficient mapping of the logarithm function onto a VLSI or FPGA architecture, since the CORDIC algorithm consists in shifts and adds. A low-cost iter...

This work presents an architecture that acquires a set of digitalized signals from an analog radar, performs some processing, send packets of data through a USB interface, and finally, by software, displays the data sent by an analog radar. In this way, the analog radar is converted into a fully operative digital radar at a very small cost. Since t...

A core that obtains a fixed-point square root is presented. The algorithm used has been proposed by Li and Chu [1]. Three types of architecture are presented: a low cost iterative version, a fully pipelined version, and a fully combinatorial version. The user can scale the size of the core, choose the precision bits required and select the architec...