Daniel Gil

• Polytechnic University of Valencia

MBU is an increasing challenge in SRAM memory, due to the chip’s large area of SRAM, and supply power scaling applied to reduce static consumption. Powerful ECCs can cope with random MBUs, but at the expense of complex encoding/decoding circuits, and high memory redundancy. Alternatively, radiation-hardened cell is an alternative technique that can...

During these last years, the use of embedded systems has grown exponentially, mainly due to the expansion of the Internet of Things (IoT). Data collected by IoT devices are sent to the cloud to be processed in datacenters. Edge Computing philosophy wants to change this “passive” behavior of IoT devices. The basic idea is to process data produced by...

Con la continua reducción de tamaño de la tecnología CMOS, la probabilidad de sufrir tanto fallos simples como múltiples en los sistemas de memoria aumenta. Así pues, son necesarios Mecanismos de Tolerancia a Fallos (MTF) que los protejan. Tradicionalmente, se han utilizado diferentes Códigos Correctores de Errores (ECC) para este fin. A la hora de...

Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can dete...

The Bose-Chaudhuri-Hocquenghem (BCH) codes are a well-known class of powerful error correction cyclic codes. BCH codes can correct multiple errors with minimal redundancy. Primitive BCH codes only exist for some word lengths, which do not frequently match those employed in digital systems. This paper focuses on double error correction (DEC) codes f...

Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single error correction-double error detection (SEC-DED) codes. ECCs are traditionally designed to minimize the number of redundant bits, as they are added to each word in the whole memory. Nevertheles...

Durante estos últimos años, el desarrollo tecnológico ha permitido aumentar la escala de integración de los circuitos integrados. En particular, este aumento ha posibilitado la creación de sistemas de memoria de gran capacidad. Sin embargo, también ha provocado un incremento en su tasa de fallos, aumentando la probabilidad de que se produzcan Singl...

Due to the increasing defect rates in highly scaled complementary metal-oxide-semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. Understanding and controlling the fault mechanisms associated with new materials and structures for both transistors and interconnectio...

Nowadays, the probability of occurrence of Single Cell Upsets (SCUs) or Multiple Cell Upsets (MCUs) has increased due to the continuous increment in the integration scale of CMOS technology, that has provoked an augment in the fault rate. SCUs and MCUs are particularly common in computer memory systems. To tolerate errors, it is common the use of E...

Actualmente, y debido al continuo aumento en la escala de integración, la tasa de fallos en los sistemas de memoria de los computadores ha aumentado. Así, la probabilidad de que se produzcan Single Cell Upsets (SCUs) o Multiple Cell Upsets (MCUs) aumenta. Una solución común es el uso de Códigos de Corrección de Errores (ECCs). Sin embargo, cuando s...

Due to the continuous increment in the integration scale, the fault rate in computer memory systems has augmented. Thus, the probability of occurrence of Single Cell Upsets (SCUs) or Multiple Cell Upsets (MCUs) also increases. A common solution is the use of Error Correction Codes (ECCs). However, when using ECCs, a good balance between the error c...

Currently, faults suffered by SRAM memory systems have increased due to the aggressive CMOS integration density. Thus, the probability of occurrence of single-cell upsets (SCUs) or multiple-cell upsets (MCUs) augments. One of the main causes of MCUs in space applications is cosmic radiation. A common solution is the use of error correction codes (E...

New fault tolerant methods are needed to cope with the fault rate augment in memory systems. Traditionally, Error Correction Codes (ECCs) have been used. This Fault-Tolerance method works well with single faults. Nevertheless, the increase of the integration density in current deep submicron chips, as well as the decrease of the energy needed to pr...

As scaling is more and more aggressive, intermittent faults are increasing their importance in current deep submicron complementary metal-oxide-semiconductor (CMOS) technologies. This work shows the dependability assessment of a fault-tolerant computer system against intermittent faults. The applied methodology lies in VHDL-based fault injection, w...

Traditionally, Error Correction Codes (ECC) works with codeword digits exposed to the same error rates. Nevertheless, with the actual height of intermittent faults, it would be interesting to divide a codeword according to possible different error rates. This work summarizes Flexible Unequal Error Control (FUEC) codes. This new codes family divides...

Error correction codes are used in semiconductor memories to protect information against errors. Simple error correction codes are preferred due to their low redundancy and encoding/decoding latency. Hamming codes are simple and can be easily built for any word length. They only allow single error correction, so a multiple error can lead to a wrong...

With the scaling of complementary metal-oxide-semiconductor (CMOS) technology to the submicron range, designers have to deal with a growing number and variety of fault types. In this way, intermittent faults are gaining importance in modern very large scale integration (VLSI) circuits. The presence of these faults is increasing due to the complexit...

Unequal Error Control (UEC) codes provide means for handling errors where the codeword digits may be exposed to different error rates, like in two-dimensional optical storage media, or VLSI circuits affected by intermittent faults or different noise sources. However, existing UEC codes are quite rigid in their definition. They split codewords in on...

The reduction of transistor size dimensions in new technologies has provoked the apparition of new fault types. In this way, intermittent faults present a great challenge, as they are expected to be more and more common. In this work, the effects of intermittent faults in the behavior of a Fault-Tolerant microprocessor are studied. To carry out thi...

Intermittent faults, being serious concerns for deep-submicron integrated circuits, are not well studied in the literature. This paper performs fault injection simulation to analyze the impact of intermittent faults, which is an important step towards the development of mitigation techniques for such threats.

As CMOS technology scales to the nanometer range, designers have to deal with a growing number and variety of fault types. Particularly, intermittent faults are expected to be an important issue in modern VLSI circuits. The complexity of manufacturing processes, producing residues and parameter variations, together with special aging mechanisms, ma...

Intermittent faults are expected to be a great challenge in VLSI circuits. The complexity of manufacturing processes, provoking residues and process variations, and special wear out mechanisms, may increase the presence of such faults. This work presents a case study of the effects of intermittent faults on the behavior of a commercial micro contro...

As technologies shrink, new kinds of faults arise. Intermittent faults are part of these new faults. They are expected to be an increasing challenge in modern VLSI circuits. Up to now, transient and permanent faults used to be injected for the experimental validation of fault tolerance mechanisms. The main objective of this work is to improve the d...

As CMOS technology enters the nanoelectronics realm (tens of nanometres and below), where quantum mechanical effects start to prevail, conventional CMOS devices are meeting many technological challenges for further scaling. This situation has motivated the emergence of a variety of new nanoelectronic devices [1] [2]. However, as new generations of...

It is expected that intermittent faults will be a great challenge in modern VLSI circuits. In this work, we present a case study of the effects of intermittent faults on the behavior of a commercial microcontroller. The methodology used lies in VHDL-based fault injection technique, which allows a systematic and exhaustive analysis of the influence...

Deep submicrometer devices are expected to be increasingly sensitive to physical faults. For this reason, fault-tolerance mechanisms are more and more required in VLSI circuits. So, validating their dependability is a prior concern in the design process. Fault injection techniques based on the use of hardware description languages offer important a...

Nowadays, new submicron technologies have allowed increasing processors performance while decreasing their size. However, as a side effect, their reliability has been negatively affected. Although mainly permanent and transient faults have been studied, intermittent faults are expected to be a big challenge in modern VLSI circuits. Usually, intermi...

Many designers bet on reducing time-to-market costs by integrating off-the-shelf (OTS) cores in their embedded solutions, while looking after maintaining the confidence placed by users in their products. Balancing these aspects is challenging and claims for suitable techniques to select, among eligible candidates, those exhibiting adequate levels o...

Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence in deep-submicrometer manufactured VLSI systems. The dependability assessment of VLSI critical systems is a hot topic that requires further research. Field-programmable gate arrays (FPGAs) have been recently pro posed as a means for speeding-up the faul...

A confident use of deep submicron VLSI systems requires the study of their behaviour in the presence of faults. Field-programmable gate arrays (FPGAs) are being used to conduct this study by means of fault injection in a very fast way. However, FPGA-based fault injection tools are mainly focused on classical faults like stuck-at and bit-flip, and d...

A confident use of deep-submicron VLSI systems requires the study of their behaviour in the presence of faults, which has been traditionally conducted via model-based fault injection techniques. Although field-programmable gate arrays (FPGAs) allows for a fast execution of models, its use to emulate the occurrence of permanent faults in VLSI models...

Advances in circuitry integration increase the probability of occurrence of transient faults in VLSI systems. A confident use of these systems requires the study of their behaviour in the presence of such faults. This study can be conducted using model-based fault injection techniques. In that context, field-programmable gate arrays (FPGAs) offer a...

This work shows that faults affecting the combinational logic embedded in a microcontroller can propagate to register elements and may have an important impact over applications, even in the most favourable case of short transient faults. Using VHDL-based fault injection techniques, we have experienced that the percentage of propagated faults, and...

Fault injection techniques based on the use of VHDL as design language offer important advantages with regard to other fault injection techniques. First, as they can be applied during the design phase of the system, they allow reducing the time-to-market. Second, this type of techniques presents high controllability and reachability. Among the diff...

Modern processors tend to increase the number of registers, being part of them not accessible by the instruction set. Traditionally, the effect of faults in these hidden registers has not been considered during system validation using fault injection. In this paper, a study of the importance of faults in hidden registers is performed. Firstly, we h...

This chapter presents an overview of some principal VHDL simulation-based fault injection techniques. Significant designs and tools, as well as their advantages and drawbacks, are shown. Also, VFIT, a VHDL simulation-based fault injection tool developed by the GSTF (Fault Tolerant Systems Group — Polytechnic University of Valencia) to run on a PC p...

As CMOS technology enters the nanoelectronic realm (tens of nanometers and below), where quantum mechanical effects start to prevail, conventional CMOS devices are meeting many technological challenges for further scaling. This situation has motivated the emergence of a variety of new nanoelectronic devices [1]. All these devices try to achieve a n...

Nowadays, the use of dependable systems is generalising, and diagnosis is an important step during their design. A diagnosis in early phases of the design cycle allows to save time and money. Fault injection can be used during the design process of the system, and using Hardware Description Languages, particularly VHDL, it is possible to accomplish...

This work presents a campaign of fault injection to validate the dependability of a fault tolerant microcomputer system. The system is duplex with cold stand-by sparing, parity detection and a watchdog timer. The faults have been injected on a chip-level VHDL model, using an injection tool designed with this purpose. We have carried out a set of in...

As the use of dependable systems is generalising, their study in early phases of the design cycle is more and more important in order to save time and money. In this work, using a generic VEDL-based fault injection tool, called VFIT (VHDL-Based Fault Injection Tool), we have validated the dependability of a real Fault-Tolerant System using its VHDL...

In this work different VHDL-based fault injection techniques (simulator commands, saboteurs and mutants) have been compared and applied in the validation of a fault-tolerant system. Some extensions and implementation designs of these techniques have been introduced. As a complement of these injection techniques, a wide set of fault models (includin...

This paper presents the prototype of an automatic and model-independent fault injection tool, to be used on an IBM-PC (or compatible) platform. The tool has been built around a commercial VHDL simulator and it is thought to implement different fault injection techniques. With this tool, a wide range of transient and permanent faults can be injected...

In this work it is intended to compare different VHDL-based fault injection techniques: simulator commands, saboteurs and mutants for the validation of fault tolerant systems. Some extensions and implementation designs of these techniques have been introduced. Also, a wide set of non-usual fault models have been implemented. As an application, a fa...

Three different VHDL-based fault injection techniques have been compared to validate a fault tolerant micro- computer system. We have studied the error pathology, their detection and recovery coverages and their latencies.

Nowadays, cache memories are applicable to real-time systems with the help of tools that obtain the worst-case execution time (WCET) of cached programs. However, these tools do not allow preemption, because from the point of view of program analysis, the number of preemptions is unknown. To face this problem, the cache-related preemption cost can b...

This work presents a campaign of fault injection to validate the dependability of a fault tolerant microcomputer system. The system is duplex with cold stand-by sparing, parity detection and a watchdog timer. The faults have been injected on a chip-level VHDL model, using an injection tool designed for this purpose. We have carried out a set of inj...

This paper presents the prototype of an automatic and model-independent fault injection tool, to use on an IBM-PC (or compatible) platform. The tool has been built around a commercial VHDL simulator. With this tool, both transient and permanent faults, of a wide range of types, can be injected into medium-complexity models. Another remarkable aspec...

This work presents a campaign of fault injection to validate the dependability of a fault tolerant microcomputer system. The system is duplex with cold stand-by sparing, parity detection and a watchdog timer. The faults have been injected on a chip-level VHDL model, using an injection tool designed with this purpose. We have carried out a set of in...

This paper presents the results of fault injection experiments to analyse the error syndrome of a microcomputer system. The faults have been injected at chip-level in VHDL models, using an injection tool designed with this purpose. We have carried out a set of injection experiments. Transient faults has been injected (stuck-at and open-line) on bot...

Reconfigurable architectures represent a promising option for tolerating the extremely high defect and failure rates of emerging nanodevices. Different approaches have been devised throughout the years for coping with the occurrence of defects and faults in Field-Programmable Gate Arrays (FPGAs). However, due to the expected defect and fault rates,...

Many designers bet on reducing time-to-market costs by integrating off-the-shelf (OTS) cores in embedded systems. However, only those cores exhibiting adequate dependability levels are suitable candidates for system integration. Hence, the development of benchmarking techniques supporting the evaluation and comparison of hardware OTS cores accordin...

It is widely acknowledged that nanoelectronic devices will suffer from more manufacturing and operational faults than classical CMOS devices in large-scale integrated circuits. The confident use of these emerging technologies relies on our capacity to better understand their fault mechanisms, and our ability to deduce related fault models. These ch...