Dan Mocuta

• Manager at imec

This article reports Si-passivated Ge nFinFETs with significantly improved Gm <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> /SS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> and positive bias temperature instability (PBTI) reliabili...

We compare the contact characteristics for Mo, Pd, and Ti on n-InGaAs layer with a range of active donor concentration from 1.6 × 1018 cm-3 to 4.8 × 1019 cm-3. The Fermi level pinning of 0.18 eV lower than the bottom of n-InGaAs conduction band is experimentally manifested. It is also revealed that the contact resistivity (ρc) of Mo/n-InGaAs contac...

Presence of a native oxide interlayer degrades seriously the contact resistivity (ρc) of co-deposited TiSi (CD-TiSi) on Si:P. The oxide cannot be scavenged by the CD-TSi due to its low solid solubility of O. We tackle the problem by capping the CD-TiSi with an O gettering cap. Utilizing a Ti cap and two-step post-metal rapid thermal anneal, we redu...

For the first time, we establish a fabrication process flow of an EUV-era ultra-density 6-surrounding-gate-transistor SRAM with 0.0205 μm2 unit cell area and demonstrate nMOS surrounding-gatetransistor function. In this paper, 6-surrounding-gate-transistor SRAM design layout is shown, and the fabrication process flow and key process steps are expla...

An ultra-thin (15 nm) InGaAs nanomembrane field-effect phototransistor is transferred entirely from a rigid InP substrate onto a flexible SU-8 on a polydimethylsiloxane substrate. The transferred InGaAs device exhibits wide-band spectral response tunability up to 1.8 µm, from the visible to near-infrared light. Using an epitaxial lift-off process o...

We address RC scaling trends and predict the performance benefits of advanced metallization options with respect to conventional Cu/low-k interconnects. The range of interconnect dimensions we cover spans from the 22 nm to the 3 nm logic technology node. We show that Ru and Co fills can significantly reduce resistance at narrow pitches. At 12 nm ha...

Nanowires (NW) and nanosheets (NS) are promising channel structure for future technology nodes as they can offer better electrostatics than FinFETs. In this paper, we show another advantage of strained Ge NW pFET over strained Ge FinFET, which lies in the preservation of Strain-Relaxed-Buffer (SRB)-induced strain through fin cut and S/D recess. Thi...

Through recent advances, the relevance of magnetic tunnel junctions (MTJs) to the microelectronics industry continues to rise. However, their reversal speed still suffers from incubation delay, a consequence of the collinear magnetization equilibrium states in perpendicularly magnetized MTJs (p-MTJs). We propose to tune the free layer in a Co−Fe−B/...

In this paper, high temperature Phosphorus ion implantation is applied to p-type Si (1 0 0) substrates and n-type bulk Si fin field-effect-transistors. Phosphorus profiles and sheet resistance on p-type Si (1 0 0) substrates are analyzed. High temperature ion implantation shows less Phosphorus diffusion after rapid thermal annealing compared to roo...

This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: the Q factor is increased to 25 as compared to our previous work, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...

3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for...

This paper reports on gate-all-around (GAA) silicon (Si) nanowire (NW) field-effect transistors (FETs) built in a lateral configuration, which represent the ultimate scaling limit of triple-gate finFET devices and allow a less disruptive CMOS scaling path in terms of processing and circuit layout design. We address several of their critical technol...

In this work, we discuss how the insertion of a LaSiO x layer in between an in-house IL passivation layer and the high-k has moved the III-V gate stack into the target window for future technology nodes. The insertion of this LaSiO x layer in the gate stack has reduced the D it and N bt below the target level of 5x10 ¹¹ /eV.cm ² and 3x10 ¹⁰ /cm ² (...

The development of low-power spintronic computation would open new paths for advanced logic nodes. It could utilize a ferromagnetic free layer shared by multiple magnetic tunnel junctions to cascade spin-coherent information. The basic component of this device would be a magnetic tunnel junction with an extended free layer. Here, we study the magne...

2-D transition metal dichalcogenides (TMDs) are promising materials for CMOS application due to their ultrathin channel with excellent electrostatic control. TMDs are especially well suited for tunneling field-effect transistors (TFETs) due to their low-dielectric constant and their promise of atomically sharp and self-passivated interfaces. Here,...

This paper proposes a La/ultrathin TiSiₓ metallic bilayer contact (MBC) on moderately doped n⁺-Si, which can simultaneously reduce contact resistivity (ρc) and at the same time improve the contact thermal endurance. In such an MBC, the top La defines the work function (WF), whereas the ultrathin (~ 1 nm) TiSiₓ (WF-transparent) interlayer acts as a...

With the rapid progress of spintronic devices, spin-logic concepts hold promises of energy-delay conscious computation for efficient logic gate operations. We report on the electrical characterization of domain walls in interconnected magnetic tunnel junctions. By means of spin-transfer torque effect, domains walls are produced at the common free l...

Ga diffusion and activation in Si, Si0.4Ge0.6 and Ge are studied comprehensively. Optimal Ga activation conditions for Si0.4Ge0.6 and Ge feature a low thermal budget: Ga is highly activated at 400oC in Ge and at 500oC in Si0.4Ge0.6 using a 1min rapid thermal annealing (RTA); the activation is further boosted using short-duration high-temperature na...

Magnetic tunnel junctions (MTJs) interconnected via a continuous ferromagnetic free layer were fabricated for Spin Torque Majority Gate (STMG) logic. The MTJs are biased independently and show magnetoelectric response under spin transfer torque. The electrical control of these devices paves the way to future spin logic devices based on domain wall...

Magnetic tunnel junctions (MTJs) interconnected via a continuous ferromagnetic free layer were fabricated for Spin Torque Majority Gate (STMG) logic. The MTJs are biased independently and show magnetoelectric response under spin transfer torque. The electrical control of these devices paves the way to future spin logic devices based on domain wall...

In this letter, the contact properties and thermal stability of TiN/Ti/p+-Si0.3Ge0.7 contacts are investigated. We demonstrate that the insertion of an ultra-thin Ti interlayer is necessary to reduce the contact resistivity (ρc) as compared to a standard TiN/p+-Si0.3Ge0.7 direct contact. However, the Ti interlayer has to be thin enough to avoid deg...

Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single horizontal Ge nanowire (NW) devices are demonstrated, the process flow described in this paper can be adjusted to make vertically stacked horizontal Ge NWs t...

We present recent progress towards the experimental realization of Spin Torque Majority Gate (STMG) devices with a focus on the integration of interconnected magnetic tunnel junctions (MTJs) sharing a common ferromag-netic free layer (FL). We have implemented an ion beam etching (IBE) approach for MTJ patterning and show results utilizing e-beam li...

Over the past decades, aggressive and continuous transistor scaling according to Moore’s law has enabled new system features thanks to ever increasing device performance and density, reduced cost and power consumption. To keep the industry’s growth rate, triple-gate finFETs were recently implemented into manufacturing at the 22nm technology node [1...

The continuous scaling of CMOS devices requires new process developments because of the strong reduction of the allowable thermal budget for device processing. This is especially the case for narrow FinFET structures and vertically stacked MOSFET devices. New epitaxial growth schemes using higher order precursors are being assessed to enable epitax...

We report on gate-all-around (GAA) N- and P-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24...

Gate-all-around (GAA) transistors based on vertically stacked horizontal nanowires are promising candidates to replace FinFETs in future CMOS technology nodes. First of all, GAA devices provide optimal electrostatic control over semiconducting nanowire channels, which enables downscaling of the gate length to below the FinFET limit, while maintaini...

InGaAs homojunction Tunnel FET devices are demonstrated with sub-60 mV/dec Sub-threshold Swing (SS) measured in DC. A 54 mV/dec SS is achieved at 100 pA/μm over a drain voltage range of 0.2-0.5 V. The SS remains sub-60 mV/dec over 1.5 orders of magnitude of current at room temperature. Trap-Assisted Tunneling (TAT) is found to be negligible in the...

With the continued scaling of CMOS devices below the 10 nm node, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons for example to a...

Special MRAM session

We demonstrate a Si-passivated Ge nMOS gate stack with Dit of ∼5×10 10 cm −2 eV −1 around midgap and unnoticeable C-V hysteresis at an operating condition (oxide trap density of ∼1×10 8 cm −2 at V ov /CET=3.5 MV/cm). Insertion of a 3D-compatible thin ALD LaOx, MgOx and LaSiO layer at the interface between HfO2 and SiO2/Si/Ge improves PBTI reliabili...

We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices. The Vt setting is enabled by nanowire-compatible dual-work-function metal integration in a high-k last replacement metal gate process. Furthermore, we demonstrate that...

We report on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer promising opportunities to enable further CMOS scaling and increased circuit layout efficiency. They allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby le...

As contact resistance becomes a bottle-neck in scaled CMOS devices, there is a need for source/drain epitaxy with maximum dopant concentrations and optimized contacting schemes. In this paper we discuss the use of highly doped Si:P layers for the Source/Drain formation in Si bulk FinFETs. We report on the macroscopic and microscopic properties of t...

For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects is required without ON-state current degradation. In this letter, solid-source doping for channel doping using 1-nm phosphosilicate glass was demonstrated on both p-type (100) Si substrate and p-type bulk Si FinFET. The profile of phosphorus in p-type...

In this paper, we illustrate how high resolution two-dimensional (2D) carrier maps obtained from scalpel scanning spreading resistance microscopy (s-SSRM) can be applied to calibrate a technology computer aided design (TCAD) simulator in order to predict and understand the performance of sub-10nm WFIN FinFETs. In the proposed approach, process simu...

As CMOS transistors are scaled down beyond N10, the metal/semiconductor contact resistance becomes a dominant contributor to the total parasitic resistance of the FinFET or Nanowire FET. The utilization of highly-P doped Si:P for the selective source/drain epitaxy was previously shown to be a key enabler to achieve a low contact resistivity in comb...

We investigate the impact of wire geometry on the resistance, capacitance, and RC delay of Cu/low- $k$ damascene interconnects for fixed line-to-line pitch. The resistance is computed by applying a semiempirical resistivity model, calibrated to Cu damascene wires, integrated with a Ru-based liner, currently investigated for the 7 nm logic technolog...

This work reports on vertical nanowire FET devices (VNWFETs) which offer new, promising opportunities to enable further CMOS scaling and increased layout efficiency. Compared to triple-gate finFETs or lateral NWFETs, these devices have the potential for lower parasitic RC and reduced power consumption at 5nm node design rules. They also allow up to...

We modeled the electrostatic doping in multilayer graphene interconnects by self consistently solving Poisson’s equation and we computed the resistivity per layer by accounting for acoustic and optical phonon scattering. For the analysis, we used two different doping concentrations, representative for graphene on top of hexagonal Boron Nitride and...

Over the past decades, aggressive and continuous transistor scaling according to Moore’s law has provided ever increasing device performance and density. For advanced (sub-)5nm nodes, to keep the growth pace, several options can be considered in terms of material choices, device architectures and circuits design. However, further cells scaling usin...

We demonstrate a NMOS Si Bulk-FinFET with extension doped by Phosphorus doped Silicate Glass (PSG). Highly doped PSG (6e21 cm−3) was used as a diffusion source. SiO2 cap on PSG decreased sheet resistance (Rs) due to less out diffusion of P. Even when thin SiO2 exists at the interface between Si and PSG, P diffused from PSG into Si. Thanks to the hi...

Silicon crystallizes in the diamond-cubic phase and shows only a weak emission at 1.1 eV. Diamond-hexagonal silicon however has an indirect bandgap at 1.5 eV and has therefore potential for application in opto-electronic devices. Here we discuss a method based on advanced silicon device processing to form diamond-hexagonal silicon nano-ribbons. Wit...

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time on high density 45nm Fin pitch using a replacement channel approach on Si substrate. In comparison to our previous work on isolated sGe FinFETs [1], 14/16nm technology node compatible modules such as replacement metal gate and germanide-free local interconnect we...

We demonstrate Si-cap-free SiGe p-channel FinFETs and gate-all-around (GAA) FETs in a replacement metal gate (RMG) process, for Ge contents of 25% and 45%. We show that the performance of these devices is substantially improved by high-pressure (HP) deuterium (D 2 ) anneal, which is ascribed to a 2x reduction in interface trap density (D IT ). Furt...

We compare As and P extension implants for NMOS Si bulk FinFETs with 5nm wide fins. P implanted FinFETs shows improved I ON , +15% with Room Temperature (RT) ion implantation (I/I) and +9% with hot I/I, keeping matched Short Channel Effects (SCE) for gate length (L G ) of 30nm compared with As implanted FinFETs. Based on TCAD work, P increases acti...

A novel RMG process in which the n-type work function metal (nWFM) is deposited first and then selectively removed from the pMOS devices is presented for the first time. The key benefit of this nMOS 1 st process lies in increased gate-fill space which results in about 10× improvement in the pMOS effective gate resistivity at gate lengths (L G ) aro...

The Fin-FET Technology scaling to sub 7nm node, using 193 immersion scanner is restricted due to reduced margins for process. The cost of the process and complexity of designs is increasing due to multi-patterning to achieve area scaling using 193i scanner. In this paper, we propose a two Fin-cut mask design for Fin-pattering of 112 SRAM (two Fins...

Both MOL PC-CA spacer dielectric and BEOL low-k dielectric breakdown data are commonly convoluted with multiple variables present in the data due to the involvement of many process steps such as lithography, etch, CMP, cleaning, and thin film deposition. With the continuing aggressive scaling of device dimensions and introduction of new device conf...

The minimum insulator spacing between the polysilicon control gate (PC) and the diffusion contacts (CA) in advanced VLSI circuits is aggressively shrinking due to continuous technology scaling. Meanwhile, rapid adoptions of new materials such as metal gate, epitaxial SiGe source /drain, stress liner, and copper contact together with new device conf...

This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 mum². V_min operation down to 0.6 V in a 16 Mb SRAM array test vehicle has been demonstrated. Aggressive ground rules are achieved with 193 nm immersion lithography. High performance is enabled by high-k/metal gate plus inn...

For the first time, embedded Si:C (eSi:C) was demonstrated to be a superior nMOSFET stressor compared to SMT or tensile liner (TL) stressors. eSi:C nMOSFET showed higher channel mobility and drive current over our best poly-gate 45 nm-node nMOSFET with SMT and tensile liner stressors. In addition, eSi:C showed better scalability than SMT plus tensi...

Dual stress liner process for high performance SOI CMOS technology at 32 nm technology node is improved through the use of dep-etch-dep, etch back, and spacer removal techniques. The stress benefit of DSL is preserved with improved gap fill for the manufacturing of sub-32 nm gate length transistors.

This paper discusses the fundamental challenges and reports the recent progress in enabling embedded Si:C (eSi:C) nMOS source/drain stressor technology. A thick oxide (SiON, Toxgl ~ 26Aå) long channel (Lgate in the range of 80nm-110nm, gate-pitch =336nm) nMOS device was used as the main test structure to evaluate the impact of eSi:C stressor to the...

The device characteristics and manufacturability of ultra-thin oxynitride have been systemically studied in this paper for CMOS applications. We have found that the transistor with plasma oxynitride gate dielectrics gives better pFET performance in terms of drive current, mobility, threshold voltage and leakage current as compared to the one with t...

A test structure specifically designed to allow inline detection of missing spacer is introduced. Missing spacer is too small to be physically detected with any current inspection tool and therefore its existence must be flagged using voltage contrast for detection with an e-beam inspection system. The structure and methodology used to address this...

A test structure specifically designed to allow in-line detection of missing spacer is introduced. Missing spacer is too small to be physically detected with any current inspection tool and therefore its existence must be flagged using voltage contrast for detection with an e-beam inspection system. How this structure and methodology were used to a...

A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to e...

We report, for the first time, a detailed study of intra-die variation (IDV) of CMOS inverter delay for the 65nm technology, driven by mm-scale variations of rapid thermal annealing (RTA). We find that variation in V_T and R_EXT accounts for most of the IDV in delay and leakage and is modulated by lamp RTA ramp rate. We show a g...