Chanro Park

A device and a method to produce an augmented-laser (ATLAS) comprising a bi-stable resistive system (BRS) integrated in series with a semiconductor laser. The laser exhibits reduction/inhibition of the Spontaneous Emission (SE) below lasing threshold by leveraging the abrupt resistance switch of the BRS. The laser system comprises a semiconductor l...

A method for fabricating a semiconductor device includes selectively etching one or more of a plurality of conductive layers within a metallization level to obtain one or more recessed conductive layers each corresponding to a conductive line lacking a via disposed thereon and at least one conductive line having a via disposed thereon. The metalliz...

A method of fabricating a semiconductor device is described. The method includes forming a stack of sacrificial layers on a substrate. A U-shaped trench is formed in the stack of the sacrificial layers. A first U-shaped channel layer is deposited in the U-shaped trench. A first U-shaped sacrificial layer is conformally formed covering the U-shaped...

A system and method of fabricating a semiconductor device include forming a series of gates, and forming a gate spacer on each side of each gate of the series of gates. The method includes forming a source region on a side of each of the gates and forming a drain region on an opposite side of each of the gates. The source region or the drain region...

An integrated semiconductor device having a gate structure adjacent to a semiconductor body at a channel region, the channel region being positioned laterally between source/drain regions. Metal plugs are on the source/drain regions, and rectangular-shaped or trapezoidal-shaped plug caps are above and immediately adjacent to the metal plugs. A self...

Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack can include one or more fi...

Embodiments of the present invention are directed to forming a wrap-around contact (WAC) for a vertical field effect transistor (VFET). In a non-limiting embodiment of the invention, a top spacer is formed on a surface of a gate. A sacrificial spacer is formed on the top spacer. A source/drain region is formed over the top spacer and between sidewa...

A gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes nanosheets, a gate around center portions of the nanosheets, and inner spacers aligned below end portions. The nanosheet end portions are tapered from the source/drain regions to the gate and the inner spacers are tapered from the gate to the source/drain regions. Ea...

Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a non-planar channel region is formed having a first semiconductor layer, a second semicondu...

A device including a substrate and at least one fin formed over the substrate. At least one transistor is integrated with the fin at a top portion of the fin. The transistor includes an active region comprising a source, a drain and a channel region between the source and drain. A gate structure is formed over the channel region, and the gate struc...

We report an improved air spacer (AS) integration scheme to overcome problems with the conventional AS process. The new scheme is fully compatible with other emerging CMOS technology elements such as self-aligned contact (SAC) and contact over active gate (COAG). Using a fan-out3 (FO3) ring oscillator (RO) on a 10-nm FinFET platform, we experimenta...

The present disclosure generally relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers; contacts connecting to at least one gate structure of the plurality of gate structures; and at...

A device is disclosed that includes an active layer, a gate structure positioned above a channel region of the active layer and a first sidewall spacer positioned adjacent the gate structure. The device also includes a gate cap layer positioned above the gate structure and an upper spacer that contacts sidewall surfaces of the gate cap layer, a por...

Methods of forming a field-effect transistor and structures for a field effect-transistor. A sidewall spacer is formed adjacent to a sidewall of a gate structure of the field-effect transistor and a dielectric cap is formed over the gate structure and the sidewall spacer. A cut is formed that extends through the dielectric cap, the gate structure,...

A method for forming a silicon structure. The method includes forming a trench silicide contact between two spacers, each spacer beside respective high-k metal gates. The method planarizes the trench silicide contact, the spacers, and the high-k metal gates. An inner layer dielectric is deposited over the trench silicide contact, the spacers, and t...

A system and method of fabricating a semiconductor device include forming a series of gates, and forming a gate spacer on each side of each gate of the series of gates. The method includes forming a source region on a side of each of the gates and forming a drain region on an opposite side of each of the gates. The source region or the drain region...

A method includes forming an active layer, forming a gate structure above a channel region of the active layer, forming a sidewall spacer adjacent the gate structure, forming a first dielectric layer adjacent the sidewall spacer, recessing the gate structure to define a gate cavity, forming an inner spacer in the gate cavity, forming a cap layer in...

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented t...

One illustrative method disclosed herein includes forming a patterned hard mask layer comprised of a plurality of discrete openings above a structure, wherein the patterned hard mask layer is comprised of a plurality of intersecting line-type features, forming a patterned etch mask above the patterned hard mask layer that exposes at least one, but...

One illustrative method disclosed herein includes the steps of performing a directed self-assembly process to form a DSA masking layer, performing at least one process operation to remove at least one of the features of the DSA masking layer so as to thereby define a patterned DSA masking layer with a DSA masking pattern, performing at least one pr...

Integrated circuits and processes for forming integrated circuits are provided. An exemplary process for forming an integrated circuit includes providing a substrate including an oxide layer and a protecting layer disposed over the oxide layer. A recess is etched through the protecting layer and at least partially into the oxide layer. A barrier ma...

An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the ga...

Disclosed herein are various methods of forming copper-based conductive structures on semiconductor devices, such as transistors. In one example, the method involves performing a first etching process through a patterned metal hard mask layer to define an opening in a layer of insulating material, performing a second etching process through the ope...

EUV Lithography is aimed to be inserted into mainstream production for sub-20nm pattern fabrication. Unlike conventional optical lithography, frequent defectivity monitors (adders, repeaters etc.) are required in EUV lithography. Due to sub-20nm pattern and defect dimensions e-beam inspection of critical pattern areas is essential for yield monitor...

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V...

For the metal gate patterning of metal gate/high-k dielectric complementary metal–oxide–semiconductor field effect transistors (CMOSFETs), plasma induced damage (PID) was identified during the etching by a conventional reactive ion etching (RIE) and, a neutral beam etching (NBE) technique. NBE uses reactive radical beam instead of reactive ions for...

Atomic layer etching (ALE) has been applied to the high-k dielectric patterning in complementary metal–oxide–semiconductor field effect transistors (CMOSFETs), and its electrical characteristics were compared with those etched by conventional etching such as wet etching (WE) or reactive ion etching (RIE). The CMOSFET etched by the ALE showed the im...

Directed Self-Assembly (DSA), as an extension of current state-of-the-art photolithography, has demonstrated the capability for patterning with resolution and cost effectiveness beyond the capability of other techniques. Previous studies of DSA have reported encouraging benchmarks in defect density and throughput capability for the patterning step,...

The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the module targets and challenges for III-V materials to be successfully integrated for high performance/low power logic at or beyond the 11 nm technology node. A VLSI compatible, self-aligned, III-V on...

Metal gate/high-k LSTP CMOSFETs for sub-32nm technology was demonstrated using a novel-damage free neutral beam-assisted atomic etching process. Due to its neutralized atomic flux and chemical reaction, it had a high etch selectivity, oxygen concentration control and improved device performance/reliability. NBALE is a key process for reducing GIDL...

Polarization degradation due to metal etch and/or photoresist(PR) strip processes has been investigated for Pt/SrBi 2 Ta 2 O 9 (SBT)/Pt ferroelectric capacitors. Interconnect metal line consisting of TiN/Al/Ti/TiN/Ti layers has been patterned by normal photolithography and plasma etch processes. We used two different sources for metal etcher, helic...

Lead-Zirconate-Titanate (PZT) films were etched with CF4/Ar mixed gases in high-density plasmas. Etch characteristics of the PZT film were investigated by using in-situ plasma diagnostic tools in conjunction with the surface analysis after etching. Densities of ionic species such as F+ and CFx+(x=1 approx. 3) and their ion energy distributions with...

Si-tunneling field effect transistors (TFETs) with a record I_on >100 μA/μm and high I_on/I_off ratio (> 10⁵) at V_ds=1V are reported. Using an optimal spike and millisec flash anneal coupled with an engineered source-gate overlap through a gate-last process, Si TFETs have been demonstrated with 10...

For the first time, we propose and experimentally demonstrate a novel single-transistor(1T) DRAM: Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM). The memory operation is obtained by engineering the body of the transistor with CTs by creating intentional electron-trapping zones. This memory makes use of charge traps and uses the exist...

Interfacial interactions at graphene/metal and graphene/dielectric interfaces are likely to profoundly influence the electronic structure of graphene. We present here the first angle-resolved near-edge X-ray absorption fine structure (NEXAFS) spectroscopy study of single- and bilayered graphene grown by chemical vapor deposition on Cu and Ni substr...

We demonstrate best in class performance for MANOS-type charge-trap flash non-volatile memory devices through improved program/erase (P/E), endurance and retention. Band-engineered (BE) tunnel-oxides (TO) and BE-SiN_x charge-trap layers are employed to optimize program, erase, and endurance with trade-off in retention. However, for the 1s...

For the first time, a novel damage-free neutral beam-assisted atomic etching process has successfully demonstrated the removal of the residual high-k dielectric layer after gate patterning. Due to its neutralized atomic flux and chemical reaction, high etch selectivity is observed to improve device performance and reliability. This process should s...

Quadratic voltage coefficient of capacitance (VCC) for ZrO ₂– SiO ₂ multilayered dielectric metal-insulator-metal capacitors depends strongly on the stacking sequence of the layered dielectrics. The quadratic VCC of an optimized SiO ₂/ ZrO ₂/ SiO ₂ stack and ZrO ₂/ SiO ₂/...

We demonstrate for the first time molybdenum based oxygen-bearing electrodes for improved performance in MANOS (Metal-Alumina-Nitride-Oxide) charge-trap NVM, and also MIM-DRAM type devices. The meta-stable high work- function (Wfn) molybdenum-oxynitride (MoON) electrodes result in improved retention and erase saturation for the charge trap NVM devi...

The simultaneous improvement in the erase and retention characteristics in a TANOS (TaN-Al₂O₃-Si₃N₄-SiO₂-Si) flash memory transistor by utilizing the band-engineered and compositionally graded SiN_x trap layer is demonstrated. With the process optimizations, a > 4V memory window and e...

This paper presents results on nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32 nm LSTP and HP applications. The 32 nm gate length transistors exhibit an excellent Ion-Ioff characteristic, and the PBTI results meet the 32 nm technology node requirement. Furthermore, for the first time, Vt variation in the La-dope...

The effects of chlorine plasma treatment on HfSiON gate dielectrics were investigated with respect to device performance and reliability characteristics. The chlorine plasma treatment was performed on atomic layer deposited HfSiON films to remove the residual carbon content. The optimal chlorine plasma treatment is shown to lower gate leakage curre...

Band engineering in TANOS (TaN-Al₂O₃-Si₃N₄-SiO₂-Silicon) Flash memory utilizing an interfacial dipole is demonstrated for the first time. A dipole layer at the tunnel oxide/charge storage layer interface leads to increase in programming speed while maintaining good retention and endurance. Usin...

A metal/high-k gate stack with P-type band edge effective work function (EWF) of 5.1-5.2 eV is achieved through optimization of a Ru-Al based metal electrode. The critical factors controlling the high EWF values are found to be Al incorporation at the high-k/SiO₂ interface and stabilization of the conductive RuO₂ layer at the...

We demonstrate an amorphous higher-k (k>20) HfTiSiON gate dielectric for sub 32 nm node capable of low equivalent oxide thickness (EOT=0.84 nm). For the first time, we have addressed the thermodynamic instability of TiO₂ containing gate dielectrics achieving an acceptably thin SiO_x interface (0.7 nm) after 1070degC. 3-10times...

As MOSFET scales below 45nm, conventional SiO2 cannot sustain equivalent oxide thickness (EOT) and leakage current requirements set in the International Technology Roadmap for Semiconductors (ITRS), due to the limitation of physical-thickness scaling, and high tunneling current [1]. Metal gate and high-k dielectric have been extensively studied to...

We have investigated the effects of acceptor and donor doping on the leakage current behavior of Pt/(Ba0.5Sr0.5)TiO3/Pt film capacitors prepared by a pulsed-laser deposition method. We selected Mn/Al and Nb as acceptor and donor dopants, respectively. The leakage current behavior depends strongly on the type of dopants. Al doping decreases the leak...

Using a pulsed-power inductively coupled plasma technique, etching characteristics for a SiO₂ film were investigated and applied to control the ferroelectric performance degradation induced by plasma etching when a ferroelectric capacitor structure is built to make a FeRAM device. It was found that the pulsed-power plasma helps to effect...

The effects of reactive ion etching damage on the electrical properties of Pt/SBT/Pt capacitors have been investigated. The plasma treated SBT/Pt layers showed a significant decrease in remanent polarization compared with that of the reference sample. The remanent polarization of the plasma treated layers varied with the gas ratios of the Cl2/Ar pl...

The formation of self-assembled nanoscale GaAs islands on AlGaAs is demonstrated through the low-temperature molecular beam epitaxy combined with the droplet epitaxy. During the growth of GaAs on the (1×1) surface of AlGaAs layer, spotty feature with 111 streaks was observed in the electron diffraction pattern and the resulting nanometer-scale GaAs...

We report the direct formation of self-assembled GaAs/AlGaAs quantum dots by low-temperature molecular beam epitaxy. To drive a three dimensional growth mode, the (1×1) AlGaAs surface was exposed alternately to the Ga and As sources. The resulting GaAs nanocrystals having {111} facets were clearly identified by high-resolution transmission electron...

The fabrication of nanometer-scale GaAs dots on AlGaAs layer by molecular beam epitaxy was demonstrated. Unlike the stress-driven transition of the three-dimensional growth mode in the lattice-mismatched system, the limited migration of Ga droplets on the AlGaAs layer grown at low substrate temperature was exploited to give rise to the formation of...

InGaAs/GaAs superlattice was grown by molecular beam epitaxy (MBE) on GaAs (100) substrate at low substrate temperature (250�C). The as-grown superlattice sample was then annealed at various temperatures for 10 min. The as-grown superlattice was pseudomorphic and stable up to 800�C annealing. Annealing at 850�C or higher temperatures, however, caus...