
Chandan Kumar Sarkar- D. Phil PhD
- Professor at Jadavpur University
Chandan Kumar Sarkar
- D. Phil PhD
- Professor at Jadavpur University
About
518
Publications
69,670
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5,775
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Introduction
Current institution
Additional affiliations
May 1999 - present
February 1996 - May 1999
June 1987 - February 1996
Education
May 1983 - June 1984
June 1980 - May 1983
July 1975 - July 1979
Publications
Publications (518)
Acousto‐optics deals with the studies of interaction between sound waves and light waves; fundamentally, the diffraction of laser light by sound through an ultrasonic grating. By and large, this effect is based on the variation of the refractive index of a medium in which a sound wave is present. The adjustment of the refractive index because of va...
Nanoelectronics: Physics, Materials and Devices addresses the concepts involved in the exploration of research on nanoscale electronics and photonic devices and their application in next discussion on the field of nanoscale electronic and most recent techniques for the modeling and simulation of these devices. It provides an in device operation, co...
In this paper, analytical modeling of a Dielectric Modulated Double Gate Field Effect Transistor (DM-DGFET) for biosensing application is presented with extensive data analysis. Firstly, the size of the nanogaps and arrangements of biomolecules in those gaps are optimized with respect to the sensitivity of the above sensor. The optimized DM-DGFET i...
In this paper, analytical modeling of a Dielectric Modulated Double Gate Field Effect Transistor (DM-DGFET) for biosensing application is presented with extensive data analysis. Firstly, the size of the nanogaps and arrangements of biomolecules in those gaps are optimized with respect to the sensitivity of the above sensor. The optimized DM-DGFET i...
This paper presents the compact analytical model of underlap gate stack (GS) graded channel (GC) junction accumulation mode (JAM) junctionless (JL) FET. At first, a comparative analysis between the two different graded channel schemes and non-graded channel is performed based on ION, IOFF and ION/IOFF ratio. The scheme that yields the higher ION/IO...
In case of conventional MOSFET structures, Short-Channel Effects (SCEs) are key issues for device performance as dimensions of these devices are reaching nanometer scales following scaling rules. SCEs affect the device characteristics and circuit performance designed with the nanoscale MOSFETs. MOSFETs with Fin-type channel (FinFET) are promising s...
In this paper, analytical modeling of a Dielectric Modulated Double Gate Field Effect Transistor (DM-DGFET) for biosensing application is presented with extensive data analysis. Firstly, the size of the nanogaps and arrangements of biomolecules in those gaps are optimized with respect to the sensitivity of the above sensor. The optimized DM-DGFET i...
The harmonic distortions (HDs) of a rectangular gate-all-around (GAA) junctionless (JL) field-effect transistor (FET) are analyzed using three-dimensional (3D) analytical modeling. The potential function [\(\psi (x,y,z)\)] of the device is derived based on the semianalytical dimension-based weighted-sum approximation approach. This method eliminate...
This letter reports, a room-temperature gas sensor based on the nanohybrid structure of ZnO nanorods (NRs) and reduced graphene oxide (rGO) with better sensitivity. In this nanohybrid structure, ZnO NRs were grown-up by the chemical bath deposition technique (CBD) followed by the electrochemical exfoliation of rGO layer. The collaborative hybridiza...
In this paper, we report a clean and green synthetic route of copper nanoparticles from copper salt using extract of basil (Ocimum tenuiflorum) flowers along with the study of their ability for selective amino acid detection. Using ultraviolet visible spectroscopy, the formation of biogenic copper nanoparticles in the medium was monitored at period...
This paper presents an analytical modeling of a separated gate underlap graded N-channel FET to assess the short-channel effects. A 2D modeling scheme is employed to derive its surface potential, threshold voltage, subthreshold current and DIBL. The proposed structure includes four regions, and the potential function for each region is developed fr...
This paper presents analytical modeling of linearity and intermodulation distortion of a rectangular GAA JL FET using 3D surface potential and drain current. The surface potential () of the GAA JL FET is derived based on the dψ(x,y,z)imension based approximation approach (i.e., weighted sum of ψ(x,y) and ψ(x,z)). The proposed method provides an alt...
A split gated silicon nanotube field-effect transistor (FET) biosensor has been proposed for the label free detection of the biomolecules for the first time in literature. The sensitivity of the sensing device has been analysed considering the on current (I ON) and the threshold voltage (V th) variation. Sub-threshold regime has been considered her...
In this paper, we focus on the improvement of comprehensive device performance of Silicon Nanotube Tunnel Field Effect Transistor (NT_TFET) for ultra low power applications. In the design we have implanted 2nm Halo region at the source side of Si NT_TFET for improving the subthreshold swing and short channel effects (SCEs). To prove the concept, th...
In this work we have studied the impact of variation of k dielectric constant on Silicon Nano Tube FET for low power and high speed applications. The Silicon Nano tubular structure offers better immunity towards short channel effects (SCE's) because of the better control of channel region due to the double gate all around. By cause of gate engineer...
This article presents a systematic study on the analog and radio-frequency (RF) performance of type-II staggered heterostructure p-channel tunnel field-effect transistors (pTFETs) with Ge (Germanium) channel and different compound semiconductor source. In order to study the figure-of-merits (FOMs) of analog and RF performances, various Ge-channel p...
In this paper we studied the impact of variation of dielectric constant and alternation of gate work function on silicon nanotube FET for low power and high speed switching applications. The silicon nano tubular structure offers better immunity towards short channel effects. Due to the gate engineered structure high K value structures possess high...
In this work, a highly sensitive room-temperature hydrogen gas-sensor based on reduced graphene oxide (rGO) and zinc oxide nanoparticles (ZnO NPs) nanohybrid structure is reported. ZnO NPs were grown by chemical deposition method while the rGO layer was produced by the electrochemical exfoliation using tetramethyle ammonium hydroxide (TMAH) as orga...
The graded n-channel underlap fin-shaped field-effect transistor (FinFET) provides ample scope for future investigation. This device and the effects of the underlap, gate length, and doping concentration of the short channel are analyzed herein using two-dimensional (2-D) modeling. The proposed structure includes four regions, in each of which a po...
A new tubular FET device named Silicon Nano Tube Tunnel Field Effect Transistor (Si-NTTFET), has been proposed which is emerged out of structural engineering and the gate dielectric engineering. The proposed structure offers better immunity towards short channel effects (SCE’s) because of the combined effect of minimal doping at the drain side and...
Recent days, for low power applications, germanium (Ge) is considered to be a good alternative of Silicon (Si) as channel material for TFETs to boost the on current. This study reports on the reliability of Ge-pTFET in presence of temperature variability. The reliability is studied through comparative analysis of Analog and Small-signal parameters....
Here we present a simple, clean and eco-friendly synthesis procedure of copper nanoparticles from copper sulphate solution using flower extract of Eichhornia crassipes along with its hydrogen peroxide detectability study. Production of copper nanoparticles was initially verified by scanning the reacting solution under ultraviolet visible (UV–Vis) s...
The paper presents an ab initio study of the 2-D insulators and their effect on the performance of a magnetic tunnel junction memory (MTJ) device. MTJ devices has been considered as an alternate to the charge based data storage cells due to its spin-polarised operation and high scaling probability. The use of 2-D insulators like X-(OH)2 (X: Ca and...
Double‐gate MOSFET with graded channel doping is studied in this work, where the source and drain ends of the channel are doped with different concentrations to yield two different versions of the above device namely high‐low (HL) and low‐high (LH). The digital and analogue performances of these devices are investigated, respectively, by implementi...
In this paper, we have presented an analysis on the performance of a strained silicon channel in Silicon Nanotube FET device. Silicon Nanotube FET devices have tube-shaped channel region and because of this conduction in the channel can be controlled in two ways from outside the tube and from inside (from hollow side) the tube which results in a be...
An effective way to get multiple threshold voltage modulation schemes in Silicon nano tube FET combining unbalanced halo doping is proposed and verified by 3D TCAD Simulator. The typical choice to accomplish multiple threshold voltages is by choosing the appropriate gate work-function for each device. But this results in higher process complexity....
This paper presents a facile method of producing graphene nanosheets by organic liquid assisted electrochemical exfoliation using tetramethyleammonium hydroxide (TMAH) as organic electrolyte. The process involves the low cost copper as ground electrode and carbon block as anode or cathode. Application of organic electrolyte eliminates the presence...
In this paper, analytical modeling of a charge plasma-based nanogap embedded surrounding gate MOSFET biosensor for label-free biosensing has been presented and verified with extensive simulated device data. Along the channel, considering parabolic potential profile, surface potential,threshold voltage,and drain currents have been modeled. Sensitivi...
This paper reviews the rapid advancements being made in the development of high electron mobility transistors
(HEMTs) on InP substrates for future sub-millimetre wave (30–300 GHz) and terahertz (300 GHz to 3.5 THz)
frequency applications. The InP HEMTs exhibits outstanding 2-DEG properties in InAlAs/InGaAs heterostructure.
This paper highlights the...
The non-planar 3D structure of multi-gate FinFETs makes them able to be scaled down to 20 nm and beyond and also have greater performance. But any variation of the fin cross-sectional shape has an impact on the device performance. In this paper, the impact of various fin cross-sectional shape on junctionless accumulation mode bulk FinFETs with thin...
A low-power microelectromechanical system-based metal-oxide gas sensor along with integrated signal conditioning unit is presented in this study to detect and quantify the variation of H2 gas concentrations. The interface circuit controls the sensor operating temperature, measures the H2 gas concentration, contributes a user-friendly interface and...
The detailed numerical analysis is performed to study and evaluate the impact of Indium (In) concentrations of the Indium gallium arsenide (InGaAs) channel on different device performances of InGaAs/In phosphide double gate metal-oxide-semiconductor field-effect transistor using TCAD software. The RF/analogue figures of merits under investigation a...
The behaviour of the adiabatic logic in the near threshold regime has been analysed in depth in this study. Near threshold adiabatic logic (NTAL) style can perform efficiently using a single sinusoidal power supply which reduces the clock tree management and enhances the energy saving capability. Power dissipation, voltage swing, effect of load, te...
Due to the scaling problem of conventional non-volatile memory devices such as floating gate and SONOS Flash memories, innovative and improved works are being carried out with an intention to develop a universal memory leading to integrate the speed of SRAM, density of DRAM and non-volatility of Flash memories in a single memory device which can ca...
In this paper, we explore the possibility of mapping devices designed in TCAD environment to its
modeled version developed in cadence virtuoso environment using a look-up table (LUT) approach. Circuit simulation of newly designed devices in TCAD environment is a very slow and tedious process involving complex scripting. Hence, the LUT based modelin...
This work presents the effect of p-type GaN gate doping concentration on the DC performances of 60nm gate length of AlGaN/GaN Normally-off HFET using 2D Atlas TCAD simulation. An extensive simulation is carried out for the proposed device to explore the parameters such as drain current, transconductance, energy band diagram and surface potential wi...
In this paper we study the analog performance and also extract the RF parameters of Graded channel Gate stack (GCGS) DG MOSFET structure for different high K materials. A relative assessment was also carried out by using 2D Sentrausu TCAD simulator for different high-K oxide layers. This novel device can be one of the promising alternatives to the...
In this paper the effects of channel engineering on
device performance in Symmetric Underlap Gatestack DoubleGate
NMOSFET has been thoroughly analyzed. A device with
undoped channel has been compared with two devices having
doping in source and drain side respectively. It has been observed
that the graded channel with heavily doped source side offe...
Nanocrystalline n-ZnO was prepared by the simple low cost sol-gel method and was deposited on crystalline Si substrate. Sensors with Al/n-ZnO/p-Si/Al, Ni/n-ZnO/p-Si/Al, Au/n-ZnO/p-Si/Al and Pd/n-ZnO/p-Si/Al device structures were exposed to different hydrogen concentrations (0.01, 0.05, 0.1, 0.5 and 1.0 %) at the optimum biasing voltage and tempera...
The hydrogen sensing by palladium-graphene junction was dependent on the atmospheric pressure chemical vapour deposition growth temperature of the graphene films. The growth temperature window adopted in this study was 900–1000 °C, and the hydrogen sensor performance of the palladium–graphene junction (0.5–2.0% H2 in air) was studied in the tempera...
Recently, behavior of adiabatic logic circuits has been analyzed in literature due to the high demand of low power portable application. In this paper, an energy efficient subthreshold adiabatic logic has been presented and analyzed in depth. Proposed logic structures are efficacious compared to the conventional logic circuits due to very low leaka...
This work reported the analog and radio frequency performance for the Graded channel Gate stack double gate MOSFET structure for change in different high K oxide materials in the gate stack region. A wide comparison is established by considering the 2D TCAD simulator for change in doping concentration along the channel. This novel structure consist...
The paper presents a drain current model for double gate metal oxide semiconductor field effect transistors (DG MOSFETs) based on a new velocity saturation model that accounts for short-channel velocity saturation effect independently in the front and the back gate controlled channels under asymmetric front and back gate bias and oxide thickness. T...
Tunnel field-effect transistor (TFET) is considered to have superior device performance compared with DG-metal–oxide–semiconductor FET in terms of reduced off-state current and lower subthreshold swing. However, performance of a device solely depends on the accuracy in the fabrication process. This work presents a systematic methodology in small-si...
In this paper, a novel programmable low power ADCcircuit design is proposed using independently driven underlap double gate MOSFET (IDUDGMOSFET) to operate in radio frequency (RF) domain and its performance is studied. The primary motivation of the design is to eliminate the need of resistor ladder for reference voltage selection and to minimize th...
This paper shows a comparative study of 14 nm Underlap Double Gate (U-DG) NMOSFET with gate stack (GS) with varying underlap length. In highly scaled devices underlap is used to minimize Short Channel Effects (SCEs) as a cost of reduced on current. Hence underlap length has been optimized with the help of on current to off current ratio (I ON/I OFF...
Biological synthesis of metal nanoparticles has been proved as a simple, biocompatible, low cost and green alternative to standard chemical and physical procedures. In this study, we present an unexplored single-step and green process for preparing copper nanoparticles from copper sulphate solution featuring leaf extract of Impatiens balsamina alon...
The papers in this special section focus on nanotechnology which includes nanoelectronics, optoelectronics, and nanomaterials. Since the Nanotechnology is now widely deployed in sensors, optoelectronic, biology, medicine, and material science, we are trying to enhance the research at the nanoscale, to share knowledge, expertise, techniques, and too...
This paper presents the effects of gate dielectrics and channel doping concentration of a symmetric double gate heterostructure MOSFET with heavily doped source/drain region. A detailed investigation of the impact of gate dielectric material on different Analog and RF performance of an InGaAs/InP heterostructure DG MOSFET is carried out. The effect...
The paper presents a comparative study between symmetric and asymmetric straggle architecture, where asymmetric nature is observed by considering straggle in source and drain side alternatively by using the data obtained from 2D numerical simulator Sentaurus TCAD. The analog parameters such as the transconductance (gm), the gain per unit current (g...
In the proposed work subthreshold analog performance of an amplifier, designed using Fully Depleted Silicon On Insulator (FDSOI) MOSFETs is done. Effect of back oxide (BOX) voltage variation on analog performance of subthreshold amplifier is observed. Gain, Bandwidth, linearity of an optimized amplifier against different design parameter is present...
In this work, we investigate the contact and channel material dependency of the transport properties of Siticene and Armchair CNT based heterostructure devices. The Density of States (DOS) of the heterojunction materials and transport properties like Device Density of States, transmission eigenstate, transmission pathway, transmission spectrum and...
In this paper charge plasma based dielectric modulated four gated MOSFET (CP-GUDM-MOSFET) has been proposed for the efficacy of label free electrical detection of the biomolecules. To achieve low thermal budgeting, charge-plasma concept is employed using appropriate metal work function electrodes. Extensive simulations have been done using the Sent...
Atmospheric pressure chemical vapour deposition was employed to deposit graphene thin films on thermally oxidized p-silicon substrates. Raman spectroscopy and energy dispersive spectroscopy revealed the multilayer nature and the composition of the grown graphene films respectively. The defective nature and the defect density of the graphene films w...
In this paper, the use of high-k spacers in a source underlapped nMOSFET is explored. The effects have been reported by varying the dielectric constant of the spacer from 3.9 to 22.5 and the study includes a comparison of analog parameters such as transconductance, transconductance generation factor, intrinsic gain, and RF parameters such as parasi...
In this study, the analogue performance of radio-frequency (RF) range amplifiers and ring oscillators designed using fully depleted silicon on insulator (FDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is studied for different back oxide (BOX) thickness. The analysis exemplifies the need for BOX thickness variation analysis for...
In this work a 6 Transistor SRAM circuit is designed and simulated with FDSOI device whose Channel length (LCH) and Buried Oxide (BOX) thickness (Tbox) is varied to observe the effects on the circuit performance in terms of stability, power consumption and delay. The LCH and Tbox are considered separately, the simulation is performed on same circui...
In this proposed work, an extensive study on the linearity performance of underlap AlInN/GaN double gate metal oxide semiconductor high electron mobility transistors (MOS-HEMT) has been analyzed using 2D Sentaurus TCAD simulation. Specifically a brief comparison is made on the linearity and intermodulation distortion characteristics of the proposed...
The theory of rate of loss of energy of non-equilibrium electrons due to inelastic interaction with the intravalley acoustic phonons in a nano-dimensional semiconductor wire has been developed under the condition of low lattice temperature, when the approximations of the well known traditional theory are not valid. Numerical results are obtained fo...
This paper illustrate the effect of gate material engineering on the performance of enhancement mode n⁺⁺GaN/InAlN/AlN/GaN high electron mobility transistors (HEMTs). A comparative analysis of key device parameters is discussed for the Triple Material Gate (TMG), Dual Material Gate (DMG) and the Single Material Gate (SMG) structure HEMTs by consider...
Here, we present a report on novel green synthesis of metallic copper nanoparticles from copper sulphate solution by using leaf extract of Heliconia psittacorum. The stability and gradual formation of copper nanoparticles during interaction with the extract were investigated using ultraviolet visible (UV-Vis) spectroscopy . Pattern of X-ray diffrac...
This study investigates the performance of the junctionless accumulation-mode (JAM) bulk FinFETs. Different electrical parameters are simulated and analysed for the device with different gate spacer's lengths and materials. Spacers having dielectric constants between 1 and 22 are used to compare the device performance, whereas different spacer leng...
This paper reports a systematic methodology to enhance the performance of germanium p-type tunnel FETs (Ge-pTFETs) using a p
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pocket implant at the source end of the channel and an underlap region at the drain end. The numerical device simulation r...
This paper shows the systematic study of underlap double gate (U-DG) NMOSFETs with Gate Stack (GS) under the influence of dual-k spacers at the different underlap regions. In highly scaled devices, underlap is used at the Source and Drain side so as to reduce the short channel effects (SCE's) but at the cost of low on current (ION) and increased ch...
This book teaches basic and advanced concepts, new methodologies and recent developments in VLSI technology with a focus on low power design. It provides insight on how to use Tanner Spice, Cadence tools, Xilinx tools, VHDL programming and Synopsis to design simple and complex circuits using latest state-of-the art technologies. Emphasis is placed...
Germanium (Ge) tunnel field effect transistor (TFET) is considered to be an excellent solution to resolve the low on-currents issue of Silicon-based TFETs. Whereas, process variability in any low technology node devices (sub-100 nm) is a crucial subject of matter which affects the device reliability and dependability in advanced SoC applications. I...