Carlos Marquez

University of Granada | UGR · Department of Electronics and Computer Technology

Through 3D-TCAD simulations this work aims to demonstrate the benefits of Reconfigurable FETs based on dual doping with respect to the Schottky junctions counterparts using the 28 nm FDSOI platform. These devices feature both N and P dopant species at source and drain to allow for electron and hole symmetrical currents instead of using mid-gap meta...

In this work, we employ the results of atomistic DFT calculation to extract useful parameters for the simulation of few-layers MoS2 structures with traditional TCAD tools. In particular, we focus on the charge distribution, which allows us to obtain a layered model for the dielectric constant, and on the effective densities of states in the conduct...

We employ atomistic calculations to study charge distribution in few-layer MoS2 structures with an applied perpendicular electric field. The results suggest a simple continuum model consisting of alternating regions which represent the semiconductor layers and the Van der Waals gaps between them. Such model is a first step towards an accurate simul...

In this work, the electrical performance of a novel reprogrammable FDSOI device with dual-doping at source/drain and only two top gates is investigated through advanced 3D TCAD simulations. The static and dynamic operations are evaluated and compared with those of traditional Schottky barrier RFETs and standard 28 nm FDSOI MOS transistors under rea...

We investigate the influence of a visible laser treatment on the electrical performance of CVD-grown graphene-based liquid gate sensors. This method allows us to treat locally the graphene sheet, improving the performance of the structure for biochemical sensing applications. It was found critical to control the atmosphere in which the laser treatm...

In this work, the electrical performance and reliability of as-synthesized CVD-grown MoS2 transistors directly grown on SiO2/Si substrate without any transfer process have been evaluated. Transfer and output characteristics, current hysteresis, capacitancevoltage and low-frequency noise signatures have been characterized revealing the huge influenc...

Two-dimensional materials, including molybdenum disulfide (MoS2), present promising sensing and detecting capabilities thanks to their extreme sensitivity to changes in the environment. Their reduced thickness also facilitates the electrostatic control of the channel and opens the door to flexible electronic applications. However, these materials s...

Graphene and two-dimensional (2D) materials have experienced an outstanding development in the last few years. The confinement of the carriers and the improved electrostatic control in the thin channels of fabricated devices have demonstrated surprising results in terms of electrical, photonic, and mechanical properties. However, these properties a...

Schottky junction reconfigurable FETs suffer from limited output currents to drive the following stages, jeopardizing their viability for high-end applications. This drawback becomes dramatic at low voltages. In this work, an analogous novel low-bias reprogrammable device is presented. It features a dual PN doping at source and drain which improves...

This chapter presents a protocol to carry out the systematic characterization of random telegraph noise in MOSFETs assisted by low-frequency noise measurements. The usefulness of this method is demonstrated through its application for monitoring the distribution of traps over state-of-the-art transistors and the influence of static low magnetic fie...

As the scaling of electronic devices approaches to the end of the roadmap quantum phenomena play an important role not only in the electrostatics but also in the electron transport. This work presents the capabilities of a novel implementation of Multi-Subband Ensemble Monte Carlo simulators (MS-EMC) including transport quantum phenomena. In partic...

Dynamic random access memory (DRAM) cells are commonly used in electronic devices and are formed from a single transistor and capacitor. Alternative approaches, which are based on the floating body effect, have been proposed that could reduce manufacturing complexity and minimize the cell footprint by removing the external capacitor. Such capacitor...

3-D numerical technology computer-aided design simulations, based on experimental results, are performed to study the origin of the large Z <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -FET dynamic random access memory (DRAM) memory cell-to-cell variability on fully depleted silicon-on-insul...

The experimental time-dependent dielectric breakdown and ON voltage reliability of advanced FD-SOI Z <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -FET memory cells are characterized for the first time. The front-gate stress time is shown to significantly modulate the ON voltage and, hence, t...

This paper addresses the low-frequency noise characterization of Z <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -FET structures. These double-gated p-i-n diode devices have been fabricated at STMicroelectronics in an ultrathin body and box (UTBB) 28-nm FDSOI technology and designed to operat...

Thin-oxide Z ² -FET cells operating as capacitor-less DRAM devices are experimentally demonstrated. Both the retention time and memory window demonstrate the feasibility of implementing this cell in advanced 28 nm node FDSOI technology. Nevertheless a performance drop and higher variability with respect to thicker oxide Z ² -FET cells are observed.

With the upcoming Internet of Things (IoT), low-power devices are becoming mainstream these days. The need for memory elements able to operate at reduced biasing conditions is therefore of utmost importance. In this paper, one of the most promising capacitor-less dynamic RAM cell, the Z <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlin...

Among the different types of bilayer tunneling field-effect transistors exploiting interband tunneling phenomena with tunneling directions aligned with gate-induced electric fields, the utilization of InAs/GaSb channels proves to be an appealing means to enhance ON-current levels. Ultrathin channel thicknesses make quantum confinement be the agent...

2D numerical TCAD simulations are used to infer the behavior of III-V capacitor-less DRAM cells. In particular, indium gallium arsenide on insulator technology (InGaAs-OI) is selected to verify the viability of III-V MSDRAM (Meta-Stable-Dip RAM) cells. The cell performance dependence on several parameters (such as the back-gate voltage, semiconduct...

Random Telegraph Noise has been experimentally characterized in two sets of nMOSFET devices under the influence of perpendicular magnetic fields at room temperature. The experimental measurements were performed following a systematic trapping phenomena characterization protocol. The results reveal that the drain-source current exhibits an unexpecte...

The need of a low-power, fast and low-cost CMOS compatible embedded DRAM cell is rising incessantly with the upcoming Internet of Things (IoT) era [1]. Capacitor-less DRAM cells [2, 3] have emerged as a promising solution since they do not require dedicated fabrication steps to deal with the storage node. Among this breeze of cells, the MSDRAM [4]...

In this letter, a functional Z <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -FET DRAM memory matrix is experimentally demonstrated for the first time. Word-level operation with simultaneous reading and programming accesses is successfully proved. Disturbance is also explored, and the results...

Advanced 28 nm node FDSOI Z2-FETs with thin top-gate insulator are characterized as capacitor-less DRAM cells. Results demonstrate effective Z2-FET memory behavior for narrow devices (below 1 μm). As compared with thicker gate oxide Z2-FETs, thinning the insulator yields lower performance in terms of retention, variability and stability of the logi...

Thin and ultrathin body-contacted Silicon-on-Insulator MOS-transistors have been used for the direct experimental measurement of the stationary body potential and impact ionization current generated at moderate and high electric field regimes. The large influence of the channel length on the evolution of the body potential as well as the severe los...

Random Telegraph Noise, Bias Instability, Impact Ionization, reliability characterization, Silicon-On-Insualtor, reduced Graphene Oxide

This work introduces a new protocol which aims to facilitate massive on-wafer characterization of Random Telegraph Noise (RTN) in MOS transistors. The methodology combines the noise spectral density scanning by gate bias assisted with a modified Weighted Time Lag Plot algorithm to identify unequivocally the single-trap RTN signals in optimum bias c...

This chapter presents a panoramic view of the potential and physical characteristics of graphene oxide (GO) and rGO, from fabrication to physical and electrical properties. The versatility of this material is emphasized by the laser reduction method, which allows the patterning of conductive rGO surrounded by insulating GO. The chemical synthesis o...

The present work is focused on the electrical characterization of laser-assisted reduced graphene oxide by point contact techniques. The aim is twofold: firstly, the careful investigation of in-line two and four point-contact techniques applied to macroscopic samples of reduced graphene oxide. The combination of both methods has shed light on the r...

Random Telegraph Noise (RTN) has been studied in Ultra-Thin Fully-Depleted Silicon-On-Insulator transistors. A modified Time Lag Plot algorithm has been used to identify devices with a single active trap. The physical characteristics of the trap have been extracted based on Shockley-Read-Hall models, revealing the possible trends of capture and emi...

This work faces the study of impact ionization in Silicon-On-Insulator transistors from the direct characterization of the body current and electrostatic potential. Body contacted devices have been fabricated for that purpose, and biased at zero-potential and zero-current conditions. The combination of both types of measurements has allowed the ext...

Impact Ionization (I.I.) is an inherent phenomenon of very scaled MOSFET devices operated at a high lateral electric field regime ( V D =V DD ). From the Silicon-On-Insulator prospective, it leads, not only to possible reliability issues arisen from the hot carrier generation, but also to the accumulation of charge in the body of the transistor [1]...

A2RAM prototype devices have been demonstrated in both SOI and bulk technologies. The fabrication process has successfully achieved the characteristic retrograde doping profile of the channel which allows the coexistence of electrons and holes in the same body while maintaining low-voltage single-gate operation. The different prototypes have been e...

This work develops an analytical model which correlates the changes of the threshold voltages in Pseudo-MOSFET structures with the charge intentionally placed on the surface of the native oxide. The model has been validated through experimental I-V characteristics obtained when the surface is physically altered with an APTES solution. The measureme...

In this work, we introduce the mobility vs. effective electric field representation for bare silicon-on-insulator substrates. The key factors determining the effective field in the silicon film are identified and modeled. This representation sheds light on the origins of the carrier mobility differences observed in passivated and non-passivated waf...

A novel concept of multi-body 1T-DRAM cell fully compatible with both planar Silicon-On- Insulator substrates and 3D architectures is presented. Its scalability is ensured thanks to the dedicated body partitioning for hole storage and electron current sensing, suppressing the super-coupling effect and allowing the coexistence of electron and hole l...

Bias instability is a reliability issue affecting the electrical characteristics of a MOS transistor when the gate is stressed with relatively high voltage. For the first time, we characterize the instability of bare SOI wafers using the pseudo-MOSFET technique. The effect of positive and negative stress pulses on the properties of both hole and el...

Chapter we present an overview of a capacitor-less DRAM cell based on a 3D multibody transistor with high scalability, low-power consumption, long retention time, non-destructive reading, and wide memory window. High performance is demonstrated on a 20 nm channel length device, including ‘1’ to ‘0’ current ratio larger than 103 (with negligible ‘0’...

Bias Instability is a reliability issue affecting the threshold voltage of a MOS transistor when the gate is stressed with relatively high voltage. For the first time, we characterize the instability of bare SOI wafers using a Pseudo-MOSFET configuration. The effect of positive and negative stress pulses on the properties of both hole and electron...

A2RAM memory cells have been fabricated and characterized on SOI and bulk substrates following standard CMOS processes. In contrast with other floating-body memory concepts, the retrograde P-N doping profile in the body of the transistor allows the coexistence of electrons and holes in the same silicon layer while maintaining single-gate operation...