Caio Batista de Melo

Caio Batista de Melo
University of California, Irvine | UCI · Department of Computer Science

Master of Science

About

6
Publications
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Publications

Publications (6)
Fig. 6.1 CPSoC infrastructure: sensors and actuators throughout the...
Fig. 6.3 Feedback loop overview. The bottom part of the figure...
Fig. 6.4 MARS framework overview from [10]. Different layers of the...
Fig. 6.7 Classification of CPU-GPU workloads observed in mobile games...
+1 Fig. 6.8 Control loop implementing a self-aware approach to memory...
Reflecting on Self-Aware Systems-on-Chip
Chapter
Full-text available
  • Jan 2021
In this chapter, we explore adaptive resource management techniques for cyber-physical systems-on-chip that employ principles of computational self-awareness to varying degrees, specifically reflection. By supporting various self-X properties, systems gain the ability to reason about runtime configuration decisions by considering the significance o...
Fig. 1. IPF's proactive approach in time vs. a reactive one.
Fig. 2. IPF's five-layer organization.
Fig. 3. Resource states: resource planning is done in layer 5, resource...
Fig. 5. IPF on a NoC-based many-core platform.
The Self-Aware Information Processing Factory Paradigm for Mixed-Critical Multiprocessing
Article
Full-text available
  • Jul 2020
In order to provide performance increases despite the end of Moore's law and Dennard scaling, architectures aggressively exploit data-and thread-level parallelism using billions of transistors on a single chip, enabled by extreme geometry miniaturization. A resulting challenge is the control, optimization, and reliable operation of such complex mul...
Fig. 3 Feedback loop overview. The bottom part of the figure represents...
Fig. 4 MARS framework overview from [8]. Different layers of the system...
Fig. 5 Single Input Single Output (SISO) feedback loop [11].
Fig. 9 Idealized IPF Platform from [31]. Self-organizing and Self-aware...
Reflecting on Self-aware Systems-on-Chip
Book
Full-text available
  • Mar 2020
In this chapter, we explore adaptive resource management techniques for cyber-physical systems-on-chip that employ principles of computational self-awareness to varying degrees, specifically reflection. By supporting various self-X properties, systems gain the ability to reason about runtime configuration decisions by considering the significance o...
Figure 1: IPF's five-layer hierarchical organization [12].
Figure 3: Overview of the LCT logic (dashed lines correspond to the...
Figure 4: Impact of safety-critical boundaries on the LCTs' behavior
Figure 5: Hierarchical relationship between the Best-Effort Controller...
Figure 8: Comparison of proactive hazard detection and handling vs....
The Information Processing Factory: A Paradigm for Life Cycle Management of Dependable Systems
Conference Paper
Full-text available
  • Oct 2019
The number and complexity of embedded system platforms used in mixed-criticality applications are rapidly growing. They run large and evolving applications on heterogeneous multi-or many-core processing platforms requiring dependable operation and long lifetime. Examples include automated and autonomous driving, smart buildings, industry 4.0, and p...
Figure 2: hMSC of the Boiler system specification.
Figure 3: Each Boiler component's LTS representing the messages exchanged.
Figure 6: An implied scenario from the boiler system.
Figure 9: Example results for the Smith-Waterman algorithm.
+11 Figure 10: Steps of the proposed methodology.
Characterization of Implied Scenarios as Families of Common Behavior
Article
Full-text available
  • Sep 2019
Concurrent systems face a threat to their reliability in emergent behaviors, which are not included in the specification but can happen during runtime. When concurrent systems are modeled in a scenario-based manner, it is possible to detect emergent behaviors as implied scenarios (ISs) which, analogously, are unexpected scenarios that can happen du...
Fig. 1. IPF's five-layer organization.
Fig. 2. Resource states: resource planning is done in layer 5, resource...
The Information Processing Factory: Organization, Terminology, and Definitions
Preprint
Full-text available
  • Jul 2019
The Information Processing Factory (IPF) project has recently introduced the abstraction of complex architectures as self-aware information processing factories. These factories consist of a set of highly configurable resources, e.g., processing elements and interconnects, whose use is monitored, planned, and configured during runtime. Managing a f...

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