Bulusu Anand

Bulusu Anand
Indian Institute of Technology Roorkee | University of Roorkee · Department of Electronics and Communication Engineering

PhD (Microelectronics)

About

105
Publications
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496
Citations

Publications

Publications (105)
Article
In order to keep up with scaling trends, significant efforts are being undertaken in the direction of vertical stacking of integrated circuits. With advancements in packaging technology, chips are being stacked atop each other using through-silicon-vias (TSVs). The fabrication process for TSVs on a silicon substrate for these 3D integrated circuits...
Article
A novel approach to overcome Boltzmann’s tyranny is to exploit the negative capacitance (NC) effect found naturally in many ferroelectric (FE) materials. We apply a set of coupled equations based on electrostatics, Kirchoff’s law, and a well-calibrated Ginzburg-Landau-Khalatnikov technology computer-aided design (TCAD) model to simulate an organic...
Article
The physical mechanism of the negative capacitance (NC) effect in an organic ferroelectric (OFE) remains unknown. Therefore, this paper presents a series circuit of a resistor and an OFE capacitor (R-OFEC) based on experimentally validated Ginzburg-Landau-Khalatnikov (GLK) theory, electrostatics, and Kirchoff’s circuit rule to understand the transi...
Article
Till date, the existing understanding of negative differential resistance (NDR) is obtained from metal-ferro–metal–insulator–semiconductor (MFMIS) FET, and it has been utilized for both MFMIS and metal–ferro–insulator–semiconductor (MFIS) based NCFETs. However, in MFIS architecture, the ferroelectric capacitance ( C FE ) is not a lumped capacitance...
Article
Harnessing the negative capacitance transient (NCT) in ferroelectric (FE) materials is a relatively new concept in nanoelectronics. In this article, a set of coupled equations based on Kirchhoff's law, electrostatics, and an experimentally validated multidomain Landau-Khalatnikov (MD-LK) equation is used to simulate poly(vinylidene fluoride-co-trif...
Article
In this paper, for the first time, we explained a detailed physical insight for Negative Differential Resistance (NDR) to Positive Differential Resistance (PDR) transition in a ferroelectric-based negative capacitance (NC) FET and also its dependence on the device terminal voltages. Using extensive well-calibrated TCAD simulations, we have investig...
Article
Bias Temperature Instability (BTI) has always been a critical reliability issue in a field effect transistor (FET). In a negative capacitance (NC) FET, a study of BTI with considering the traps at different interfaces is needed to investigate the device performance, which is not yet explored. In this work, for the first time, we have addressed the...
Article
A time-domain jitter estimation methodology considering process-voltage-temperature (PVT) variations of the single-ended ring oscillator (SERO) at an early stage of design is presented for near-threshold voltage (NTV) regime where nonlinearities dominates. For the first time, the model accounts for the jitter due to the over/undershoot region which...
Article
In this work, a comprehensive study of random spatial fluctuation of the ferroelectric (FE) phase and dielectric (DE) phase in FeFETs is conducted to understand its impact on device variation. It is found that: i) there exists a certain DE percentage threshold that below which the increase of the DE phase does not significantly impact the device me...
Article
This brief presents a general technique for achieving the highest possible RO oscillation frequency accompanied by lower phase noise in an enhanced circuit design utilizing novel delay cells. The circuit architecture has the delay cells’ inputs separated by an optimized skew offset. Skew-offset optimization is attained by integrating a pre-charge/d...
Conference Paper
In this paper, the observation of transient negative capacitance signature (NCS) in an organic ferroelectric gate stack (OFEGS) at minimum supply voltage (V S ) of ±0.5 V is investigated employing a well-calibrated Ginzburg-Landau-Khalatnikov (GLK) model in the environment of Sentaurus technology computer-aided design (STCAD). We observe an 88.62 t...
Conference Paper
The idea of harnessing the negative capacitance signature (NCS) effect in a ferroelectric (FE) material is a recent entry in the world of nanoelectronics. There is an urgent need to harness this effect at a minimum supply voltage (VA). Therefore, in this paper, we have investigated the transient NCS response in a series resistor (R)-organic FE (OFE...
Article
In this paper, a variation-aware design methodology for high performance MOS-varactor voltage-controlled ring oscillator (MV-VCRO) in near-threshold-voltage (NTV) regime is proposed. The MV-VCRO is suitable because it eliminates series-stack transistors and generates rail-to-rail swing. For the first time, delay-models for conventional, bulk-driven...
Article
This article demonstrates low supply voltage (VDD) and high-frequency polarization switching in an organic ferroelectric capacitor (OFEC). The Landau- Khalatnikov (LK) equation is used to model the organic ferroelectric (OFE) in the Sentaurus technology computer-aided design (TCAD) environment considering multidomain (MD) dynamics and interaction f...
Article
This paper presents a general approach for generating high-frequency multiphase signals (even/odd), low phase noise, low power, and reduced supply sensitivity ring oscillators (ROs). For the same, multi-loop skew based single-ended ring oscillators (MSSROs) are designed and systematic analysis is performed. The topology is based on a unique feedbac...
Article
In this paper, a novel energy efficient 12T memory cell is proposed which is radiation hardened by design (RHD) to tolerate single-event multiple-node upsets (SEMNU) in near threshold voltage regime. The radiation hardness of the proposed memory cell is improved by controlling the cross coupled inverters' PMOS devices through dummy access transisto...
Article
Due to the highly variation-prone nature of the near-threshold voltage (NTV) circuits, it is critical to have design and performance models that consider process, voltage, and temperature (PVT) variations. However, in the NTV regime, the existing timing models are based on arbitrarily chosen ${V}_{\text {DD}}$ -dependent threshold points for effe...
Article
This article presents an energy-efficient triple-node-upset (TNU)-tolerant latch in a subthreshold/near-threshold regime. The proposed latch provides the TNU tolerance using two restorer circuits (RCs) to hold the correct state and a three-input clocked combinational majority circuit (CMC). The RC is based on pull-up and pull-down paths, controlled...
Article
The gate-source overlap length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OV</sub> ) in the line tunneling FET (L-TFET) can be used as a design parameter to improve the analog circuit performance. In this paper, we investigate the drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/Mat...
Article
This paper presents a physics-based semiempirical model of drain saturation voltage ( ${V}_{\text {DS,SAT}}$ ) of a FinFET device suitable for analog circuit design. The previous belief of similarity of the saturation phenomenon in the FinFET and planar MOSFET devices is investigated for the first time and is shown to be inconsistent in the FinFET...
Article
Near-threshold voltage (NTV) digital VLSI circuits, though important, have their sequential elements vulnerable to soft errors. The critical charge for a single event upset for a D-latch depends on its fan-out load, supply voltage, and transistor level parameters. A SPICE simulation-based estimation of the critical charge is highly resource/time in...
Article
Energy efficiency is considered to be the most critical design parameter for IoT and other ultra low power applications. However, energy efficient circuits show a lesser immunity against soft error, because of the smaller device node capacitances in nanoscale technologies and near-threshold voltage operation. Due to these reasons, the tolerance of...
Conference Paper
Through Silicon Vias (TSVs) used in 3D ICs induce stress in the silicon wafer. This stress causes variations in the mobility and threshold voltage depending upon the value of various stress components, which in turn affects the propagation delay of logic gates. In this paper, a complete methodology is developed for modeling the variation of an inve...
Article
Power dissipation is a prime concern in sub-nanometer VLSI regime and, therefore, operation at near/sub-threshold regime has gained importance. However, though energy efficient, a system performance/functionality is at stake, because of the increase in the variability in near/sub-threshold regime. Therefore, resilient circuit approaches are importa...
Article
A novel energy-efficient radiation hardened by design 10T static RAM (SRAM) cell is proposed. The parasitic extracted simulations show that by employing the proposed 10T-SRAM cell, an average improvement of - 29, 5/10%, and 108/129%, in layout area, write/read access time (WAT/RAT), and write/read static noise margin (WSNM/RSNM), respectively, is o...
Article
This paper presents an effective current model (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) for a near-threshold voltage (NTV) inverter and two-input NAND/NOR gates. The proposed model is validated by 2-D technology computer-aided design mixed-mode device simulations and HSPICE simula...
Conference Paper
This paper presents a novel delay model for Inverter followed by Transmission Gate (Inv-Tx) structure. Our model is novel in the sense that it considers the series stack effect along with the internal node voltage and parasitic capacitances while treating the Inv-Tx structure as a single entity. The model is derived for an unexplored scenario when...
Chapter
In sub 10 nm technology node, vertical silicon nanowire (VNW) FET device has become a promising substitute due to its better gate controllability, short channel immunity, high ION/IOFF ratio and CMOS compatibility. This paper presents, a standard cell library using physics based Verilog-A compact model for 10 nm vertical SiNW FET device. A unified...
Article
This paper highlights the output current saturation in a line tunneling-based tunnel FET (LT-TFET). Thereafter, a novel method to extract the onset of saturation voltage (VDSAT) for LT-TFET is proposed for the first time. A soft saturation state is attained when the electron density in the epitaxial layer over the source region saturates with the d...
Article
In this paper, we present an effective switching current model (Ieff) for inverter followed by a transmission gate structure (Inv-Tx) based on its switching trajectory. Unlike an inverter or NAND/NOR gates, where Ieff depends only on nMOSFET (pMOSFET) current for a falling (rising) transition, it is a function of both nMOSFET and pMOSFET currents f...
Article
In this paper, we analyze stability metrics (e.g. read, write noise margins and access time), geometrical variability and layout area optimization of silicon nanowire field effect transistor (SiNW FET) based 6T SRAM with multiwire sizing technique. The SRAM cell analyzed in this paper is based on the TCAD and experimentally verified SiNW FET Verilo...
Article
For sub-20nm FinFET and nanowire CMOS devices, NBTI is an important reliability issue, and requires an accurate model to predict device and circuit performance. In this paper, we report well calibrated predictive and scalable compact Verilog-A based compact model, integrated with NBTI model for nanowire (NW) CMOS circuit simulation and design. The...
Article
Full-text available
This brief investigates for the first time, a method to extract the value of saturation drain voltage for a tunnel FET. The saturation in output characteristics of a TFET is found to take place when the difference in conduction band energy (ΔEC) of channel (ECC) and drain (ECD) is a few KBT. As the drain voltage (VDS) increases, it is found that th...
Article
Full-text available
Device simulations have become an integral part of semiconductor technology to address many issues (short channel effects, narrow width effects, hot-electron effect) as it goes into nano regime, helping us to continue further with the Moore's Law. TCAD provides a simulation environment to design and develop novel devices, thus a leap forward to stu...
Article
Accurate analytical timing models are desirable for CMOS logic gates designed using nanometer technology nodes. However, many of them are available for Inverter only and other logic gates are handled by collapsing them into equivalent Inverter. Developing an accurate analytical timing model for combinational logic gates entails the challenge of inc...
Conference Paper
Static timing analysis (STA), which is a part of design automation requires the generation and storage of delay values for combinational standard cells and the setup and hold time values for sequential cells at numerous corners in the form of a Look Up Table (LUT). This paper proposes a novel approach for LUT generation of sequential standard cells...
Conference Paper
Operating VLSI circuits at near/sub-threshold region is emerging as the most important technique for low power applications. However, due to the increasing variability in sub-threshold regime, system performance and yield is at stake. Therefore, improved circuit techniques are needed with low power overhead which can essentially improve the yield....
Article
Strain engineering and inverse narrow width effect (INWE) are among the main causes of layout-dependent variations in narrow width devices. Transistor sizing and layout without considering these effects at a prelayout stage may result in suboptimal design and design/layout iterations. In this paper, we model the channel stress variations in multifi...
Article
For optimizing FinFET circuit-level parameters (such as number of fins) with performance predictability, it is necessary to understand the nature of voltage transitions at the nodes of a multistage logic circuit. Since the device's extension region parasitics are strong, these transitions need to be studied while considering them. We find using Tec...
Conference Paper
As semiconductor industry advances toward nano-scale technology, it comes across many issues (such as short channel, narrow width, hot-electron effects etc.), which need to be addressed in time to continue advancements with Moore's Law. Technology Computer Aided Design provides a huge scope to build an environment which can be used to design and de...
Article
In this paper, a detailed analysis of the voltage transfer characteristics of vertical nanowire transistor-based CMOS inverter is presented. We show that noise margins are strongly dependent on the source/drain series resistance, and that the extension lengths can be used as tuning parameters to control the noise margin and gains of the inverter.
Article
Full-text available
In this paper, we present a physics based semi-analytical model for channel potential of symmetric double gate tunnel field effect transistor (TFET). The analytical results are compared with TCAD Sentaurus simulated data. We have used a fitting parameter λ, which represents the screening length (or Debye length) of the device, in this work this fit...
Article
Full-text available
In this letter we optimize and investigate for the first time, the effect of Source/Drain (S/D) spacer oxide on the performance of a dual gate ambipolar silicon nanowire field effect transistor (SiNWFET). Using extensive 3-D TCAD simulations we show that the OFF-state leakage can be reduced by more than 2 orders of magnitude owing to the combined u...
Conference Paper
Full-text available
High permittivity materials have considered as a key enabler in nano-scaled underlap devices to achieve better electrostatic control. However, the enhanced fringing capacitance inherently associated with high-k materials poses several design challenges that limits its usage in high-performance (HP) circuits applications. To simultaneously improve t...
Article
A detailed investigation carried out, with the help of extensive simulations using the TCAD device simulator Sentaurus, with the aim of achieving an understanding of the effects of variations in gate and drain potentials on the device characteristics of a silicon double-gate tunnel field effect transistor (Si-DG TFET) is reported in this paper. The...
Article
Increasing the accuracy of circuit delay estimation using Non Linear Delay Model (NLDM) in nanometer range CMOS technologies is highly challenging. To solve this issue, people have started using effective current source model (ECSM) and composite current source model (CCSM), which can both be derived from each other. For a standard cell, ECSM store...
Chapter
A much higher performance can be achieved by the use of a high-K spacer for only the SE region of the Underlap FinFET. We explain this effect using a 3-transistor equivalent circuit in the FinFET device. Our new device design does not increase OFF state current.
Article
Full-text available
In this paper, the impact of nanowire source/drain extension, diameter, and channel length on nanowire (NW) device performance is investigated. We present a novel approach using the extension length as tuning parameter to match the drive current of n- and p-FET in NW CMOS logic applicable down to 10-nm gate length. Our approach overcomes the drive...
Conference Paper
As the semiconductor industry is moving down to deep-sub micron era (below 45nm), Well Proximity Effect (WPE) is causing significant variations in device performance. This may impact the functionality and performance of circuit designs in highly scaled CMOS technologies. In this work, we have studied the impact of WPE on standard cells and propose...
Article
Strain engineering for performance enhancement is an integral part of a state-of-the-art CMOS process flow. However, use of stressors makes the performance of CMOS devices layout dependent. Performance variability arising due to the use of stressor materials is often referred to as Layout Dependent Effect (LDE) variability. The existing delay model...
Article
We investigate the effects of nitrogen passivation on band structure and density of states in zigzag graphene nanoribbon (zzGNR) using first principle quantum mechanical simulations. The results show that nitrogen edge termination of zzGNR produces a bandgap (~0.7eV) around the Fermi level. We analyze the Bloch functions and projected density of st...
Conference Paper
In this paper, a compact analytical model for sub onset current, the current before the onset of Band-to-Band tunneling, is presented for tunnel field-effect transistor. Shockley-Reed-Hall (SRH) generation and recombination is used to explain the sub-onset current at the two reverse biased source/channel and channel/drain junctions. 2-D numerical s...
Article
FinFETs are poised to replace conventional MOSFETs at sub-22-nm technology nodes mainly due to their relatively planar compatible fabrication process. It is well known that FinFET device parasitics are critical for the propagation delay and power dissipation. However, a quantitative understanding of device parasitics for circuit design is yet to be...
Conference Paper
In this work we studied the impact of number of fingers in strain engineered MFGSs on the performance of sequential circuits designed using multi-finger gate structures (MFGSs) and following different layout scenarios. We studied the stress induced in the channel of MFGSs by decoupling different stress sources and dependence of channel stress on th...
Article
In this paper, the analytical models of parasitic resistance and capacitance of vertical nanowire (VNW) FET are presented, considering device structural asymmetry. These models are then used to analyze the effect of channel, source-drain extension lengths, and nanowire diameter on device and VNW CMOS performance for 15 nm node. We find that the asy...
Conference Paper
In this work, the parasitic resistance components of Vertical nanowire FET (VNW) are analytically modeled considering the gate and device asymmetry. Further the models are used to analyze the scaling performance with varying channel length and source-drain extension length. The top and bottom electrode asymmetry leads to asymmetric parasitic resist...
Article
In this work we investigate the impact of process-induced mechanical stress in narrow width devices and its implication on circuit design. We observe that the channel stress and hence drive strength of narrow width devices significantly depend upon the width of a device. We present a model for estimating width dependent channel stress and effective...
Article
In this paper we propose a modified model of logical effort for designing optimized buffers in multi-fingered layout scenario in the presence of process induced mechanical stress. It is observed that mechanical stresses induced by tensile and compressive Etch Stop Liner (t-ESL and c-ESL), embedded SiGe (eSiGe) and Shallow Trench Isolation (STI) are...
Conference Paper
Accurate estimation of delay is a major challenge in current nanometer regime using Non Linear Delay Model (NLDM) due to issues such as parametric variation, nonlinear capacitance value etc. It demands a large number of simulations to be performed for getting the accurate delay values. To partly solve this issue, people have started using Effective...