Bertrand Le Gal

Bertrand Le Gal
Bordeaux INP · IMS laboratory, UMR CNRS 5218

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153
Publications
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Publications

Publications (153)
Chapter
LDPC codes are a family of error-correcting codes that are present in most space communication standards. Thanks to their large processing power and their parallelization capabilities, prevailing multi-core devices facilitate real-time implementations of digital communication systems, which were previously implemented thanks to dedicated hardware c...
Chapter
In wireless communications, frame detection and synchronization are usually performed using a preamble, consuming bandwidth and resources that are not negligible for small packets. Recently, a new kind of preamble-free frame called Quasi Cyclic Small Packet (QCSP) have been proposed. This paper studies the implementation of QCSP transmission, both...
Conference Paper
In wireless communications, frame detection and synchronization are usually performed using a preamble that consumes bandwidth and resources. A new type of frame called Quasi Cyclic Short Packet offers the advantage of avoiding preamble (thus saving resource) while allowing simple detection algorithm. The paper presents a time method to simplify th...
Article
Full-text available
Advances in digital communication advocate for the use of hardware LDPC decoders in applications requiring reliable and fast information transfer. Hand-coded RTL architectures provide the highest performances but slower the path to IP design. By the use of HLS-based methodology, a number of approaches exists to facilitate development and to rapidly...
Article
Polar codes are a new error correction code family that should be benchmarked and evaluated in comparison to LDPC and turbo-codes. Indeed, recent advances in the 5G digital communication standard recommended the use of polar codes in EMBB control channels. However, in many cases, the implementation of efficient FEC hardware decoders is challenging....
Article
Full-text available
Low-Density Parity-Check (LDPC) codes are a well known Error Correction Code family used for instance, in wireless and satellite communication links. Error correction performance of LDPC codes was further enhanced by extending it to higher order Galois fields, giving rise hence to the so-called non-binary LDPC codes (NB-LDPC). Error correction perf...
Article
In the last few years, with the advent of a software-defined radio (SDR), the processor cores were stated to be an efficient solution to execute the physical layer components. Indeed, multi-core architectures provide both high-processing performance and flexibility, such that they are used in current base station systems instead of dedicated FPGA o...
Article
Full-text available
AFF3CT is an open source toolbox dedicated to Forward Error Correction (FEC or channel coding). It supports a broad range of codes: from widespread turbo codes and Low-Density Parity-Check (LDPC) codes to more recent polar codes. The toolbox is written in C++ and can be used either as a simulator to quickly evaluate algorithms characteristics, or a...
Poster
Full-text available
Dans cet article nous présentons un environne-ment de simulation de Monte Carlo pour les systèmes de communications numériques. Nous nous focalisons en particulier sur les fonctions associées au codage de canal. Après avoir présenté les enjeux liés à la simulation , nous identifions trois problèmes inhérents à ce type de simulation. Puis nous prése...
Conference Paper
The ADMM decoding is a novel LP-based algorithm that can improve the decoding performances of the conventional BP decoding algorithms for LDPC codes. However, it was shown that the Euclidean projection (EP) computation involved in the ADMM algorithm limits the throughput performances of the ADMM hardware decoders and drastically increases their sil...
Article
Full-text available
The alternate direction method of multipliers (ADMM) algorithm has recently been proposed for LDPC decoding based on linear programming (LP) techniques. Even though it improves the error rate performance compared with usual message passing (MP) techniques, it shows a higher computation complexity. However, a significant step towards LP LDPC decodin...
Conference Paper
The enforcement of the linear programming (LP) decoding was recently extended to LDPC convolutional codes (LDPC-CC). It was demonstrated that their convolutional structure suites the message-passing based representation of the LP problem, thanks to the application of the alternating directions method of multipliers (ADMM). In this paper, a modified...
Article
This paper presents the first optimized software implementation of a SCAN decoder for Polar codes. Unlike SC and SC-List decoding algorithms, the SCAN decoding algorithm provides soft outputs (useful for, e.g., parallel concatenated decoders Zhang et al. IEEE Trans Commun 64(2):456–466 2016). Despite the strong data dependencies in the SCAN decodin...
Poster
Full-text available
Construction of good Non-Binary Low Density Parity Check codes
Poster
Full-text available
This demonstration intends to present AFF3CT (A Fast Forward 3rror Correction Tool). The main objective of AFF3CT is to provide a portable, open source, fast and flexible software to the channel coding community in such a way that researchers can spend more time on channel coding / algorithmic problems instead of software development issues. It is...
Conference Paper
Linear programming (LP) technique was demon- strated as efficient for binary and non-binary LDPC block decoding. Indeed, it improves the error correction performance of codes and provides the Maximum-likelihood (ML) certificate. In this paper, the LP algorithm is applied for decoding LDPC convolutional codes (LDPC-CC). The proposed algorithm is bui...
Conference Paper
The ADMM based linear programming (LP) tech-nique shows interesting error correction performance when decoding binary LDPC block codes. Nonetheless, it’s applicability to decode LDPC convolutional codes (LDPC-CC) has not been yet investigated. In this paper, a first flooding based formulation of the ADMM-LP for decoding LDPC-CCs is described. In ad...
Conference Paper
A node-wise (NS) schedule has been recently pro- posed for decoding LDPC codes with the linear programming (LP) decoding approach, based on the alternate direction method of multipliers (ADMM). It improves the error correction performances as well as the convergence speed of the ADMM-LP de-coder. However, it suffers from a high computational comple...
Article
The alternate direction method of multipliers is a recent linear programming error correcting approach which improves the decoding performance of LDPC codes compared with the best BP decoding techniques. In this letter, an efficient implementation of the ADMM LP decoding algorithm on a multicore architecture is presented. Its throughput performance...
Conference Paper
Turbo codes are well known error-correcting codes used in many communication standards. However, they suffer from error floors. Recently, a method - denoted as the flip and check algorithm - that lowers the error floor of turbo codes was proposed. This method relies on the identification of the least reliable bits during the turbo decoding process....
Article
Embedded systems are being increasingly network interconnected. They are required to interact with their environment through text-based protocol messages. Parsing such messages is control dominated. The work presented in this article attempts to accelerate message parsers using a codesign-based approach. We propose a generic architecture associated...
Conference Paper
This paper presents a high-throughput implementation of a portable software turbo decoder. The code is optimized for traditional multi-core CPUs (like x86) and it is based on the Enhanced max-log-MAP turbo decoding variant. The code follows the LTE-Advanced specification. The key of the high performance comes from an inter-frame SIMD strategy combi...
Conference Paper
This article addresses the error floor reduction of double-binary turbo codes. The proposed approach is an extension of a low complexity method originally proposed for decoding binary turbo codes. This method's interest is that it does not need to modify the turbo coding scheme as long as an error detection code is serially concatenated with the tu...
Conference Paper
This paper presents a new dynamic and fully generic implementation of a Successive Cancellation (SC) decoder (multi-precision support and intra-/inter-frame strategy support). This fully generic SC decoder is used to perform comparisons of the different configurations in terms of throughput, latency and energy consumption. A special emphasis is giv...
Article
Decoding performance of turbo codes can flatten at moderately high signal-To-noise ratio. This letter proposes a low complexity method for lowering this error floor. This method rests on the observation of the extrinsic information during the iterative decoding process. A set of {q}most unreliable bits are identified based on their associated extri...
Conference Paper
Error Correction Code decoding algorithms for consumer products such as Internet of Things (IoT) devices are usually implemented as dedicated hardware circuits. As processors are becoming increasingly powerful and energy efficient, there is now a strong desire to perform this processing in software to reduce production costs and time to market. The...
Article
The alternate direction method of multipliers (ADMM) approach has been recently considered for LDPC decoding. It has been approved to enhance the error rate performance compared with conventional message passing (MP) techniques in both the waterfall and error floor regions at the cost of a higher computation complexity. In this letter, a formulatio...
Article
Full-text available
Real-time efficient implementations of LDPC decoders have long been considered exclusively reachable using dedicated hardware architectures. Attempts to implement LDPC decoders on CPU and GPU devices have lead to high power consumptions as well as high processing latencies that are incompatible with most embedded and mobile transmission systems. In...
Article
Full-text available
Error Correction Code decoding algorithms for consumer products such as Internet of Things (IoT) devices are usually implemented as dedicated hardware circuits. As processors are becoming increasingly powerful and energy efficient, there is now a strong desire to perform this processing in software to reduce production costs and time to market. The...
Conference Paper
Full-text available
Dans cet article, nous étudions une méthode de correction de l'information extrinsèque permettant d'améliorer les performances de l'algorithme Max-Log-MAP pour le décodage de Turbo Codes. Cette méthode intitulée Self-Corrected Max-Log-MAP se base sur une approche originellement proposée pour le décodage des codes LDPC. Son principe consiste en la r...
Article
Full-text available
Low-Density Parity-Check (LDPC) codes are an efficient way to correct transmission errors in digital communication systems. Although initially targeting strictly to ASICs due to computation complexity, LDPC decoders have been recently ported to multicore and many-core systems. Most works focused on taking advantage of GPU devices. In this paper, we...
Article
Full-text available
This paper presents an optimized software implementation of a Successive Cancellation (SC) decoder for polar codes. Despite the strong data dependencies in SC decoding, a highly parallel software polar decoder is devised for x86 processor target. A high level of performance is achieved by exploiting the parallelism inherent in today's processor arc...
Article
This paper presents the software implementation of a Polar Codes decoder on an embedded processor. An efficient use of computation and memory resource is made in order to devise a fast polar decoder on an embedded ARM processor. Memory footprint reduction and algorithmic simplifications are applied in order to increase the throughput of the decoder...
Article
The trend of communication systems with higher data rates requires complex modulation techniques. To satisfy the stringent linearity requirements of the emitter, linearization techniques have attracted much attention. Many methods are proposed to reduce the effects of nonlinearities. We implemented an analog and digital Cartesian feedback technique...
Article
Full-text available
Low density parity check (LDPC) decoding process is known as compute intensive. This kind of digital communication applications was recently implemented onto graphic processing unit (GPU) devices for LDPC code performance estimation and/or for real-time measurements. Overall previous studies about LDPC decoding on GPU were based on the implementati...
Article
Low density parity-check (LDPC) codes, are widely used for error correction in digital communication systems. Their inclusion in communication standards requires to define decoders able to support efficiently a set of codes with different code length, code rates or code structures. In addition to this high flexibility, these decoders still have to...
Article
Full-text available
Rapid prototyping is an important step in the development and the verification of computationally demanding tasks of digital communication systems, such as Forward Error Correction (FEC) decoding. The goal is to replace time-consuming simulations based on abstract models of the system with real-time experiments under real-world conditions. GPU-like...
Article
Full-text available
This paper presents a novel hardware architecture for the real-time high-throughput implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard. A parallel filtering order of six units is proposed according to the H.264/AVC standard. With a parallel filtering order (fully compliant with H.264/AVC) an...
Article
In this paper, we introduce FoRTReSS (Flow for Reconfigurable archiTectures in Real-time SystemS), a methodology for the generation of partially reconfigurable architectures with real-time constraints, enabling Design Space Exploration (DSE) at the early stages of the development. FoRTReSS can be completely integrated into existing partial reconfig...
Conference Paper
Full-text available
This paper, proposes a new architecture to reduce the silicon area of the Cartesian feedback (CFB) used to linearize a power amplifier in WCDMA communication standard. The first stage of the previous version consists of two CORDIC structures in vector mode for the phase computation following by a subtractor. Here, we propose to merge these two CORD...
Conference Paper
Full-text available
Supporting standard text-based protocols in embedded systems is challenging because of the often limited computational resources that embedded systems provide. To overcome this issue, a promising approach is to build parsers directly in hardware. Unfortunately, developing such parsers is a daunting task for most developers as it is at the cross-roa...
Conference Paper
Full-text available
Intensive research in the networking domain addresses content- and context-aware features for the Future Internet. Thus, being able to manipulate data flows and to adapt those to given constraints with a minimum resource involvement is a hot topic. On top of this topic, video manipulation is the challenge to undertake in order to optimize resource-...
Conference Paper
Full-text available
Application Specific Instruction set Processor (ASIP) is a promising approach to design an LDPC decoder that have to be compliant with multi-standards. Indeed, channel decoding is mainly dominated by dedicated hardware implementations that cannot easily support a large variety of digital communication standards. In this paper, an LDPC decoder archi...
Article
Full-text available
Supporting standard text-based protocols in embedded systems is challenging because of the often limited computational resources that embedded systems provide. To overcome this issue, a promising approach is to build parsers directly in the hardware. Unfortunately, developing such parsers is a daunting task for most developers as it is at the cross...