Bernice Zee

• Advanced Micro Devices

The semiconductor industry is no longer driven purely by performance. Miniaturization, increased functionality, low latency and high bandwidth requirements are becoming more important. Furthermore, as Moore’s law scaling becomes more difficult and costly, innovations in packaging technologies through heterogeneous integration are being adopted rapi...

3D X-ray microscopy (XRM) is an effective highresolution and non-destructive tool for semiconductor package level failure analysis. One limitation with XRM is the ability to achieve high-resolution 3D images over large fields of view (FOVs) within acceptable scan times. As modern semiconductor packages become more complex, there are increasing dema...

Electronic Device Failure Analysis Technology Roadmap examines the trends shaping the future of semiconductor technology as well as the tools and techniques that will be required to detect, analyze, and remediate failures. The information is organized into ten chapters, seven of which assess the capabilities, limitations, and future needs of fault...

Electronic Device Failure Analysis Technology Roadmap examines the trends shaping the future of semiconductor technology as well as the tools and techniques that will be required to detect, analyze, and remediate failures. The information is organized into ten chapters, seven of which assess the capabilities, limitations, and future needs of fault...

Over the past decade, 3D X-ray technique has played a critical role in semiconductor package failure analysis (FA), primarily owing to its non-destructive nature and high resolution capability [1,2]. As novel complex IC packages soar in recent years [3,4], X-ray failure analysis faces increasing challenges in imaging new advanced packages because I...

Lock-in thermography (LIT) has been successfully applied in different excitation and analysis modes including classical LIT, analysis of the time-resolved temperature response (TRTR) upon square wave excitation and TRTR analysis in combination with arbitrary waveform stimulation. The results obtained by both classical square wave- and arbitrary wav...

Industry and market requirements keep imposing demands in terms of tighter transistor packing, die and component real estate management on the package, faster connections and expanding functionality. This has forced the semiconductor industry to look for novel packaging approaches to allow for 3D stacking of transistors (the so called “More than Mo...

Lock-in thermography (LIT) phase data is used to generate phase shift versus applied lock-in frequency plots to estimate defect depth in semiconductor packages. Typically, samples need to be tested for an extended time to ensure data consistency. Furthermore, determining the specific point on the thermal emission site to collect data from can be ch...

Process challenges and other technology challenges have slowed the implementation of 3D technology into high volume manufacturing well behind the original ITRS expectations. Nevertheless, although full implementation suffered delays, 2.5D through the use of interposer and TSV 3D devices are being already produced, especially in memory devices. Thes...

This paper describes the use of Differential Cone-Beam algorithm to improve CT reconstruction resolution for enhanced visualization of semiconductor flip chip package defects. Results demonstrated improvements in CT reconstruction resolution and time.

This paper describes an alternative cross-section sample preparation approach using triple ion beam (TIB) milling to prepare flip chip samples. The 3 cases study results clearly demonstrate the capability and advantages of TIB milling for preparing Lead-free and eutectic C4 solder bumps and back-end-of-line (BEOL) defects as compared to conventiona...

This paper studied the factors causing adhesion failure between lid and adhesive. Adhesive curing mechanism has been experimentally investigated in combination of surface behaviour analysis on lid by using FTIR and XPS. The results showed residue on lid surface caused by low water rinse flow can affect the curing condition.

This paper presents a study done on the orientation of C4 solder bumps with respect to bulk silicon (Si) in transmission electron microscopy (TEM). The research found that when a sample comprising both controlled-collapse-chip-connection (C4) solder and Si was oriented with respect to a known zone axis of Si, the orientation of the C4 solder grains...

An electrochemically integrated multi-electrode array namely the wire beam electrode (WBE) has been applied in novel experiments to study the anodic dissolution behaviour of aluminium (AA1100), which was exposed to corrosive media with and without the presence of corrosion inhibitor potassium dichromate. The objective of this work is to demonstrate...

Thesis (M. Phil.)--Nanyang Technological University, School of Materials Engineering, 2004.