Avirup Dasgupta

Avirup Dasgupta
Indian Institute of Technology Roorkee | University of Roorkee · Department of Electronics and Communication Engineering

PhD

About

70
Publications
30,697
Reads
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640
Citations
Introduction
Avirup Dasgupta is an assistant professor in the department of Electronics and Communication Engineering at the Indian Institute of Technology Roorkee (IIT Roorkee). He is a member of the Compact Model Coalition, the BSIM group and the Berkeley Device Modeling Center. He is also the recipient of the prestigious IEEE EDS Early Career Award (2021). Prof. Dasgupta is involved in the study of semiconductor device physics as well as compact and numerical modeling of semiconductor devices.
Additional affiliations
January 2021 - present
Indian Institute of Technology Roorkee
Position
  • Professor (Assistant)
September 2018 - December 2020
University of California, Berkeley
Position
  • PostDoc Position
Education
July 2014 - June 2018
Indian Institute of Technology Kanpur
Field of study
  • Electrical Engineering
July 2009 - June 2014
Indian Institute of Technology Kanpur
Field of study
  • Electrical Engineering
July 2009 - June 2014
Indian Institute of Technology Kanpur
Field of study
  • Electrical Engineering

Publications

Publications (70)
Article
We propose an updated compact model for mobility in Nanosheet FETs. This is necessary since Nanosheet FETs exhibit significant mobility degradation with thickness and width scaling caused by centroid shift, changing effective mass due to quantum confinement as well as various crystal orientations of the various conduction planes. The model takes al...
Article
We propose a compact model for nanosheet FETs that take the effects of quantum confinement into account. The model captures the nanosheet width and thickness dependence of the electrostatic dimension, density of states, effective mass, subband energies and threshold voltages and includes them in the charge calculation, resulting in accurate termina...
Article
Full-text available
We have already presented a compact model for Field Effect Transistors (FETs) operating in the quasi-ballistic regime [1]. However, this model suffers from two important problems: (a) The profile for charge density along the channel is not correctly accounted for and (b) current is not conserved throughout the channel. In this paper, we propose imp...
Conference Paper
In this paper, an artificial neural network (ANN) trained using a novel transfer learning approach is presented for the variability-aware signal integrity analysis of on-chip multi- walled carbon nanotube (MWCNT) interconnects. In the proposed transfer learning approach, initially a secondary ANN is trained to emulate the signal integrity quantitie...
Conference Paper
This work deals with insights into low-frequency noise in phosphorene FET. In addition to the flicker noise component, which is often reported in the literature, we also look at generation - recombination (G-R) noise. We evaluate the dependence of noise on the number of layers for both armchair (AC) and zigzag (ZZ) orientations. We also extract the...
Article
We present compact models that capture published cryogenic temperature effects on silicon carrier mobility and velocity saturation, as well as fully depleted silicon on insulator (FDSOI) and fin field effect transistor (FinFET) devices characteristics within the industry-standard Berkeley short-channel IGFET model (BSIM) framework for cryogenic IC...
Article
In this article, we analyze how a ferroelectric (FE) acts as a rechargeable energy storage medium which stores, releases, and retrieves energy, and helps the gate achieve a desired charge density with reduced energy (voltage) from the external gate drive. During transistor turn-on, the FE releases energy, while the whole system is absorbing energy,...
Article
Full-text available
We discuss the BSIM-CMG compact model for SPICE simulations of any common multi-gate (CMG) device. This is an industry standard model which has been used extensively for FinFETs IC design and simulation, and has now been extended to accurately model gate-all-around FET (GAAFET). We present the core framework of BSIM-CMG and discuss the latest updat...
Article
Nanosheet gate-all-around transistors are analyzed for RF applications using calibrated TCAD simulations. The effects of stack spacing and number of stacks on device performance are studied and a substack design for improved RF performance is proposed. The novel substack design can improve cut-off frequency (F <sub xmlns:mml="http://www.w3.org/1998...
Article
Full-text available
Gate-All-Around Field Effect Transistors (GAAFETs) for the future technology nodes will have highly confined channel cross-sections. Effects like subband separation and geometry dependent density of states result in kinks, peaks and valleys appearing in terminal characteristics like capacitance and transconductance. This has significant effect on t...
Article
Full-text available
In this paper, we propose a compact model for Negative Capacitance Nanosheet Field Effect Transistor (NC-NSFET) including quasi-ballistic transport for sub-7nm technology node. The model captures the electrical characteristics of NC-NSFET for different ferroelectric thicknesses. Further, it captures the reverse short channel effects of NCFET for di...
Article
In this article, we will analyze and provide new insights into the polarization gradient effect of a ferroelectric using TCAD simulation and demonstrate how to model the polarization gradient effect using the negative capacitance FET (NCFET) compact model based on the BSIM framework. A larger value of g (the coefficient of polarization gradient eff...
Preprint
Full-text available
A comprehensive study of the scaling of negative capacitance FinFET (NC-FinFET) is conducted with TCAD. We show that the NC-FinFET can be scaled to "2.1nm node" and almost "1.5nm node" that comes two nodes after the industry "3nm node," which has 16nm Lg and is the last FinFET node according to the International Roadmap for Devices and Systems (IRD...
Article
The compact model for negative capacitance FDSOI (NC-FDSOI) FET with metal–ferroelectric–insulator–semiconductor (MFIS) gate-stack is presented, for the first time, in this article. The model is developed based on the framework of BSIM-IMG, an industry-standard model (i.e., for zero thickness of a ferroelectric layer, the model mimics the behavior...
Conference Paper
FDSOI devices are prominently used in low power circuits and high frequency domains due to their superior RF and analog performance, thanks to back-bias capability and relatively ease of transistor design over FinFETs and planar bulk transistors. BSIM-IMG is the industry standard compact model for simulating FDSOI devices. In this work, we will dis...
Conference Paper
Lateral nanosheet field-effect-transistor (FET) is now targeting for 3nm CMOS technology node. It is important to see quantization effect at such confined geometry. In this work, we study the geometrical confinement effects in silicon nanosheet. We developed a unified phenomenological model for insulator capacitance (Cins) in rectangular (i.e., Nan...
Article
The spacer design of the negative capacitance FinFET (NC-FinFET) is investigated by using Sentaurus technology computer-aided design (TCAD). The spacer affects not only the gate capacitance but also the drain current due to the additional gate control from the outer fringing field. It is found that in a heavily loaded circuit although the fin corne...
Article
Full-text available
1/f noise is characterized on thick and thin gate oxide based FinFETs for different channel lengths. The devices exhibit gate bias dependency in 1/f noise even in weak-inversion region of operation which cannot be explained by the existing flicker noise model. We attribute this phenomenon to the non-uniform oxide-trap distribution in energy or spac...
Article
Full-text available
Negative capacitance transistors use ferroelectric (FE) material in the gate stack to improve the transistor performance. The extent of improvement depends on the capacitance matching between the FE capacitance (C f e) and the underlying MOS transistor (CMOS). Since both CMOS and C f e have strong non-linearity, it is difficult to achieve a good ma...
Article
A new design to overcome the nonuniformity of capacitance matching along the channel of a negative capacitance field-effect transistor (NCFET) is presented in this paper. By introducing nonuniform oxidation, the thickness of SiO 2 at the edge regions of the channel can be increased while maintaining the thickness of SiO 2 at the center region of th...
Article
We present a charge based compact model for induced gate thermal noise for Fully Depleted Silicon on Insulator (FDSOI) Transistor. The model uses front and back gate charges as well as the respective mobilities for the development of analytical expression. The model is implemented in Verilog-A and validated with experimentally calibrated TCAD simul...
Conference Paper
We explore the impact of channel area scaling in InGaAs gate-all-around transistor for circular (CNW), square (SNW) and triangular (TNW) cross-sections using coupled self-consistent Schrodinger-Poisson solver. We find that, among all three cross-sections, TNW shows the strongest confinement effect for all the considered dimensions. The confinement...
Article
We model the effects of cross section radius scaling on CV and IV characteristics of Gate-All-Around Field Effect Transistors (GAAFETs); capturing the continuous transition from 3D electron system to 1D electron system. We have obtained computationally efficient models for effective mass, bandgap and subband energies as functions of the cross secti...
Conference Paper
In this paper we present a model for the Flicker noise in quasi-ballistic transistors based on our improved core transport model. The model is validated with DC and noise measurements for an InGaAs nanowire FET and a Carbon nano-tube FET. The noise model, along with the core is valid from drift-diffusive to quasi-ballistic regimes of operation.
Article
In this work, we present an analytical charge based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology viz. different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model...
Article
We present a surface potential based compact model for nanowire FETs which considers 1D electrostatics along with the effect of multiple energy subbands. The model is valid for any semiconductor material, cross-section geometry and any channel length with transport regimes varying from drift-diffusive to quasi-ballistic. The model captures the phen...
Conference Paper
Full-text available
Abstract—In this paper, we present a novel physics based model for front and back gate coupling in UTBB (Ultra Thin body with Buried oxide) Fully Depleted Silicon On Insulator (FD-SOI) Transistors, which is then used in deriving the front and back gate surface potentials. To the best of our knowledge this is the first time a physical coupling model...
Conference Paper
In this paper, we report the major conduction mechanisms of the gate leakage current (Ig) in AlGaN/GaN HEMTs and develop an analytical model for it in a surface potential based framework. GaN HEMTs with higher Al mole fraction in the AlGaN barrier layer experiences high electric field across this layer in the strong reverse gate bias region, leadin...
Conference Paper
Full-text available
In this paper we have proposed new physics based analytical models for transport and flnoise model for field effect transistors (FETs) working in the quasi-ballistic regime. The model is capable of accurately predicting the device current and low frequency flicker noise power spectral density for all drain and gate biases and includes short channel...
Conference Paper
Full-text available
A quantum mechanical model of charge centroid is presented for III-V FETs. The model takes into account the finite potential barrier at the semiconductor/insulator interface and also the non-linearity of the potential profile. The model takes two energy subbands into account to calculate the centroid shift and has been validated against TCAD simula...
Conference Paper
Full-text available
In this paper, we present a study of higher back plane doping on analog figure of merit of FD-SOI (fully depleted-silicon on insulator) MOSFETs at higher frequency. Detailed procedure for DC and RF parameter extraction at higher frequency has been discussed. Surface potential based Industry standard BSIM-IMG model for FD-SOI MOSFETs with enhanced g...
Article
In this paper we have proposed a new analytical model for Field Effect Transistors (FETs) working in the quasi-ballistic regime. The model is based on a calculation of the charge density along the channel which is then used to solve the Poisson’s equation to get the variation of the channel potential. This is then used to calculate the ballistic an...
Article
Full-text available
In this work, we report the noise measurements in the RF frequency range for ultra thin body and thin buried oxide fully depleted silicon on insulator (UTBB FD-SOI) transistors.We analyze the impact of back and front gate biases on the various noise parameters; along with discussions on the secondary effects in FD-SOI transistors which contribute t...
Article
We present an analytical surface potential based model for the induced thermal noise at the gate terminal in High Electron Mobility Transistors, due to gate channel coupling. Our model is applicable to any HEMT device. We also present the results of the validation of our model with experimental data from literature.
Article
In this paper, a surface-potential-based compact model is proposed for the capacitance of AlGaN/GaN high electron mobility transistor (HEMT) dual field-plate structure i.e. with gate and source field-plates. Field-plate incorporation in a HEMT gives an improvement in terms of enhanced breakdown voltage, reduced gate leakage etc. but it affects the...
Conference Paper
In this work, we have studied the trapping in GaN power HEMTs and discussed effect of traps on device characteristics. Simulation set-ups for analysis of switching collapse and current collapse observed in pulsed I-V are also presented. We have proposed and implemented a RC network based trap model to capture the effect of trapping in a surface pot...
Conference Paper
Full-text available
In this paper, we aim to present the Advances Spice Model for High Electron Mobility Transistors (ASM-HEMT). The model is currently being considered in the second phase of industry standardization by the Compact Model Coalition (CMC). The presented physical model is surface potential based and is computationally efficient by virtue of being complet...
Conference Paper
Full-text available
Incorporation of Field Plate in High Electron Mobility Transistors (HEMTs) improves the device breakdown voltage but on the other hand, increases the device Capacitance. It has a direct impact on the device switching characteristics and hence the study of the capacitive behavior holds supreme importance for GaN HEMTs power switching application. Al...
Article
Full-text available
In this paper, an analytical surface potential based compact model for thermal noise in High Electron Mobility Transistors (HEMTs) is presented. The model is based on the recently proposed surface potential formulation for charges and current. The model is tunable and applicable to any HEMT device.
Article
In this paper, the gate current in AlGaN/GaN high-electron mobility transistors is modeled analytically in a surface potential-based compact model. Thermionic emission and Poole–Frenkel emission are two dominant mechanisms for the gate current in the forward and reverse-bias regions, respectively. In addition, a trap-assisted tunneling component, w...
Conference Paper
Full-text available
We present a physical compact model for the calculation of the capacitance including a physics based model for the calculation of the charge centroid for III-V FETs. We have used Fermi-Dirac statistics considering two energy subbands obtained from analytical Schrödinger-Poisson solution of charge. The model is validated with data from numerical dev...
Article
Full-text available
In this paper, we present a physics-based compact model for low frequency noise in high electron mobility transistors (HEMTs). The model is derived considering the physical mechanisms of carrier number fluctuation and mobility fluctuation in the channel. The model is tunable and hence applicable to a wide range of HEMT devices of different geometri...

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