Ashish Sachdeva

Chitkara University · Department of Electronics and Communications Engineering

The recent development in the field of sustainable energy solution for ultra‐low power application is attracting the attention of researchers. This paper is themed on the boosting of input harvested voltage from micro thermo‐electric generator to an appropriate output voltage level. This research proposed an optimized DC–DC boost converter design c...

Wearable device applications such as smartwatches, fitness trackers, and health monitors rely on batteries for power and require static random-access memory (SRAM) with low power consumption and high stability to ensure accurate sensor readings during prolonged operation. In this regard, this paper proposes a novel low-power single-ended 10-transis...

Higher charge mobility, gate control, and better electrostatics are the key reasons that make a carbon nanotube field effect transistor (CNTFET) a better candidate as the successor of conventional complementary metal oxide semiconductor transistors. However, the increased charge mobility also enhances the leakage power. This work uses CNTFET for de...

A large number of interconnections required to implement a binary logic-based circuit leads to an increase in power/energy consumption and area overhead. Utilizing multiple-valued logic (MVL), especially ternary logic, can improve power/energy and total area by reducing the number of interconnections. A ternary logic-based circuit is easily impleme...

Carbon nanotube field effect transistor (CNTFET) is swiftly becoming an alternative to conventional CMOS transistors due to superior transport properties, improved current handling characteristics, and better gate control. This work presents a new Carbon nanotube field effect transistor (CNTFET) based low power, stable static random access memory (...

Radiation‐induced soft errors are becoming a key challenge in satellite‐based communication. The worst‐hit component of such devices is static random‐access memory bit‐cells, owing to their high density, large area, and low‐operating voltage. The unsuitability of conventional 6T SRAM for this purpose is ascertained by weak stability constraints, hi...

In the present scenario, the devices supporting neighbor discovery are going through the renovation phase, and crossing the classical barrier such as the trade-off between power dissipation and access time. The presence of opportunistic nodes in place of static nodes has presented multiple challenges for such devices. Therefore, the focus of neighb...

Recent advancements in high-performance processor operation have nurtured the requirement of low power, reliable, and fast static random-access memory (SRAM). Scaling supply voltage is the most preferred technique while minimizing the power dissipation in SRAM cells. However, several challenges follow with this improvement including, increased soft...

Satellite communication plays a vital role in extending 5G cellular networks to hard-to-reach areas, including airplanes, railways, shipments, other transport mechanisms, and especially in rural regions of the country that are traditionally beyond the reach of cellular service providers. The devices, specifically those incorporating static memories...

With the aggressive growth of the internet of things-based applications in the domestic and industrial domain, the embedded static memory is also under renovation stage to eliminate classical barriers such as soft errors, poor stability, and mediocre performance. In this work, a novel twelve transistors (12T) SRAM cell is presented that replaces th...

Advent and rapid development of on-chip computation in applications based on internet of things has opened space for integration of human life processes with technology. Wireless sensor node is a crucial component of this integration and SRAM employed in these nodes is under renovation phase. In this work, a novel single ended, bit-line powered 10T...

The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM d...

In this article, a Schmitt trigger based 12-Transistors(ST12T) static random-access memory (SRAM) bit-cell has been proposed. The Read Power of proposed cell is reduced by 29.17%/ 24.14% /7.66% /5.87% /7.67% /16.62% when compared to 6T/ 7T/ TA8T/ 9T/ PPN10T/ D2p11T SRAM cells. Proposed ST12T cell also shows 1.52× and 1.86× lesser variability in rea...

The on-chip static random access memory (SRAM) has been under revamp due to swift growth in demand of power-efficient internet-of-things based devices. In this context, a low power transmission gate based read decoupled 9-transistor (TRD9T) SRAM bit-cell has been proposed in this work. The proposed cell efficiently minimizes the power dissipation i...

This paper presents a circuit-level technique of designing a low power and half select free 10T Static Random-Access Memory Cell (SRAM). The proposed cell works with single end read operation and differential write operation. The proposed bit-cell is free from half select issue and supports bit interleaving format. The presented 10T cell exhibits 4...

Over the course of history, we humans have gradually build up a grand edifice of knowledge that enable us to predict, to various extent the panorama of many natural, social,& cultural phenomenon. GAs work by evolving a population of individuals over a number of generations. A fitness value is assigned to each individual in the population, where the...

In this paper, stability analysis of conventional 6-T SRAM cell and Schmitt trigger (ST) based 10-T SRAM cell with optimized sizing parameters has been performed and compared. The read stability, write ability, delay and dissipated power have been investigated. By using N-curve methodology a significant improvement of 4.49%, 5.13% and 28.65% in SVN...

This paper analyzes 11-T SRAM cell to resolve the issue of stability over higher frequencies along with reduced power consumption and moderate delay. The dynamic power for the circuit at 1V supply voltage is found to be 1.740 µW, 2.706 µW, 4.564 µW for 500 MHz, 1 GHz and 2GHz frequency respectively. The reduction in dynamic power is calculated to b...

In this paper, a 11-T static random-access memory (SRAM) cell has been examined that shows a fair reduction in read power dissipation while upholding the stability and moderate performance. In the presented work, parametric variability analysis of various design metrices such as signal to noise margin, read current and read power of the Proposed 11...

This paper analyzes 11-T static random-access memory cell (SRAM) cell circuit to resolve the issue of stability over higher frequencies along with reduced power consumption and moderate delay. The dynamic power for the circuit at 1V supply voltage is found to be 1.740 μW, 2.706 μW, 4.564 μW for 500 MHz, 1 GHz and 2GHz frequency respectively. The re...

Floor planning is a prominent area in the (VLSI) circuit design automation, because it affects the performance, size, yield and reliability of the VLSI chips. Shrinking of manufacturing process, the power density of chips has increased under such a large power density the temperature problem will be highlighted. As technology progresses and the num...

Floorplanning is the initial phase of the very large scale integrated-circuit (VLSI) physical design process, the resultant quality of this phase is very important for successive design stages. It helps to determine the size, reliability, performance and area of the chip. The main motive of VLSI floorplanning is to minimize both area and wire lengt...

In this Paper different SRAM (Static Random Access Memories) cells are studied and compared w.r.t. their power dissipations and current leakage. These different studied structures are also compared with a normal 6-T SRAM cell, which is simulated under 180nm technology. As per outlooks some of the studied improved structures have less power consumpt...

Fiber optic communication technology has brought a revolution since 1970s. This technology has rapidly replaced the copper wires, starting from the core backbone networks then gradually to the metro and now finally towards the access networks. WDM networks present concurrency by multiplexing more than one wavelength and transmit them simultaneously...

an Optical WDM Network is composed of wavelength routing nodes interconnected by point-to-point optical fiber links in a haphazard topology. Wavelength-division multiplexing (WDM) is an effective technique to exploit the large bandwidth of optical fibers to meet the rapid growth of bandwidth demand in the Internet. WDM networks therefore have large...

A method to generate disjoint spanning trees and hence to compute source to all terminal(SAT) reliability of acyclic directed networks is proposed in this paper. SAT reliability of a directed network is defined as the probability that there exists a minimal spanning tree from source node to all terminal nodes of the network. The method initiates wi...

Genetic algorithms (GAs) are adaptive methods which may be used to solve search and optimization problems. They are based on the genetic processes of biological organisms. Over many generations, natural populations evolve according to the principles of natural selection and ”survival of the fittest. This new generation contains a higher proportion...

Over the course of history, we humans have gradually build up a grand edifice of knowledge that enable us to predict, to various extent the panorama of many natural, social,& cultural phenomenon. GAs work by evolving a population of individuals over a number of generations. A fitness value is assigned to each individual in the population, where the...