Artur Jutman

• PhD
• Senior Researcher at Tallinn University of Technology

monitoring failures throughout the computing system

Cyber-physical systems, that consist of a cyber part—a computing system—and a physical part—the system in the physical environment—as well as the respective interfaces between those parts, are omnipresent in our daily lives. The application in the physical environment drives the overall requirements that must be respected when designing the computi...

Motivated by the need to tolerate faults, this paper presents a complete fault management solution that includes fault detection and categorization, maintaining a map of faults, and modified scheduling and application algorithms for using healthy resources only. As the system maintains fairly sophisticated models of itself regarding faulty and heal...

The last decade has seen increasingly rapid growth in the prevalence of FPGA devices. Today, FPGAs are extensively used in all commercial sectors, like communications, consumer, military and industry. Test engineers also recognized a great potential of FPGAs for test and measurement (T&M) purposes. The main benefit of FPGA devices is a possibility...

In recent years embedded instrumentation becomes a cutting-edge technology in the field of testing and measurements. In this paper, we propose a classification of different implementations of FPGA-based embedded instruments based on the format they are delivered to an end-user. Up to now, instruments provided as soft core IPs and hard macro blocks...

This paper presents a method for optimization of board-level scan test with the help of reconfigurable scan-chains (RSCs) implemented in a programmable logic of FPGA. Despite that the RSC concept is a well-known solution for scan-based test time reduction, the usage of RSC may lead to un-acceptable hardware overhead. In our work, we are targeting a...

IEEE 1687 (IJTAG) has been developed to enable flexible and automated access to the increasing number of embedded instruments in today's integrated circuits. These instruments enable efficient post-silicon validation, debugging, wafer sort, package test, burn-in, bring-up and manufacturing test of printed circuit board assemblies, power-on self-tes...

This survey introduces into the common practices, current challenges and advanced techniques of high quality system level test and diagnosis. Specialized techniques and industrial standards of testing complex boards are introduced. The reuse for system test of design for test structures and test data developed at chip level is discussed, including...

The paper describes asynchronous fault detection in silicon chips with network of embedded instruments based on IEEE P1687 IJTAG. This technique allows faster fault detection and localization by using asynchronous signal propagation from instruments to instrumentation network controller. The additional hardware is described, scenarios of operation...

The article focuses on the effective scalable IEEE 1687 instrumentation network for fault management. Failure resilience mechanisms guarantee system's graceful degradation in the field under pressure of wear-out. It is based on fault tolerance concepts but goes beyond by localizing and classifying faults into, that is, transient versus permanent an...

With the continuous growth of capacity of non-volatile memories (NVM) in-system programming (ISP) has become the most time-consuming step in post-assembly phase of board manufacturing. This paper presents a method to assess ISP solutions for on-chip and on-board NVMs. The major contribution of the approach is the formal basis for comparison of stat...

In order to cope with the complexity of today’s digital systems in diagnostic modeling, hierarchical multi-level approaches should be used. In this chapter, the possibilities of using Decision Diagrams (DD) for uniform diagnostic modeling of digital systems at different levels of abstraction are discussed. DDs can be used for modeling the functions...

This paper studies a new approach for board-level test based on synthesizable embedded instruments implemented on FPGA. This very recent methodology utilizes programmable logic devices (FPGA) that are usually available on modern PCBs to a large extent. The purpose of an embedded instrument is to carry out a vast portion of test application related...

This paper presents a software/hardware bundle for studying, training and research related to IEEE 1149.1 Boundary Scan (BS) standard. The presented package includes a software environment Trainer 1149 that is capable to graphically visualize BS facilities and perform fine-grain simulation of BS test process. Trainer 1149 provides a cozy graphical...

The main purpose of this paper is to refine the benefits of the FPGA-based synthetic instrumentation concept (see Section 1) proposed by us earlier [1] as well as to provide some new experimental data based on real industrial designs to show the efficiency of our methodology (see Section 2).

As chips are getting increasingly complex, there is no surprise to find more and more built-in DFX. This built-in DFT is obviously beneficial for chip/silicon DFX engineers; however, board/system level DFX engineers often have limited access to the build in DFX features. There is currently an increasing demand from board/system level DFX engineers...

While system level test was a topic of extremely high interest during the last decades, the cost of the test program development was continuously growing. The restricted capabilities of Boundary Scan (BS) with respect of such modern challenges as dynamic (timing-accurate), at-speed and high speed testing as well as in-system diagnosis of functional...

Many contemporary electronic systems are based on System-on-Chips (SoC) such as micro-controllers or signal processors that communicate with many peripheral devices on the system board and beyond. While, SoC test was a topic of extremely high interest during the last decade, the test beyond SoCs didn't get much attention after introduction of Bound...

Fault tolerance and fault management mechanisms are necessary means to reduce the impact of soft errors and wear out in electronic devices. The semiconductor products manufactured with latest and emerging processes are increasingly affected by these effects. The paper describes a new general scalable fault management architecture based on the lates...

The complexity of today's VLSI chip designs makes verification a necessary step before fabrication. As a result, gate- level logic simulation has become an integral component of the VLSI circuit design process which verifies the design and analyzes its behavior. Because of the continuous growth of the size and complexity of circuits, more efficient...

In this paper, we describe a training environment based on multi-functional software system called “Trainer 1149”. It provides simulation and demonstration functionality for learning, research, and development related to IEEE 1149.1 Boundary Scan (BS) standard. The software supports both the analytic and synthetic learning process. Trainer 1149 is...

This paper presents a software/hardware bundle for studying, training and research related to IEEE 1149.1 Boundary Scan (BS) standard. The presented package includes a software environment that is capable to graphically visualize BS facilities and perform fine-grain simulation of BS test process. The system is not restricted to the limited number o...

In order to cope with the complexity of today’s digital systems in diagnostic modeling, hierarchical multi-level approaches should be used. In this chapter, the possibilities of using Decision Diagrams (DD) for uniform diagnostic modeling of digital systems at different levels of abstraction are discussed. DDs can be used for modeling the functions...

This chapter further details the topic of embedded self-test directing the reader towards the aspects of embedded test generation and test sequence optimization. The authors will brief the basics of widely used pseudorandom test generators and consider different techniques targeting the optimization of fault coverage characteristics of generated se...

Many contemporary electronic systems are based on such System-on-Chips (SoC) as microcontrollers or signal processors that communicate with many peripheral devices on the system board and beyond. While, SoC test was a topic of extremely high interest during the last decade, the test beyond SoCs didn't get much attention after introduction of Bounda...

An environment targeted to e-learning of test issues in microelectronics is presented. The environment consists of a set of Java applets, desktop applications and of a web based access to the HW equipment which can be used in the classroom, for learning at home, in laboratory research and training, or for carrying out testing of students during exa...

Logic simulation is a critical component of the design tool flow in modern hardware development efforts. In this paper a new algorithm for parallel logic simulation is proposed based on a new model of Structurally Synthesized Multiple Input BDDs (SSMIBDD). The SSMIBDDs allow further model size reduction and therefore higher speed of logic simulatio...

The paper presents a new structural fault-independent fault collapsing method for test generation based on the topology analysis of the circuit, which has linear complexity. Fault collapsing is carried out by superposition of binary decision diagrams (BDD) for logic gates, which is used for constructing structurally synthesized BDDs (SSBDD). A new...

The paper presents a new structural fault-independent fault collapsing method based on the topology analysis of the circuit, which has linear complexity. The minimal necessary set of faults as the target objective for test generation is found. The main idea is to produce fault collapsing concurrently with the construction of structurally synthesize...

In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine th...

In this paper, a new very fast fault simulation method for extended class of faults is proposed. The method is based on a two-phase procedure. In the first phase, a novel parallel exact critical path fault tracing is used to determine all the "active" nodes with detectable stuck-at faults. In the second phase of the procedure, reasoning is carried...

This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard boundary scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately imple...

Binary decision diagrams (BDD) have become the state-of-the-art data structure in VLSI CAD for representation and manipulation of Boolean Functions. For verification, fault simulation and test generation purposes structurally synthesized BDDs (SSBDD) have proved to be better suited than traditional BDDs which represent only the function but not the...

The IEEE 1149.1 standard test access port and boundary-scan architecture [1] was approved in 1990 in response to the need for coping with shrinking sizes due to advanced packaging and mounting technologies, and also with the increasing complexity of modern microelectronic devices. Boundary-scan test (BST) was quickly adopted by all industry sectors...

In this work, we propose a multifunctional remote e-learning environment for teaching research by learning and investigating the problems of fault diagnosis in electronic systems. It is a collection of software tools which allow to simulate a system under diagnosis, emulate a pool of different methods and algorithms of fault location, analyze the e...

A new method based on the critical path tracing is proposed for fault simulation in combinational parts of digital systems. The novelty of the method lays in the possibility to carry out complex computations on sets of faults in parallel simultaneously for many test patterns. A topological analysis is carried out to generate an efficient optimized...

This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard Boundary Scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately imple...

This paper represents a new iteration, a new look at the problem of microprocessor-based system-level test that takes into account a new reality in semiconductor technologies and electronic manufacturing. We propose a method of testing correct PCB assembly that uses existing debug interface of a microprocessor for test data transfer. Hence, our app...

Variations in crosstalk is an added source of delay and glitch faults in system on chips built with deep sub-micron technology, especially in chips using wide and long buses. Many of these faults, in such sub-micron chips, may only appear when the chip works at normal operating speed. These crosstalk-induced faults are more serious in systems built...

LFSR reseeding techniques are often applied in BIST due to their ability to considerably improve the fault coverage and test application time by embedding specific vectors into the pseudorandom sequence. The efficiency of a typical reseeding scheme to a large extent depends on the seed selection and consequent test sequence optimization algorithms....

Built-In Self-Test (BIST) techniques are often based on pseudo-random pattern generators, which represent simple structures that can generate necessary test stimuli for a device under test (DUT). For some designs, however, additional measures of fault coverage improvement have to be applied. LFSR reseeding is a popular technique due to its ability...

Nowadays, test and measurement tasks at high volume production facilities are fully automated. Normally the responses of analog components to test stimuli have to be first digitized before being automatically processed in order to identify deviations from the reference signal. When dealing with high frequency devices, the analog to digital conversi...

The efficiency of test generation (quality, speed) for digital systems like microprocessors is highly depending on the methods for diagnostic modeling of systems. For systems with high logic complexity higher level methods are unavoidable.A method is discussed for modeling microprocessors with high level Decision Diagrams (DD). DDs can be used for...

In this paper we analyze the feasibility of a novel neural networks (NN) -based embedded self-test framework for analog devices and systems. The solution that we propose avoids signal quantization, directly dealing with original analog signals, which enables high-accuracy fault detection through lossless signal processing. This is only possible whe...

Testing of delay faults in chips built using sub- micron technology and working at very high speed can only be done using an at-speed testing technique. Such a method has been proposed for testing of delay faults in links connecting two switches which operate asynchronously with respect to each other in a NoC. In this paper, we present a detailed a...

This paper describes a unique remote laboratory for studying CMOS physical defects that is meant to be used in advanced courses in the scope of microelectronic design and test. Both the measurement equipment and the remote access mechanism were custom developed in the frame of the European Union project REASON. The core of the equipment is an educa...

In this paper we describe web-based distributed framework for building software systems to facilitate high-quality teaching, learning and research of digital circuits design and test. Internet-based working becomes a necessity and a reality in modern society and the growing number of developed remote laboratories shows the perspectives of expanded...

A lot of learning management systems (LMS) were developed in the last ten years since e-learning opens new possibilities in learning scenarios. They offer the possibility to watch any of the students action on the computer, but possibilities to verify the level of knowledge, a student has reached (accordingly to Bloompsilas taxonomy), are very poor...

This paper describes a new software tool for high quality training/learning in the field of digital microelectronics. Its main purpose is to give insight into reliability and quality assurance technologies based on Linear Feedback Shift Registers (LFSR) and other Pseudo-Random Pattern Generators (PRPG). Various PRPG types are becoming the mainstrea...

Polynomial selection for LFSR-based BIST schemes has been typically left out of the scope of active research in the recent works due to lack of analytical methods that address this issue. Usage of primitive polynomial with a small number of feedbacks is considered a classical rule of thumb that is usually implemented. Although being beneficial for...

A new improved method for calculation of fault coverage with parallel fault backtracing in combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. A topological analysis is carried out to generate an effic...

This paper describes a diagnostic software package called Turbo Tester. It contains a variety of tools related to the area of testing and diagnosis of integrated circuits. The range of tools includes test generators, logic and fault simulators, a test optimizer, a module for hazard analysis, built- in self-test simulators, design verification and d...

Linear feedback shift registers (LFSR) and other pseudo-random pattern generators (PRPG) have become one of the central elements used in testing and self testing of contemporary complex electronic systems like processors, controllers, and high-performance integrated circuits. The current paper describes a training and research tool for learning bas...

An efficient method of parallel fault simulation for combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. Converting gate-level circuits to the macro-level is accompanied with fault collapsing. A parall...

An environment targeted to e-learning is presented for teaching design and test of electronic systems. The environment consists of a set of Java applets, and of web based access to the hardware equipments, which can be used in the classroom, for learning at home, in laboratory research and training, or for carrying out testing of students during ex...

An environment targeted to e-learning is presented for teaching design and test of electronic systems. The environment consists of a set of Java applets, and of web based access to the HW equipments which can be used in the classroom, for learning at home, in laboratory research and training, or for carrying out testing of students during exams. Th...

Crosstalk induced faults, like delay faults and glitch faults, are becoming important to test for high density SoCs operating at high clock speeds. In this paper, the authors propose a methodology for at-speed testing of glitch faults in links connecting two distinct clock domains in a SoC or a NoC system. The basic idea is to try to create conditi...

In this paper the authors present a framework aimed at optimization of important properties of pseudo-random test pattern generators used in embedded testing of modern complex digital devices like systems-on-chip. The method we propose is based on an evolutionary technique often referred as the genetic algorithm. Experimental results show the feasi...

Linear feedback shift registers (LFSR) has become one of the central elements used in testing and self testing of contemporary complex electronic systems like processors, controllers, and high-performance integrated circuits. The current paper describes a training tool for learning basic and advanced issues related to LFSR-based pseudo-random test...

In this paper, a pure functional test generation method for finite state machines (FSM) is proposed. The method is solely based on state transition diagram (STD) description of FSMs. It guarantees full coverage of stuck-at faults in a two-level implementation of the sum-of-product forms of the next state logic and output logic synthesized from the...

Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when the chip works at normal operating speed. In this paper, we propose a methodology for at-speed testing of delay faults in links connecting two distinct clock domains in a So...

This article describes a measurement environment for study of two CMOS defect types: opens and shorts. These defect types are physically implemented in silicon in a big variety of locations inside a set of digital standard cells and small circuits. The integrated circuit (IC) with the collection of defects is mounted onto a plug-and-play measuremen...

At-speed testing of crosstalk induced logic and delay faults in core based SoCs, is becoming very important. Closely packed buses interconnecting cores are generally laid out on many interconnect layers to minimize area and delay. Aggressor-victim model is often used to represent the effect of crosstalk due to influence of one wire on the other. In...

Current paper proposes an efficient alternative for traditional gate- level fault simulation. The authors explain how Structurally Synthesized Binary Decision Diagrams (SSBDD) can be used for representation, simulation and fault modeling of digital circuits. It is shown how the first phase of any fault simulation algorithm: the fault-free simulatio...

We describe a new e-learning environment and a runtime platform for educational tools on digital system testing and design for testability. This environment is being developed in Tallinn University of Technology and consists of several functional layers. The first one is the hardware component used for illustration of various physical phenomena app...

Interconnect testing in a SoC environment is a new area of research. It represents a further development of traditional board-level testing with respect to the new interconnect paradigm, new fault models, and required high level of autonomy. This article analyzes available interconnect self-test solutions and comes up with a new BIST scheme for at-...

This article describes a novel approach to fault diagnosis suitable for at-speed testing of board-level interconnect faults. The approach is based on a new parallel test pattern generator and a specific fault detecting sequence. The test sequence has tree major advantages. At first, it detects both static and dynamic faults upon interconnects. Seco...

This article describes a novel approach to test pattern generation for at-speed interconnect built-in self-test. The novelty consists in both the original test sequence detecting opens, shorts and delays and the original design of the test pattern generator. The main idea is based on using a circular shift register and its proper initialization. Co...

The paper presents a conception of how to improve the skills of the students studying digital design and test related topics. A learning method based on using the so-called "living pictures" is applied. The goal of this method is to put interactive teaching modules on the Internet so that they can be used in asynchronous-mode learning of digital de...

Current paper presents a special case of BDDs called Structurally Synthesized BDDs. Dieren t from BDDs, which are generated by Shannon's expansion, SSBDDs are generated by a superposition procedure. The paper investigates the mathematical properties of such kind of BDDs, in order to separate the properties of the underlying "skeleton" graphs from t...

Our paper describes a successful experi- ence in combining separate educational tools developed at different universities into a single educational workflow aimed at tea- ching selected topics from the area of Self- Test of digital electronics.

In this paper, we present an overview of latest developments taking place at Tallinn Technical University (TTU) in the area of e-learning supported by European project REASON (REsearch And Training Action for System On Chip DesigN) [8].

Binary Decision Diagrams present an efficient way of modeling digital systems for simulation purposes. In order to take into account the need of representing faults directly in BDDs for fault simulation and test generation a special class of BDDs, refered to as structurally synthesized BDDs is used in the paper. It is shown that the efficiency of s...

This work presents a new teaching concept with, subsequently, a method that combines training and research activities in a common environment. It is developed in the frame of a cooperative project supported by the European Union, called "REASON - Research and Training Action for System on Chip Design". For teaching the advanced topic of design of d...

This paper describes tools used in an e-learning environment developed at Tallinn Technical University in the frames of the project REASON. The environment makes use of a diagnostic software package called Turbo Tester and a set of Java applets. It is aimed at teaching basics as well as advanced topics from the area of digital testing and diagnosti...

Logic-level simulation is still one of the most often used operations on digital designs during both design and test stages. This makes it a critical issue affecting the overall cost of a project. In this paper we investigate and show the origins of common advantages of four recently proposed efficient simulation methods of different classes: logic...

A conception of practical works for teaching design and test of digital circuits is presented. The works cover essential topics in testing and diagnostics field. They are meant for improving the skills of students to be educated for hardware and SoC design in test related topics. Six practical works are described. The works are based on two diagnos...

This paper presents an overview of recently proposed fast methods for static compaction of sequential circuit tests divided into independent test sequences. The methods include genetic algorithm based, greedy and deterministic approaches. We explain the algorithms and discuss the underlying complexity issues. The different methods were tested on a...

In this paper we sum up the research that was done during the last decade on the topic of Structurally Synthesized Binary Decision Diagrams (SSBDDs). We describe general properties of SSBDDs, which make this model very efficient for circuit structure dependent methods and algorithms. In addition, we describe a deterministic test generation algorith...

Abstract – In this paper we describe general properties of Structurally Synthesized Binary Decision Diagrams,(SSBDDs) [1], which make SSBDDs very efficient for application in various structure dependent methods and algorithms. In addition, we describe four recently proposed,efficient simulation methods,of different classes: logic simulation, multi-...

The paper presents a new teaching conception for distance-learning based on using of so called "living pictures". The field considered covers computer engineering, switching and automata theories, and more specifically, design and test of digital circuits and systems. A set of tools ("interactive modules") is offered which support different stages...

The paper presents a new method for static compaction of sequential circuit tests that are divided into independent test sequences. We propose an exact method based on the branch-and-bound approach. The search space for the algorithm is efficiently pruned at each step by determining the set of essential vectors, removing faults and sequences implem...

This paper describes a design system for distance-learning based on using of so called "living pictures". While describing the approach, it addresses relevant questions about the design and test of control intensive digital systems. The system is implemented in a form of Java applets and can be freely accessed over Internet. The Java applets has bu...