Anu Gupta

• PhD
• Professor at Birla Institute of Technology and Science, Pilani

Ensuring women’s safety in smart cities is a need of the hour. Even though several legal and technological steps are adopted worldwide, women’s safety continues to be an international concern. Criminal records are maintained by law enforcement agencies and are most often not available to the public in an easily comprehensible form. While some weara...

This study presents a circle Hough transform (CHT) architecture that provides memory reduction between 74 and 93% without and with little degradation in the accuracy, respectively. For an image of P × Q pixels, the standard (direct) CHT requires a two-dimensional (2D) accumulator array of P × Q cells, but the proposed CHT uses a 2D accumulator arra...

This paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transform (CHT) based algorithm to localize irises in the images c...

In scaled technologies with lower supply voltage, conventional Static Random Access Memory (SRAM) cell suffers from unsuccessful read & write operation due to high off state current in sub-threshold region at nanometre technologies. This work proposes new functional low-power designs of SRAM cells with 7, 8, 9 and 12 transistors which operate at on...

This study presents hardware implementation of 5 × 5 median filter that uses a new low-latency median filter (LLMF) core in order to find the median of 25 integer values. The proposed LLMF core architecture computes the median of 25 integers in just three clock cycles. The maximum frequency of operation of the proposed median filter architecture is...

This paper proposes an edge-map generation technique for pupil detection in near infrared (NIR) images and its hardware implementation. The proposed edge-map generation technique is based on generating two different edge-maps of same eye image using Gaussian filtering, image binarization and Sobel edge detection operations and then combining them t...

This paper proposes an accurate iris localization algorithm for the iris images acquired under near infrared (NIR) illuminations and having noise due to eyelids, eyelashes, lighting reflections, non-uniform illumination, eyeglasses and eyebrow hair etc. The two main contributions in the paper are an edge map generation technique for pupil boundary...

This paper proposes an accurate iris localization algorithm for the iris images acquired under near infrared (NIR) illuminations and having noise due to eyelids, eyelashes, lighting reflections, non-uniform illumination, eyeglasses and eyebrow hair etc. The two main contributions in the paper are an edge map generation technique for pupil boundary...

The paper presents a variability-aware modified 9T SRAM cell. In comparison to 6T SRAM cell the proposed cell achieves 1.3× higher read-SNM and 1.77× higher write-SNM with 79.6% SINM (static current noise margin) distribution at the expense of 14.7× lower WTI (write trip current) at 0.4 V power supply voltage, while maintaining similar stability in...

The paper presents a variability-aware modified 9T SRAM cell. In comparison to 6T SRAM cell the proposed cell achieves 1.3× higher read-SNM and 1.77× higher write-SNM with 79.6% SINM (static current noise margin) distribution at the expense of 14.7× lower WTI (write trip current) at 0.4 V power supply voltage, while maintaining similar stability in...

Iris segmentation in the iris recognition systems is a challenging task under noncooperative environments. The iris segmentation is a process of detecting the pupil, iris’s outer boundary, and eyelids in the iris image. In this paper, we propose a pupil localization method for locating the pupils in the non-close-up and frontal-view iris images tha...

This paper proposes a hardware optimized low power three stage compensated operational amplifier with a capability of driving a wide range of capacitive loads ranging from 200pF to 5nF. The amplifier is compensated by implementing Embedded Capacitance Multiplier (CM) Compensation on the outer Miller capacitor of traditional Reverse Nested Miller Co...

Rapid increases in chip complexity, increasingly faster clocks and proliferation of portable devices have combined to make power dissipation an important design parameter. In battery operated digital devices the demand of low power consumption and low energy dissipation in order to maximise battery life are the matter-of-course. Typical energy opti...

In this chapter, the design and comparative analysis is done in between the most well-known column compression multipliers by Wallace and Dadda in sub-threshold regime. In order to reduce the hardware which ultimately reduces area, power and overall power delay product, an energy efficient basic modules of the multipliers like AND gates, half adder...

This paper involves the design and comparative analysis of Han-Carlson and Kogge-Stone adders in sub-threshold regime using three different hybrid logic families. The performance metrics considered for the analysis of the adders are: power, delay and PDP. Simulation studies are carried out for 8, 16, 32 and 64 bit input data width. The proposed cir...

In this paper, the effects of applying the forward body bias technique to an operational amplifier with transistors operating in the subthreshold regime are reported. A previously established operational amplifier is chosen as a reference and is realized in Cadence Virtuoso. The forward body bias technique is then applied to different transistors i...

The paper presents a novel 8T SRAM cell with access pass gates replaced with modified PMOS pass transistor logic. In comparison to 6T SRAM cell, the proposed cell achieves 3.5x higher read SNM and 2.4x higher write SNM with 16.6% improved SINM (static current noise margin) distribution at the expense of 7x lower WTI (write trip current) at 0.4 V po...

This paper proposes a hardware-efficient low-power 2-bit ternary arithmetic logic unit (TALU) design in carbon nano tube field effect transistor technology. The proposed TALU architecture combines adder-subtractor and Ex-OR cell in one cell, thereby reducing the number of transistors by 71% in comparison with other TALU architecture. Further, the p...

Iris localization is an important step for high accuracy iris recognition systems and it becomes difficult for iris images captured in unconstrained environments. The proposed method localizes irises in unconstrained infrared iris images having non-ideal issues such as severe reflections, eyeglasses, low contrast, low illumination and occlusions by...

The computing efficiency of modern column compression multipliers offers a highly efficient solution to the binary multiplication problem and is well suited for VLSI implementations. The various analyses are established more on compressors circuits particularly with Multiplexer (MUX) design. Conventionally, compressors are anatomized into XOR gate...

Carbon Nanotube Field-Effect Transistor (CNTFET) has proved to be a promising alternative to conventional CMOS design owing to the better electrostatic control and high mobility. The paper presents a novel design of 10 Transistor ternary memory cell, with separate read and write lines. Extensive HSPICE simulations have validated the read-write func...

The paper presents the analysis and implementation of ultra low-power, low voltage and low area 4-bit carry look ahead adder circuits. Sub-threshold design technique has been used to reduce the power consumption and area while maintaining low complexity of logic design in the proposed circuit. Simulation results illustrate the superiority of the ci...

In this paper, a new low power, low noise operational amplifier dedicated to implantable biomedical applications is introduced. The amplifier is designed to minimize input referred noise and power consumption. To reduce input thermal noise, we use the EKV Model to set the bias currents of the transistors. To reduce the flicker noise, PMOS input tra...

This paper proposes a new high speed ternary full adder (TFA) cell for carbon nano tube field effect transistor (CNTFET) technology. The proposed design has a symmetric pull-up and pull-down networks along with a resistive voltage divider as its integral part, which is configured using transistors. The design takes inputs through a decoding unit an...

This paper proposes a novel design of 1-bit ternary magnitude comparator (TMC) using carbon nano tube field effect transistors (CNTFETs). The proposed 1-bit TMC is designed for pass transistor logic style in order to achieve low transistor count. Further, proposed design is used in realization of n-bit TMC which utilizes static binary tree configur...

This paper proposes a novel CNTFET-based design of ternary full adder (TFA) cell using dynamic logic style. The proposed TFA is designed based on the conventional CMOS architecture with utilization of inherent binary nature (0, 1) of input carry signal. Since voltage at the output of the dynamic circuit is stored on a parasitic capacitance, a terna...

This letter presents a design of three-valued content-addressable memory (3CAM) cell with low capacitance comparison logic using carbon nanotube field-effect transistors (CNTFETs). By utilising Synopsis HSPICE and latest layout design tools for 32 nm CNTFET, it is shown that the proposed 3CAM cell achieves 65% reduction in search delay and 6% savin...

In circuit design and evaluation, power and delay play a major role in deciding the circuit performance. Power and delay are approximately inversely related to each other and if one parameter is decreased the other gets increased. The proposed method uses power-delay-product (PDP) as performance metric to optimize the delay and power. The mathemati...

This paper proposes a novel design of pass transistor-based ternary full adder (TFA) cell using inherent binary nature (0, 1) of input carry in carbon nanotube field effect transistor (CNTFET) technology. A buffer circuit is added to get high performance without sacrificing the overall energy efficiency of the design. The use of pass transistor log...

This article presents a hardware-efficient design of 2-bit ternary arithmetic logic unit (ALU) using carbon nanotube field-effect transistors (CNTFETs) for nanoelectronics. The proposed structure introduces a ternary adder–subtractor functional module to optimise ALU architecture. The full adder–subtractor (FAS) cell uses nearly 72% less transistor...

This paper proposes a low power design of 4-input ternary XOR function using carbon nano tube field effect transistors (CNTFETs). In CNTFET, the desired threshold voltage can be achieved by setting the diameter of CNTs. Based on this unique property of CNTFET, the proposed XOR gate is designed utilizing multi-diameter CNTs for multi threshold struc...

This paper presents a highly adaptive operational a mplifier with high gain, high bandwidth, high speed and low power consumption. By adopting the recyclin g folded cascode topology along with an adaptive- biasing circuit, this design achieves high performa nce in terms of gain-bandwidth product (GBW) and sl ew rate (SR). This single stage op-amp...

This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed and low power consumption. By adopting the recycling folded cascode topology along with an adaptive-biasing circuit, this design achieves high performance in terms of gainbandwidth product (GBW) and slew rate (SR). This single stage op-amp has bee...

In this paper, we propose a high performance system design methodology taking the best average delay on prime. Our analysis method is based on the commonly used logical effort methodology, extended to the least delay to find the transistors sizing. Simulation results are tabulated using SPECTRE in 0.18 μm CMOS technology as applied to three differe...

Carbon Nanotube Field-Effect Transistor (CNTFET) technology with their excellent current capabilities, ballistic transport operation and superior thermal conductivities has proved to be a very promising and superior alternative to the conventional CMOS technology. A detailed analysis and simulation based assessment of circuit performance of this te...

Carbon Nanotube Field-Effect Transistor (CNTFET) with high mobility due to ballistic transport operation and low OFF current capability has proved to be a promising alternate to the conventional CMOS technology. This paper presents a design, performance assessment and comparative analysis for CNTFET based Dynamic Ternary Content Addressable Memory...

This paper describes a 8-bit 22.5 MS/s Asynchronous Analog to Digital Converter (A-ADC) employing a Successive Approximation Register (SAR) architecture. The proposed system relies on single rail encoded handshaking signals to transfer data between functional blocks and perpetuates its conversion cyclically without an external clock. The components...

This paper presents a well-defined method for the design of a high gain, high CMRR two-stage CMOS operational amplifier using 0.18μm CMOS technology for Bio-medical applications. The Op-amp consists of a cascade of Folded-cascode differential amplifier in first stage followed by a fully differential amplifier with PMOS current source load in second...

A frequency compensation technique for achieving high 3-dB bandwidth in two-stage operational amplifiers is demonstrated in this paper. Due to the phenomenon of pole splitting in Miller's Compensation technique in classical op-amp, the 3-dB bandwidth reduces drastically. The technique demonstrated in this paper is a modification of Miller's Compens...

Carbon Nanotube Field-Effect Transistor (CNTFET) with 1-D band structure providing better electrostatic control and high mobility due to ballistic transport operation has proved to be a promising alternative to the conventional CMOS technology. This paper presents a design, performance evaluation and comparative analysis for CNTFET based Dynamic Du...

The paper presents the implementation of a high speed energy efficient 4-bit binary CLA based incrementer decrementer. The design methodology is extensively based on static CMOS logic and transmission gate logic to achieve higher operating frequencies, smaller delays and optimized area. This circuit is especially suitable for long bit incrementer/d...

Carbon Nanotube Field-Effect Transistor (CNTFET) with 1-D band structure providing high carrier velocity on account of ballistic transport operation and low OFF current capability has proved to be a promising alternative to the conventional CMOS technology. This paper presents novel designs of content addressable memory (CAM) cells using CNTFETs. A...

In the post silicon era as the silicon reaches its fundamental scaling limits graphene nanoribbons is expected to take over and thus continue the Moore's law about the diminishing size of transistors. Graphene nanoribbons facilitates high speed low power switching applications. Low and high field mobilities of the graphene nanoribbons are found to...

Integrated biomedical sensors are used in biomedical devices which monitor vital bio-signals such as ECG, EMG, AAP, etc., whose maximum frequency range up to few MHz. Such integrated systems require analog to digital converters with Megahertz conversion rate. This paper presents a novel architecture of asynchronous pipelined analog to digital conve...

Tradeoff between the power dissipation and speed is one of the major issues in modern VLSI circuit design. Improving the circuit speed methods typically lead to excessive power consumption. In this work, we explore the energy-delay design in CMOS circuits, to find gate sizes which produce the lowest possible energy and delay. Our analysis methods i...

In this paper, an effort has been made to improve the delay of a gate by skewing the gates by choosing proper sizing. The expression for skewed logical effort has been derived for universal logic gates namely NOT, NAND and NOR for minimizing the delay. The validations for minimum delay through simulation was done on a chain of inverters. The improv...

This paper presents a novel architecture of Asynchronous Pipelined Analog to digital converter with emphasis on elimination of external clock for integrated self-triggered sensor based applications. The main innovative feature of the proposed pipelined ADC is that it operates without any external clock signal and performs conversion of the analog i...

This paper presents a fast locking, multiphase-output Delay Locked Loop(DLL). We propose a novel method to reduce locking time using a circuit which determines the input frequency thereby enabling the DLL to start output clock closest to reference clock(ref_clk). The DLL is designed in TSMC 0.18um technology. It has a frequency range from 105 MHz t...

The present day software approaches for fingerprint identification systems, are very slow and computationally complex, and hence the user has to wait for a long time before being granted access. The hardware version of the same system is much faster and reliable. We proceed by exploring a new tool in MATLAB in order to describe this system. Three b...

Redundant binary number appears to be appropriate for high-speed arithmetic operation, but the delay and hardware cost associated with the conversion from redundant binary (RB) to natural binary (NB) number is still a challenging task. In the present investigation a simple approach has been adopted to achieve high speed with lesser hardware and pow...

This paper proposes a design for a low power cascaded three stage Operational Amplifier, with frequency compensation by Nested Miller Compensation which could be made to operate at low voltage supplies. The multipath technique is used to increase the bandwidth by converting the system into a two stage amplifier at high frequencies. The Op-Amp is de...

Most of the time, power supplies fail to provide a constant voltage supply and some external voltage signal may override on the power supply giving unwanted fluctuation at the output node. This paper discusses 3 techniques to improve the Power Supply Rejection Ratio (PSRR) in amplifier circuits. 1) Cascoding technique – Cascoding increases the gain...

This paper presents a novel fixed-point 16-bit word-width 16-point FFT/IFFT processor architecture designed primarily for the signal and image processing application. The 16-point FFT is realised by using Cooley-Tukey decimation in time algorithm. This approach reduces the number of required complex multiplications compared to a normal discrete Fou...

A very simple technique to achieve low settling time is presented. It is based on the combination of class AB differential input stages, local common-mode feedback (LCMFB), and clamping circuit which provides additional current boosting, keeping the gain-bandwidth product (GBW) nearly constant. The slew enhancement is provided by an auxiliary circu...

Working with low frequency Universal Charge Recovery Logic (CRL) based NAND gate given in Ill, the leakage current results in gradual charge up of the output node resulting in an incorrect output. A better implementation of the same circuit which increases the output resistance for the leakage current is used to mitigate this drawback in this paper...

An advanced technology based on semiconductor band gaps for the generation of on-chip stable reference current is presented. The strong on-chip current reference circuit provided by the unique design achieves second-order compensation with no external components and has the potential to generate currents with temperature coefficients less than ten...

This paper describes the design of a high performance, low power fully differential telescopic amplifier. As is well known, high gain differential amplifiers require an additional Common-Mode Feedback (CMFB) circuit owing to their high output impedances. This is because high output impedance makes it difficult to fix their output DC level. The addi...

One of the most carefully engineered components of a digital integrated circuit is the clock distribution network. A clock is unarguably the most important signal and the network used for its distribution contributes to nearly half of the entire power dissipated by the IC. The design of a clock distribution network requires tremendous resources in...

Purpose The objective is to explore various adder architectures using different logic‐design styles and transistor‐sizes for different operand sizes. The scope of this work is the development of tools, which can be used to predict an optimum adder design for a given application based on the speed and energy‐consumption constraints. Design/methodol...

Power dissipation has become a critical design constraint in portable applications like a hand held computer due to limited battery life and reliability of integrated circuits. In this paper, a detailed comparison of five adiabatic logic families is carried out by simulation using SPICE. The simulation results are obtained for full adders, which ar...

This paper proposes an approach for designing a R-2R 10 bit Digital to Analog Converter (DAC) which could be made to operate at low voltage supply by efficiently exploiting the cascaded Operational Amplifier (Op-Amp) architecture. The DAC operates at a 3V power supply with a settling time of 50-100ns , dynamic range of around 50-60 dB for signals u...

This paper describes a new circuit of a temperature-compensated CMOS current reference. The temperature dependency of the output current has been compensated by the addition of two currents which have exactly opposite temperature dependencies. Using a simple circuit, an appreciably low value of temperature drift of the output current has been obtai...

In this paper design and implementation of a two stage fully differential, RC Miller compensated CMOS operational amplifier is presented. High gain enables this circuit to operate efficiently in a closed loop feedback system, whereas high bandwidth makes it suitable for high speed applications. The design is also able to address any fluctuation in...

Verilog-AMS is one of the major hardware description languages that are currently employed while designing or testing the performance of mixed signal systems. Besides providing extended capabilities to model analog and digital behavior, this language supports the merging of existing digital and analog designs without going through the process of re...