Anne-Marie Trullemans-Anckaert

Catholic University of Louvain | UCLouvain · Department of Electrical Engineering

Dynamic current activity extraction plays a very important role in estimating the electromagnetic compatibility of integrated circuits. For that purpose, the Integrated Circuit Electromagnetic Model (ICEM) is being developed by the International Electrotechnical Commission (IEC). This article introduces a mixed-mode simulation methodology, based on...

A new design methodology is presented for predicting the conducted-mode emission generated by an integrated circuit. Using the Integrated Circuit Electromagnetic Model (ICEM) developed by the International Electro-technical Commission (IEC), the influence of the internal power supply distribution is modeled, and the sensitivity to design options or...

Transient supply current extraction plays a very important role in estimating performance level in the IC EMC field. As far as complex circuits such as microcontrollers are concerned, transistor-level (SPICE-based) simulation leads to very long CPU times, mainly because of memory arrays which often represent more than 80 % of the transistors in a m...

Switching activity estimates are fundamental in probabilistic techniques orienting resynthesis for low power. The Polynomial Simulation method allows a good performance /accuracy tradeoff for activity computation under general delay,controlled by a single parameter l.

We present here the Controlling Value Boolean Matching based on fault analysis. The problem is to match a Boolean function with don't cares on library cells under arbitrary input permutations and/or input-output phase assignments. Most of the library cells can be represented by tree structure circuits. The approach presented here is suitable for th...

We present an interactive environment, named AStErIx, to help the development of new logic synthesis algorithms and visualize graphically the synthesis results. This environment is based on public domain tools (Sis and LEDA), with added facilities to improve the programming support (based on the Obelix library), and a graph interface (Idefix) to an...

The technology mapping — final step of the logic synthesis — maps the decomposed Boolean function on physical cells. We address here the decomposition and the matching steps. We present two different ROBDD-based techniques to handle the decomposition problem, and compare them. For handling the matching step, we analyse a heuristics based on symmetr...

A novel approach to the Boolean mapping problem is presented. It relies on a Boolean matching algorithm [TF96], which may take advantage of don't care conditions . For area minimization, the comparison with the structural matching approach - used in SIS [Tou90] - shows that the Boolean mapping achieve better results in similar computing time. Wewil...

A novel approach to the Boolean mapping problem is presented. It relies on a Boolean matching algorithm based on testing techniques. The matching is detected by checking the controllability and observabilityofsignals in the cell structure against the subject functions of the network. The method was implemented inside the SIS [Tou90] synthesis envir...

At the end of the logic synthesis, the technology mapping maps the Boolean function on physical cells. This step is based on a matching check, which complexity depends on the number of library cell inputs, and increases if don't cares are considered. We present a method based on fault analysis techniques, which uses a structural equivalent of the c...

Most of the research in last years has been concentrated on developing low power design, where the BDDs have been used to estimate the power consumption.

We address the problem of power estimation at the register-transfer level (RTL). At this level, the circuit is described in terms of a set of interconnected memory elements and combinational modules of different degrees of complexity. We propose a bottom-up approach to create a simplified high-level model of the block behavior for power estimation,...

Ending the logic synthesis, the technology mapping step maps the Boolean function on physical cells. This itep is based on a matching check, which complexity depends on the number of library cell inputs, and increases if don't cares are considered. The method presented here is based on fault analysis. Using a structural equivalent of the cell, it a...

At the end of logic synthesis, the technology mapping step maps the Boolean function on physical cells. This step is based on a matching check, the complexity of which depends on the number of library cell inputs, and increases if don't cares are considered. The method presented here is based on fault analysis. Using a structural equivalent of the...

A new method was presented for the minimization of incompletely specified functions using MBDs (modified binary decision diagrams: ROBDDs with a don't care terminal). The cost function to be minimized is the MBD size, which is an important factor in the case of FPGA synthesis. The method developed is based on a subgraph matching target to reduce th...

Heuristics leading to improved ordering computation for binary decision diagrams (BDDs) are given. An initial step, based on the topology of the network, generates a hierarchical variable ordering. This initial result is further refined by incremental manipulation governed by the stochastic evolution technique. A new property of BDDs is introduced...

The paper presents algorithms for two-level logic minimization of Boolean functions represented by Modified Binary Decision Diagrams (MBDs). MBDs allow the representation of the don't care set in the same graph. The main goal is to produce prime and irredundant covers for these MBDs. A new kind of mixed two-level representation is adopted, where ea...