Anindya Sundar Dhar

• PhD
• Professor at Indian Institute of Technology Kharagpur

This paper presents an adaptive encoding framework for the reduction of coupling transition activity in on-chip data buses. The technique relies on the observation of data characteristics over fixed window sizes and formation of cluster with bit-lines. The proposed method utilizes redundancy in space and time to prevent loss of information while re...

In this work, we attempt to solve the problem of achieving more consecutive degrees of freedom (DOF) in a coprime array for direction-of-arrival (DOA) estimation. Specifically, we propose a novel coprime array, which we term as optimal coprime array (OCA). OCA has attractive features in terms of achieving a large number of uniform DOF. Also, closed...

This paper proposes a novel coprime array configuration, which achieves more degrees of freedom (DOFs) than the existing coprime arrays for half wavelength array motion in direction-of-arrival estimation. Generally, in a moving coprime array, there exists a large number of redundant lags in its difference coarray, which limits the number of achieva...

In this work, we propose a novel coprime array with compressed inter-element spacing (CACIS) configuration, which achieves the more consecutive and unique degrees of freedom (DOF) over the existing CACIS configuration. We know that CACIS is a popular configuration of the coprime class of arrays for direction-of-arrival estimation, where the inter-e...

Optimized Field Programmable Gate Array (FPGA) implementation of Cellular Automata (CA) for high speed design requires knowledge of the platform specific logic cell architecture. In this paper, we have proposed architectures and design automation of a particular class of CA, essentially a Finite State Machine (FSM), which obey rules governed by pri...

This paper presents the design and analysis of the architecture of a fraction phase based frequency calibration unit where the number of delay cells (that sense the fraction phase) have been reduced to zero. As no pre-calibration of the delay values are required, it becomes immune to process-voltage-temperature variation. Simulation results for fre...

In this work, we propose some novel coprime array configurations for real-valued sources, which will achieve more degrees-of-freedom (DOF) than the other existing coprime arrays when the array is moved only by half wavelength. We know that for real-valued sources, the properties of the difference and sum coarray (DSCA) of the synthetic array (SA) c...

This work proposes a novel $k$ -times extended coprime array for direction-of-arrival (DOA) estimation that achieves more consecutive degrees-of-freedom (DOF) than the existing $k$ -times extended coprime array with the same number of sensors. If $M$ and $N$ are the parameters of the coprime array, it will be proved that the increase in con...

In this work, we propose a novel coprime array configuration that will increase the degrees of freedom (DOF) and reduce the mutual coupling than those of the prototype coprime array (PCA). The novel array will be called as special coprime array (SCA). Here we utilize both the temporal and spatial information to get the sum difference coarray (SDCA)...

Approximate computing technique has been adopted in recent years to develop low power design solutions targeted towards error-tolerant applications. Since the accuracy requirements of an application can vary dynamically at run-time, there is a justified need to design reconfigurable approximate circuits with varying power requirements proportional...

In this letter, a novel nested array is proposed which not only increases the degrees of freedom (DOF) but also reduces the mutual coupling that occurs in the general nested array structure by moving the original array only half wavelength. Here we deal with real-valued sources like AM or BPSK whereby we can explore the property of the sum coarray...

Cellular Automata (CA) is attractive for high-speed VLSI implementation due to modularity, cascadability, and locality of interconnections confined to neighboring logic cells. However, this outcome is not easily transferable to tree-structured CA, since the neighbors having half and double the index value of the current CA cell under question can b...

In this paper, we have addressed a speed-area efficient VLSI implementation of a cellular automaton (CA) based random number generator (RNG) on FPGAs, in which each CA cell was proposed to be a multi-bit word in the original algorithm. This is in contrast to typical CA algorithms comprising one bit per CA cell. The original algorithm is shown favou...

‘Fast Fourier transform’ (FFT), being a prevalent algorithm for the proficient computation of ‘discrete Fourier transform,’ constitutes one of the major sub-modules in numerous real-time signal processing systems. In this article, a new approach of CORDIC-based high-radix FFT architecture has been demonstrated. Having identified the complex rotatio...

In this paper, we have achieved run-time dynamic reconfiguration by employing a category of logic cells equipped to realize programmability in Cellular Automata (CA) architectures on Field Programmable Gate Arrays (FPGAs). This is essential for real time VLSI implementations of random number generators, whose functionality requires reconfiguration...

In recent years, several approximate adders have been proposed which are targeted for energy-efficient system design specific to error-tolerant applications. An approximate least significant bit (LSB) adder (ALA) is one such class of adder which is composed of two adder segments: one accurate most significant adder segment and one LSB adder segment...

Approximate computing has emerged as a promising technique to develop energy efficient design solutions for error-tolerant applications. Many research efforts have been directed towards proposing approximations in power-hungry multiplier circuits. In this brief, we have introduced two variants of a broken array approximate booth multiplier design c...

Canonic signed digit (CSD) recoding finds applications in real time VLSI signal processing. In this paper, we have proposed optimized FPGA implementations of CSD recoding techniques starting from a two’s complement input and a redundant signed digit (SD) input. The architectures exploit the fast, hardwired fabric resources of the FPGA logic element...

Running discrete Fourier transform (running DFT) is being used to overcome the drawbacks of ping pong buffer technique by employing fast Fourier transform (FFT) for real time spectrum analyzer, However, the major drawback of existing MAC or CORDIC (CO-ordinate Rotational DIgital Computer) based computation of running DFT is error accumulation due t...

This paper presents a new static redundancy technique that combines the redundancy at transistor level with redundancy at functional level and offers a very good reliability at minimal increase in the hardware, delay and power overheads. The proposed method does not require any external voter hardware as in triple modular redundancy (TMR) method; i...

Cellular automata (CA) have received significant attention in VLSI design for the inherent architectural advantages of modularity, cascadability, simplicity and localized interconnections. In this paper, we have designed FPGA fabric aware CA circuit topologies with a built-in bidirectional scan chain to facilitate fine-grained fault localization of...

This study presents a very-large-scale integration (VLSI) architecture for the triangular windowed sliding discrete Fourier transform (SDFT) based on COordinate rotation DIgital computer (CORDIC) algorithm. In the literature, the triangular windowed SDFT is obtained by direct cascading of two SDFT modules, whereas the idea of direct cascading leads...

This brief proposes robust adaptive filtering algorithms and their VLSI architectures for sparse system identification under impulsive noise. Several robust algorithms are derived by combining error nonlinear adaptive filtering algorithms with proportionate adaptation. We make a comparative study of the derived algorithms and their VLSI architectur...

In this paper, we propose a new static fault-tolerant technique, viz. modulo-quad-transistor, combining redundancy at circuit level with that at functional level, which offers considerably lower failure rate over all the popular fault-tolerant methods. The new approach of compound redundancy also combines the benefits of the two, reducing the overa...

Since decades, the fractional Fourier transform (FrFT) has attracted researchers from various domains such as signal and image processing applications. These applications have been essentially demanding the requirement of low computational complexity of FrFT. In this paper, FrFT is simplified to reduce the complexity, and further an efficient CORDI...

This paper presents a COordinate Rotation DIgital Computer (CORDIC)-based architecture of the sliding discrete Fourier transform (SDFT) for the real-time spectrum analysis with a refreshing mechanism through which the design can provide reduced and bounded error-accumulation due to the recursive nature of the existing SDFT algorithms. The proposed...

In error-tolerant applications, approximate adders have been exploited extensively to achieve energy efficient system designs. Mean error distance is one of the important error metrics used as a performance measure of approximate adders. In this work, a fast and efficient methodology is proposed to determine the exact mean error distance in approxi...

Hardware implementation of hybrid coder based on fractal and SPIHT image compression technique is presented in this paper. Time complexity of fractal image encoder is improved and the desired image quality at varying bit rates is achieved as a result of this hybridization. LL subband of the wavelet transformed image is used for the fractal encoding...

The ever increasing demand to push the envelope for achieving superlative metrics of VLSI circuit performance along with denser logic packing and miniaturization of device dimensions, has rendered FPGAs to be more vulnerable to reliability hazards. This has led to reducing of the reliability and lifetime of VLSI chips. In this paper, we have propos...

Fault tolerance has become essential for safety-critical applications like avionics, space, defense, automotive, bio-medical etc., where redundancy must be added to increase the systems’ reliability. Incorporation of fault tolerance costs for extra hardware, time and power overhead that limits the use of existing fault tolerant methods in resource...

This paper presents an adaptive encoding framework for the reduction of transition activity in high-capacitance off-chip data buses, since power dissipation associated with those buses can be significant for high-speed communication. The technique relies on the observation of data characteristics over fixed window sizes and formation of cluster wit...

In order to meet superior performance metrics along with denser logic integration and device miniaturization, FPGAs have become more susceptible to transistor related aging, coupled with manufacturing defects owing to increased complexity in photolithographic techniques, thereby reducing the reliability and lifetime. In this paper, we propose certa...

This paper presents a framework based on the logarithmic number system to implement adaptive filters with error nonlinearities in hardware. The framework is demonstrated through pipelined implementations of two recently proposed adaptive filtering algorithms based on logarithmic cost, namely, least mean logarithmic square (LMLS) and least logarithm...

This study presents a COordinate rotation DIgital computer (CORDIC)-based novel architecture combining the sliding discrete Fourier transform (DFT) with Hann windowing to reduce the leakage effect of the DFT spectrum. The proposed architecture also presents a refreshing approach to minimise error due to the finite word-length in the output windowed...

This paper investigates the problem of implementing proportionate-type LMS family of algorithms in hardware for sparse adaptive filtering applications especially the network echo cancelation. We derive a re-formulated proportionate type algorithm through algorithm-architecture co-design methodology that can be pipelined and has an efficient archite...

Cellular Automata (CA) circuits have received significant attention for efficient hardware implementation of Built-In Self-Test (BIST) structures or pseudorandom number generators (PRNGs). In this paper, we have presented an efficient automation technique of linear computational complexity, to generate design descriptions of high performance FPGA b...

The study presents the algorithm design, non-ideal effect analysis, architectural analysis and design, circuit analysis and design of an iterative frequency calibration system that corrects frequencies consuming very low energy. The method is based on measuring the 'fraction' portion when an oscillator frequency (typically of a radio frequency osci...

M-PSK (phase shift keying) modulation schemes are used in many high-speed applications like satellite communication, as they are more bandwidth and power efficient compared with other schemes. This study presents very large scale integrated circuits (VLSI) architectures for modulators and demodulators of quadrature phase shift keying (QPSK), 8PSK a...

This work presents an FPGA prototyping of a new low latency pipelined CORDIC-like rotator. The proposed rotator predicts the directions for all rotations in parallel and determines the final coordinates using the architecture with logarithmic relation between the number stages and precision of the target angle. The functionality of the pipelined CO...

Conditional carry adder has the advantage of best delay characteristics compared to other fast adders. This article presents approximate models of conditional carry adder (CCA), suitable in considering for error tolerant applications. Four approximate models (Approx1, Approx2, Approx3, and Approx4) with different levels of approximation have been p...

Motion estimation (ME) accounts for the major part of computational complexity of any video coding standard. The diamond search (DS) algorithm is widely used as a fast search technique to perform motion estimation. In this paper, a novel architecture for the diamond search technique is proposed that efficiently handles memory addressing and reduces...

While designing fault tolerant systems using dynamic reconfiguration, choice regarding the size of the granule influences the area, the power and the delay overheads. In this paper, attempt has been made to determine the optimum granule size that would incur minimum overhead vis-à-vis other design parameters such as the number of faults to be toler...

This paper presents a simple hardware architecture for quadtree(QT) partitioning based fractal image decoder. The decoding process in fractal based compression technique is an iterative process and utilizes the parameters extracted during encoding for converging to a fixed point, that approximates the original image. The adaptive sized partitioning...

An area efficient and high speed architecture design of hard decision Viterbi decoder with encoding rate of 1/2 and constraint length of k = 3 is presented in this paper for the application in satellite communication. The proposed Viterbi decoder is implemented in field programmable gate array (FPGA) and also in application specific integrated circ...

Scan flip -- flop insertion for aiding design for testability invites additional hardware overhead, thereby deteriorating the performance of the circuit. In this paper, we shall demonstrate a novel FPGA based implementation of inserting scan registers in commonly used Finite State Machines and pipelined data path circuits with no hardware overhead...

This paper presents an efficient hardware architecture for implementing fractal image compression (FIC) algorithm aimed toward image compression with improved encoding speed. The proposed architecture follows the full-search-based FIC scheme. Parallel processing has been effectively used in the present work to achieve the goal of reducing the time...

Motion estimation is the most computationally intensive part of any video coding standard. The three-step search algorithm is a popular fast search technique to reduce complexity in motion estimation. In this paper, we propose a novel architecture for the three-step search technique that simplifies memory addressing and reduces hardware complexity....

In the current era of speed and recent trend of device miniaturisation, failure rates have been increased with the increase in the design complexity and the density of transistors in chip and hence reliability issues at circuit level have become more prominent and challenging. In this study, the authors propose a new static fault tolerant method ca...

This paper presents the design philosophy of a fault tolerant conditional sum adder that uses hot-standby technique, which is an online swapping process of faulty components of a circuit by fault-free spares without interrupting the normal operation of the system. We have used dynamic recovery scheme in fault detection and correction and made the m...

In this paper, a parallel architecture for the computation of one dimensional discrete Mellin transform (DMT) is proposed for real time hardware implementation. Since Mellin transform is a useful technique in pattern recognition, speech processing, image registration and signal detection due to its scale invariant property, so it is essential to de...

A fast search based architecture for fractal image encoder, which efficiently exploits parallelism, is proposed. Speed up in encoding is achieved through parallel processing by finding data independency in different mathematical operations carried out in fractal encoding. This architecture requires 531 milli seconds to encode a 256×256 gray scale i...

In this paper the design of an ultra low power transmitter in MICS/ISM band has been presented. The transmitter uses Frequency Shift Keying (FSK) as the modulation scheme. At the heart of the transmitter is an oscillator whose frequency is periodically calibrated. A ring type oscillator has been considered instead of LC type as it reduces the buffe...

In this paper, a modelling technique for anisotropic magneto-resistors (AMRs) and piezo-resistors has been developed. These models are then used to model sensors using such elements. The motivation is to develop a platform which will help in the analysis of different performance parameters of such sensors and optimally design electronic systems for...

A low voltage, low power, resistive sensor architecture is proposed in this paper. The architecture is novel as it enhances the sensitivity along the main axis as well as reducing the impact of cross axes components. The proposed scheme also allows the simultaneous measurement of sensitivity along six different axes. With less than 15% of the power...

Windowing techniques have been widely used for preprocessing of samples before fast Fourier transform (FFT) in real time spectral analysis to minimize spectral leakage and picket fence effect. Among all popular window functions, Kaiser-Bessel window is an obvious choice for its better spectral characteristics. In this paper, CORDIC (CO-ordinate Rot...

In the era of deep sub-micron technology, probability of chip failure has been increased with increase in chip density. A system must be fault tolerant to decrease the failure rate and increase the reliability of it. Multiple faults can affect a system simultaneously and there is a trade-off between area overhead and number of faults tolerated. Thi...

In this paper, an efficient VLSI architecture of a hierarchical block matching algorithm has been proposed for motion estimation. At the lowest resolution level, two motion vector (MV) candidates are selected to get better performance. In the next search level, these two candidates provide the center points for local searches to get one MV candidat...

In this paper, a pipelined architecture using CORDIC for realization of transform domain equalizer is presented. Transform domain equalizer has much faster convergence than its time domain counterpart for practical hardware realization having nonzero adaptation delay. Here running DFT is employed as the transform, and CORDIC is used for realization...

Spectrum analyzer is perhaps the most useful instrument that finds its application in almost every branch of engineering. In this work, a pipelined architecture of a hardware economic spectrum analyzer has been presented that incorporates the zooming capability with a nominal increase in the hardware complexity. Sliding window DFT algorithm has bee...

Fault Tolerance is the ability of a system to detect and recover from a fault in the system. By incorporating fault tolerant features in any architecture, reliability and durability of the system increases at the cost of increased hardware. There must be a good tradeoff between cost and system performance. For all critical applications the system m...

We proposed a sampled analog VLSI architecture to implement discrete Haar wavelet transform (DHWT). Gain-boosted folded cascode operational amplifier based switched capacitor integrator circuit serves as the building block for the proposed architecture. This architecture performs DHWT operation on real-time samples which are discrete in time but co...

A real-time sampled analog VLSI architecture is designed to implement discrete Daubechies wavelet transform (DDWT). This architecture process discrete time continuous level samples that avoids the requirement of complex data converters, where as in digital architectures these data converters are necessary to generate digital samples that consumes e...

A discrete time continuous level VLSI architecture in current mode is proposed to implement 1-D Discrete Haar Wavelet Transform (DHWT). This architecture is implemented in current mode on unquantized samples, to achieve high dynamic range that is suitable for high frequency applications. DHWT is performed on the incoming samples which are available...

Fault tolerance is the ability of a system to retain its normal operation without failure when some part of the system fails to operate properly. It increases the wear-out time for any system at a cost of increased hardware. Fault tolerant approaches must be incorporated in any safety-critical system for continuing its job without failure even if a...

In this paper, a modulation technique, viz., differential frequency shift keying (DFSK), has been proposed for ultralow power wireless sensor node applications, which has been shown to be the most energy-efficient transmission technique for short-distance wireless communication systems, such as wireless body area network. The proposed technique is...

This paper proposes a novel memory architecture, introducing Random Access Analog Memory (RA2M), to store unquantized samples of video signal of maximum 5 MHz bandwidth for storing time duration in order of millisecond by implementing periodic memory refreshing mechanism in it. At 16.5 MHz sampling frequency with 25 frames/s frame rate, this implem...

In this paper, a new redundant scalable CORDIC-like architecture is proposed for the implementation of fast rotation. The sequential nature of the conventional CORDIC algorithm in determining the direction of rotations is eliminated by computing the directions from the target angle. The proposed architecture offers high regularity and modularity. D...

This paper describes a sampled analog architecture to compute discrete linear transforms, DXT(X=C/H/S/F), using switched capacitor blocks fed with current samples. The scheme uses matrix representation of any DXT kernel, and multiplies each column of the kernel matrix with the input samples simultaneously, using an array of current scalers. It is s...

In this work, a hardware efficient and flexible architecture has been proposed for computing Log Polar Transformation (LPT) for real time applications in image processing and pattern recognition. CORDIC (COordinate Rotational DIgital Computing) is used as a building block for our proposed architecture, so as to keep the design flexible that can be...

Since decades, fractional Fourier transform has taken a considerable attention for various applications in signal and image processing domain. On the evolution of fractional Fourier transform and its discrete form, the real time computation of discrete fractional Fourier transform is essential in those applications. On this context, we have propose...

This paper describes a simple method of calculating delay of an RC ladder which is often encountered in VLSI interconnect analysis. The method first deals with a specific case where R and C are identical and the transfer function in closed form, is derived for arbitrary number of stages. The roots of the transfer function is then found in closed fo...

A new scaled radix-4 CORDIC architecture that incorporates pipelining and parallelism is presented. The latency of the architecture is n/2 clock cycles and throughput rate is one valid result per n/2 clocks for n bit precision. A 16 bit radix-4 CORDIC architecture is implemented on the available FPGA platform. The corresponding latency of the archi...

Mellin transform (MT) due to its scale invariance property finds itself in a myriad of applications. This work introduces row column decomposition (RCD) based, area efficient MT implementation for real time scale analysis of images. The proposed CORDIC based, multiplierless and fully pipeline architecture sidesteps the transposition operation in co...

In the last decade, CORDIC algorithm has drawn wide attention from academia and industry for various applications such as DSP, biomedical signal processing, software defined radio, neural networks, and MIMO systems to mention just a few. It is an iterative algorithm, requiring simple shift and addition operations, for hardware realization of basic...

In this paper, we propose an integrated voice and data transmission technique using adaptive modulation, wherein the effective data transmission rate (throughput) is improved by allowing the bit-error rate (BER) for voice to increase beyond the BER needed for data. In a given integrated frame with data and voice bits, voice bits are allowed to use...

The Mellin transform (MT) is a form of a signal representation similar to Fourier transform (FT) which has been widely used in signal processing owing to its distinct properties like scale invariance. In this work, a 2D form of MT which is termed as 2D discrete Mellin transform (DMT) is introduced. The paper also proposes an area efficient, power a...

Coordinate rotation digital computer (CORDIC) based digital signal processing has become an important tool in consumer, communications, biomedical, and industrial products, providing designers with significant impetus for porting algorithm into architecture. Unfolded implementations of CORDIC algorithm can achieve low latency for rotation and vario...

The current trend of hardware intensive signal processing is based on the CORDIC. Over the years many architectures have been proposed to address issues pertaining to throughput and latency. In this paper, we are proposing a pipelined architecture for the VLSI implementation of radix-4 CORDIC rotator with redundant arithmetic to achieve low latency...

Advances in the VLSI technology have provided designers with significant impetus for porting algorithm into architecture. In this paper, we propose an architecture with low latency for the implementation of CORDIC algorithm in rotation mode suited for parallel and pipelined operation. In our proposed architecture, redundant radix-4 arithmetic is em...