Andreas Gothenberg

STINT, The Swedish Foundation for International Cooperation in Research and Higher Education

This paper presents a high resolution time-to-digital converter (TDC) architecture, which combines the advantages of sub-ranging and Vernier delay line TDCs. In the proposed TDC, the time input is converted to a digital code in a coarse–fine manner by two stages of parallel delay lines. Both stages have coarse (but slightly different) time resoluti...

Strategic internationalization is critical for the competitiveness of individual universities as well as the knowledge system of nations. We present some of the challenges that have been identified in a series of interviews with the leaderships at several universities in Sweden. We also present strategic measures intended to tackle some of these c...

This letter proposes a new parallel delay-line time-to-digital converter (TDC) architecture based on the Vernier principle. Two parallel delay-line stages with slightly different incremental step sizes are cascaded, resulting in a finer resolution compared to the traditional parallel delay line. A 2-bit TDC fabricated in a 0.18 μm CMOS technology d...

This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the invert...

It has recently become very popular to feedforward the input signal in wideband delta-sigma modulators, so that the integrators only process quantization errors. The advantage being that the actual signal is not distorted by opamp and integrator nonlinearities. In this paper, we focus on improved feedforward techniques for cascaded delta-sigma modu...

In any data converter system, the linearity of the sampling switch is a very critical parameter, especially for wideband sigma-delta modulators. Distortion introduced in the sampling instance directly degrades the quality of the input signal. In this paper we present analyses of a set of sampling switches in the frequency and voltage domains in ord...

This paper presents a theoretical overview and analysis of clock jitter in a switched capacitor (SC) Sigma-Delta (ΣΔ) Analog-to-Digital Converter (ADC). We start by defining three different types of jitter effects and proceed to analyze their impact, both mathematically and by simulations. The main jitter assumption throughout this analysis is that...

The continuous evolution of CMOS technologies towards deepsubmicron processes has provided new opportunities for integration of mixed-signal systems on single monolithic integrated circuits. In order to find the optimal usage of CMOS technology and robustness against undesired mixed-signal couplings, new approaches to CMOS front-end integration are...

This paper presents the effect of nonlinearities on data converter resolution. Two models, an exponential and a sinusoidal approach, are proposed to estimate the drop in signal to noise (+distortion) ratio (SNDR). Matlab simulation results predict a loss between 1 dB and 10 dB when introducing a nonlinearity error of up to 2 LSB. These models were...

An improved cascaded sigma-delta noise shaper with reduced sensitivity to switch and opamp nonlinearities is presented. The architecture can be used for wideband applications, i.e. RF-front ends, at low oversampling ratio, as well as for high-resolution audio applications

Baseband signal processing for current base stations or 3rd generation mobile systems will impose high bandwidth and high VLSI integration demand. Many of the desired integration aspects can be satisfied with sigma-delta converter front-ends. However, under the technology constraints there are simultaneous requirements for high sample rate and low...

This paper presents a theoretical overview and analysis of the main types of clock jitter in a switched capacitor (SC) Sigma-Delta (ΣΔ) Analog-to-Digital-Converter (ADC). We start by defining the different types of jitter and proceed to analyze their impact both theoretically and by simulations. The main jitter assumption throughout this paper is t...

As the operating speed of CMOS transistors increases, the natural consequense is to clock circuits at a higher rate. This enables data converters, and especially Sigma-Delta (ΣΔ) Analog-to-Digital converters (ADCs), to operate at higher frequencies. Previously, ΣΔ ADCs were mainly used for audio applications because of their high resolution in that...

The sampling switch of a wideband sigma-delta noise shaper for RF applications is a very critical component as any nonlinearities within reduces the spurious free dynamic range, SFDR, of the whole modulator. Errors due to nonlinearities are carried on to all other processing stages. The analysis investigates a variety of sampling switches. It is fo...

This paper presents methods to model and analyze substrate coupled noise in pipelined data converters. The substrate noise models covers substrate types, such as lightly and highly doped substrates, and the analyzes includes the effects on the pipelined data converter performance from a variety of noise shielding techniques, such as guarding and we...

This paper demonstrates a method for determining the stability and sensitivity of feedback coefficient variations of sigma delta noise shapers using a model based on parameterized quantization gain which varies from sample to sample. The method is demonstrated for two types of sigma delta converter structures, the 4th order multibit cascaded struct...

Baseband signal processing for current base stations or 3rd generation mobile systems will impose high bandwidth and high VLSI integration demand. Many of the desired integration aspects can be satisfied with sigma-delta converter front-ends. However, under the technology constraints there are simultaneous requirements for high sample rate and low...

Baseband signal processing for current base stations or 3rd generation mobile systems will impose high bandwidth and high VLSI integration demand. Many of the desired integration aspects can be satisfied with sigma-delta converter front-ends. However, under the technology constraints there are simultaneous requirements for high sample rate and low...