Amirreza Yousefzadeh

University of Twente | UT · Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS)

For Edge AI applications, deploying online learning and adaptation on resource-constrained embedded devices can deal with low-latency sensor-generated data streams in changing environments. However, since maintaining low-latency and power-efficient inference is paramount at the Edge, online learning and adaptation on the device should impose minima...

Event-driven neuromorphic processors for artificial intelligence (AI) inference on edge/IoT devices require large on-chip memory capacity, for efficient execution of spiking neural networks (NNs). In this work, we evaluate 3-D stacking benefits on SENECA, a digital neuromorphic accelerator core, sweeping its on-chip memory capacity from 2 up to 32...

Current Artificial Intelligence (AI) computation systems face challenges, primarily from the memory-wall issue, limiting overall system-level performance, especially for Edge devices with constrained battery budgets, such as smartphones, wearables, and Internet-of-Things sensor systems. In this paper, we propose a new SRAM-based Compute-In-Memory (...

Currently, neural-network processing in machine learning applications relies on layer synchronization, whereby neurons in a layer aggregate incoming currents from all neurons in the preceding layer, before evaluating their activation function. This is practiced even in artificial Spiking Neural Networks (SNNs), which are touted as consistent with n...

Spiking neural networks (SNNs) for event-based optical flow are claimed to be computationally more efficient than their artificial neural networks (ANNs) counterparts, but a fair comparison is missing in the literature. In this work, we propose an event-based optical flow solution based on activation sparsification and a neuromorphic processor, SEN...

In this paper, we present SENSIM, which is an open-source simulator designed specifically for the SENECA neuromorphic processor. This simulator is unique in that it combines features from both hardware-specific and hardware-agnostic spiking neural network simulators, resulting in a hybrid event-driven and time-step-driven simulation approach. This...

Neuromorphic processors are well-suited for efficiently handling sparse events from event-based cameras. However, they face significant challenges in the growth of computing demand and hardware costs as the input resolution increases. This paper proposes the Trainable Region-of-Interest Prediction (TRIP), the first hardware-efficient hard attention...

For Edge AI applications, deploying online learning and adaptation on resource-constrained embedded devices can deal with fast sensor-generated streams of data in changing environments. However, since maintaining low-latency and power-efficient inference is paramount at the Edge, online learning and adaptation on the device should impose minimal ad...

Neuromorphic processors promise low-latency and energy-efficient processing by adopting novel brain-inspired design methodologies. Yet, current neuromorphic solutions still struggle to rival conventional deep learning accelerators' performance and area efficiency in practical applications. Event-driven data-flow processing and near/in-memory comput...

Smart computing on edge-devices has demonstrated huge potential for various application sectors such as personalized healthcare and smart robotics. These devices aim at bringing smart computing close to the source where the data is generated or stored, while coping with the stringent resource budget of the edge platforms. The conventional Von-Neuma...

Neuromorphic processors aim to emulate the biological principles of the brain to achieve high efficiency with low power consumption. However, the lack of flexibility in most neuromorphic architecture designs results in significant performance loss and inefficient memory usage when mapping various neural network algorithms. This paper proposes SENEC...

The role of axonal synaptic delays in the efficacy and performance of artificial neural networks has been largely unexplored. In step-based analog-valued neural network models (ANNs), the concept is almost absent. In their spiking neuroscience-inspired counterparts, there is hardly a systematic account of their effects on model performance in terms...

The field of neuromorphic computing holds great promise in terms of advancing computing efficiency and capabilities by following brain-inspired principles. However, the rich diversity of techniques employed in neuromorphic research has resulted in a lack of clear standards for benchmarking, hindering effective evaluation of the advantages and stren...

Sparse and event-driven spiking neural network (SNN) algorithms are the ideal candidate solution for energy-efficient edge computing. Yet, with the growing complexity of SNN algorithms, it isn't easy to properly benchmark and optimize their computational cost without hardware in the loop. Although digital neuromorphic processors have been widely ad...

Activation sparsity can improve compute efficiency and resource utilization in sparsity-aware neural network accelerators. While spatial sparsification of activations is a popular topic in DNN literature, introducing and exploiting spatio-temporal sparsity is a topic much less explored in DNN literature. However, it is in perfect resonance with the...

Computation-in-Memory (CIM) is an emerging computing paradigm to address memory bottleneck challenges in computer architecture. A CIM unit cannot fully replace a general-purpose processor. Still, it significantly reduces the amount of data transfer between a traditional memory unit and the processor by enriching the transferred information. Data tr...

SENeCA is our first RISC-V-based digital neuromorphic processor to accelerate bio-inspired Spiking Neural Networks for extreme edge applications inside or near sensors where ultra-low power and adaptivity features are required. SENeCA is optimized to exploit unstructured spatio-temporal sparsity in computations and data transfer. It is a digital IP...

The European project ANDANTE [1] aims at providing neuro-inspired and/or energy-efficient hardware accelerators for running AI applications at the edge. Given the wealth of applications targeted, with various processing needs and sensors involved, several implementations are pursued in parallel: (1) fully digital or analog-mixed signal; (2) with cl...

SENeCA is a RISC-V-based digital neuromorphic processor targeting extreme edge applications by accelerating Spiking Neural Networks inside or near sensors and small devices where ultra-low power and adaptivity are required • SENeCA inherits fundamental properties from the biological brain:-Spatio-temporal sparsity exploitation-Parallel processing-I...

Activation sparsity improves compute efficiency and resource utilization in sparsity-aware neural network accelerators. As the predominant operation in DNNs is multiply-accumulate (MAC) of activations with weights to compute inner products, skipping operations where (at least) one of the two operands is zero can make inference more efficient in ter...

The development of brain-inspired neuromorphic computing architectures as a paradigm for Artificial Intelligence (AI) at the edge is a candidate solution that can meet strict energy and cost reduction constraints in the Internet of Things (IoT) application areas. Toward this goal, we present μBrain: the first digital yet fully event-driven without...

We present a novel computing architecture which combines the event-based and compute-in-network principles of neuromorphic computing with a traditional dataflow architecture. The result is a fine-grained dynamic dataflow system which avoids the coding issues intrinsic to spiking systems, and is suitable for both procedural workload and deep neural...

Biological neurons are known to have sparse and asynchronous communications using spikes. Despite our incomplete understanding of processing strategies of the brain, its low energy consumption in fulfilling delicate tasks suggests the existence of energy efficient mechanisms. Inspired by these key factors, we introduce SpArNet, a bio-inspired quant...

Inference of Deep Neural Networks for stream signal (Video/Audio) processing in edge devices is still challenging. Unlike most state of the art inference engines which are efficient for static signals, our brain is optimized for real-time dynamic signal processing. We believe one important feature of the brain (asynchronous state-full processing) i...

Artificial Neural Networks (ANNs) show great performance in several data analysis tasks including visual and auditory applications. However, direct implementation of these algorithms without considering the sparsity of data requires high processing power, consume vast amounts of energy and suffer from scalability issues. Inspired by biology, one of...

In computational neuroscience, synaptic plasticity learning rules are typically studied using the full 64-bit floating point precision computers provide. However, for dedicated hardware implementations, the precision used not only penalizes directly the required memory resources, but also the computing, communication, and energy resources. When it...

Interest in event-based vision sensors has proliferated in recent years, with innovative technology becoming more accessible to new researchers and highlighting such sensors' potential to enable low-latency sensing at low computational cost. These sensors can outperform frame-based vision sensors regarding data compression, dynamic range, temporal...

Vision processing with Dynamic Vision Sensors (DVS) is becoming increasingly popular. This type of bio-inspired vision sensor does not record static scenes. DVS pixel activity relies on changes in light intensity. In this paper, we introduce a platform for object recognition with a DVS in which the sensor is installed on a moving pan-tilt unit in c...

Neuromorphic engineering is a new emerging technology that tries to bring intelligence and efficiency of biological brain to silicon hardware. Conventional processors are not able to simulate biological neurons efficiently due to the entirely different structure of neural networks. Neuromorphic engineering tries to provide efficient solutions for i...

The SpiNNaker chip is a multi-core processor optimized for neuromorphic applications. Many SpiNNaker chips are assembled to make a highly parallel million core platform. This system can be used for simulation of a large number of neurons in real-time. SpiNNaker is using a general purpose ARM processor that gives a high amount of flexibility to impl...

Address-Event-Representation (AER) is a widely employed asynchronous technique for interchanging “neural spikes” between different hardware elements in Neuromorphic Systems. Each neuron or cell in a chip or a system is assigned an Address (or ID) which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number...

We present a highly hardware friendly STDP (Spike Timing Dependent Plasticity) learning rule for training Spiking Convolutional Cores in Unsupervised mode and training Fully Connected Classifiers in Supervised Mode. Examples are given for a 2-layer Spiking Neural System which learns in real time features from visual scenes obtained with spiking DVS...

This is a proposal for live demonstration of a hardware that can learn visual feature online and in real-time during presentation of an object. Input Spikes are coming from a bio-inspired silicon retina or Dynamic Vision Sensor (DVS) and will be processed in a Spiking Convolutional Neural Network (SCNN) that is equipped with Synaptic Time Dependent...

We propose demonstration of a serial link for fast asynchronous communication in massively parallel platforms connected to DVS for real-time implementation of bio-inspired vision processing and spiking neural networks. This demonstration is associated with the track ??. Associated paper submission identifier: ??.

Address-Event-Representation (AER) is a widely extended asynchronous technique for interchanging " neural spikes " among different hardware elements in Neuromorphic Systems. Conventional AER links use parallel physical wires together with a pair of handshaking signals (Request and Acknowledge). Here we present a fully serial implementation using bi...

We present a new passive and low power localization method for quadcopter UAVs (Unmanned aerial vehicles) by using dynamic vision sensors. This method works by detecting the speed of rotation of propellers that is normally higher than the speed of movement of other objects in the background. Dynamic vision sensors are fast and power efficient. We h...

A method of performing unsupervised detection of repeating patterns in a series (TS) of events (E21, E12, E5 ...), comprising the steps of: a) Providing a plurality of neurons (NR1 - NRP), each neuron being representative of W event types; b) Acquiring an input packet (IV) comprising N successive events of the series; c) Attributing to at least som...

A digital electronic circuit (SNN) implementing a spiking neural network comprising: an input unit, (IU) for receiving a series of digital signals (ES) representing respective events and for generating a data packet (PK) representative of N contiguous signals of the series, with 1≤N≤M; - a memory (NM) storing data defining a plurality of neurons, c...

Asynchronous handshaken interchip links are very popular among neuromorphic full-custom chips due to their delay-insensitive and high-speed properties. Of special interest are those links that minimize bit-line transitions for power saving, such as the two-phase handshaken non-return-to-zero (NRZ) 2-of-7 protocol used in the SpiNNaker chips. Interf...

https://youtu.be/S9CX7tGEboo

This paper describes a digital implementation of a parallel and pipelined spiking convolutional neural network (S-ConvNet) core for processing spikes in an event-driven system. Event-driven vision systems use typically as sensor some bio-inspired spiking device, such as the popular Dynamic Vision Sensor (DVS). DVS cameras generate spikes related to...

Small tutorial for Verilog in Persian, I prepared this when I was teaching Verilog in logic circuit lab of Amirkabir university of technology

Ethernet is among the most popular forms of data networking in the world. It has been widely used for local area networks and recently, it has also become very popular in metro area networks. As the usage of Ethernet grows, security and privacy of data transport using Ethernet becomes more important. As a result, there have been a lot of developmen...