Amin Rezaei

Amin Rezaei
California State University, Long Beach | CSULB · Department of Computer Engineering & Computer Science

About

30
Publications
3,080
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295
Citations

Publications

Publications (30)
Conference Paper
Reliability is a critical feature of chip integration and unreliability can lead to performance, cost, and time-to-market penalties. Moreover, upcoming Many-Core System-on-Chips (MCSoCs), notably future generations of mobile devices, will suffer from high power densities due to the dark silicon problem. Thus, in this paper, a novel NoC-based MCSoC...
Conference Paper
Logic encryption has attracted much attention due to increasing IC design costs and growing number of untrusted foundries. Unreachable states in a design provide a space of flexibility for logic encryption to explore. However, due to the available access of scan chain, traditional combinational encryption cannot leverage the benefit of such flexibi...
Article
In order to fulfill the ever-increasing demand for high-speed and high-bandwidth, wireless-based MCSoC is presented based on a NoC communication infrastructure. Inspiring the separation between the communication and the computation demands as well as providing the flexible topology configurations, makes wireless-based NoC a promising future MCSoC a...
Chapter
Chaos is a deterministic phenomenon that emerges under certain conditions in a nonlinear dynamic system when the trajectories of the state variables become periodic and highly sensitive to the initial conditions. Chaotic systems are flexible, and it has been shown that communication is possible using parametric feedback control. Chaos synchronizati...
Conference Paper
In the presence of complicated kinematic and dynamic, we present a generalizable robust control technique for the 6-Degree of Freedom (6DoF) Stewart integrated platform with revolving, time-delayed torque control actuators to achieve faster, and reliable efficiency for parallel control manipulators. The suggested optimal solution involves the const...
Preprint
Full-text available
Supervised learning on Deep Neural Networks (DNNs) is data hungry. Optimizing performance of DNN in the presence of noisy labels has become of paramount importance since collecting a large dataset will usually bring in noisy labels. Inspired by the robustness of K-Nearest Neighbors (KNN) against data noise, in this work, we propose to apply deep KN...
Preprint
Full-text available
Integrated circuits (ICs) are the foundation of all computing systems. They comprise high-value hardware intellectual property (IP) that are at risk of piracy, reverse-engineering, and modifications while making their way through the geographically-distributed IC supply chain. On the frontier of hardware security are various design-for-trust techni...
Article
Full-text available
The combination of traditional wired links for regular transmissions and express wireless paths for long distance communications is a promising solution to prevent multi-hop network delays. In wireless network-on-chip technology, wireless-equipped routers are more error-prone than the conventional ones not only because of their implementation compl...
Article
Full-text available
In the current many-core architectures, network-on-chips (NoCs) have been efficiently utilized as communication backbones for enabling massive parallelism and high degree of integration on a chip. In spite of the advantages of conventional NoCs, wired multi-hop links impose limitations on their performance by long delay and much power consumption e...
Conference Paper
Cyclic logic encryption is newly proposed in the area of hardware security. It introduces feedback cycles into the circuit to defeat existing logic decryption techniques. To ensure that the circuit is acyclic under the correct key, CycSAT is developed to add the acyclic condition as a CNF formula to the SAT-based attack. However, we found that it i...
Conference Paper
Logic encryption is an important hardware protection technique that adds extra keys to lock a given circuit. With recent discovery of the effective SAT-based attack, new enhancement methods such as SARLock and Anti-SAT have been proposed to thwart the SAT-based and similar exact attacks. Since these new techniques all have very low error rate, appr...
Chapter
MCSoCs, with their scalability and parallel computation power, provide an ideal implementation base for modern embedded systems. However, chip designers are facing a design challenge wherein shrinking component sizes though have improved density but started stressing energy budget. This phenomenon, that is called utilization wall, has revolutionize...
Conference Paper
Because of high bandwidth, low latency and flexible topology configurations provided by wireless NoC, this emerging technology is gaining momentum to be a promising future on-chip interconnection paradigm. However, congestion occurrence in wireless routers reduces the benefit of high speed wireless links and significantly increases the network late...

Projects

Projects (3)
Project
With increasing complexity and cost of modern Integrated Circuits (ICs), a design house has to seek the aid from various external agencies, such as Electronic Design Automation (EDA) companies, Intellectual Property (IP) vendors, library providers, and fabrication foundries. The active participation of external entities in the design and manufacturing flow has produced numerous hardware security issues. Most leading-edge design houses have out-sourced their fabrication to the offshore foundries for the sake of lower labor and manufacturing cost. However, many offshore foundries are hard to be trusted since they may be in a country without consummate enforcement law for IP protection. The economic impacts and security hazards of hardware piracy is not apt to be neglected compared to software, but is even more severe. In this project, we are developing a thorough hardware security framework. Our approach is based on a novel separation between two entangled goals in hardware security: logic locking and circuit obfuscation. Locking is a logical request to make sure that the correct behavior only happens when the correct key is applied and the correct key cannot be easily figured out by studying the logic of the locked circuit. Obfuscation is a structural request to make sure that the correct key or the original circuit cannot be revealed by any structural analysis of the obfuscated circuit.
Project
Many-Core System-on-Chips (MCSoCs) with their scalability and parallel computation power, provide an ideal implementation base for modern embedded systems. However, chip designers are facing a design challenge wherein shrinking component sizes though have improved density but started stressing energy budget. As a result, only some parts of the entire chip can be run at maximum permissible frequency while the remaining parts should either be switched off (i.e. dark silicon) or run at lower frequency (i.e. dim silicon). This phenomenon of limiting performance rating, has revolutionized the semiconductor industry by shifting the main purpose of chip design from a performance-driven approach to a complex multi-objective one. In order to efficiently address the above challenges, in this project we are proposing a hierarchical MCSoC platform. We have introduced a fine-grained NoC-based MCSoC architecture along with core behavior model, system topology, application migration scheme, and controlling mechanism in order to handle high-performance Quality-of-Service (QoS)-aware mobile demands.. Moreover, we have proposed a temperature and congestion aware task mapping algorithm in order to solve some of the key concerns in future NoC-based MCSoCs.
Project
Nowadays, commercial Many-Core System-on-Chips (MCSoCs) are available based on Network-on-Chip (NoC) communication infrastructure. It is also predicted that upcoming MCSoCs will progressively continue operating on completely new principles and novel NoC-based architectures. In comparison with the traditional bus interconnection networks, mesh-based NoC provides more regular, scalable, and flexible framework. Although mesh-based NoC architecture has many advantages, its multi-hop nature places a negative impact on latency of the system. This will become even more challenging when the network size will be increased by technology scaling. This project has aimed at developing a new on-chip interconnection network, dubbed Wireless Network-on-Chip (WNoC) to sustain the exponential growth of computing performance in the next generation Gigascale MCSoCs. In this project, we have designed WNoC from various crucial aspects. The system architecture is designed in a way that decouples communication from computation. Also, a layered architecture including application mapping, application migration, and routing layers is specially designed to tackle distinct features of WNoC from conventional NoCs and to simplify the hardware implementation.