Alexandre M. Amory

• PhD
• Research Associate at Pontifical Catholic University of Rio Grande do Sul

Teaching computer programming to the visually impaired is a difficult task that has sparked a great deal of interest, in part due to its specific demands. Robotics has been one of the strategies adopted to help in this task. One system that uses robotics to teach programming for the visually impaired, called Donnie, has as its key part the need to...

In this paper, we propose a mobile robot localization system based on the Received Signal Strength Indicator (RSSI) of three radio module beacons, to enhance or replace GPS positioning in scenarios with little or no GPS availability, such as urban environments with blocked sky view (near buildings or tall trees). Our approach uses an Extended Kalma...

This work presents GoDonnie a programming language to command a robot to improve orientation and mobility(O&M) skills in people who are visually impaired (PVI). The GoDonnie programming language is based on the Logo language. GoDonnie runs in a programming environment called Donnie. This environment has a 2D graphic simulator with a virtual robot,...

The use of robotics in disaster scenarios has become a reality. However, an Unmanned Surface Vehicle (USV) needs a robust navigation strategy to face unpredictable environmental forces such as waves, wind, and water current. A starting step toward this goal is to have a programming environment with realistic USV models where designers can assess th...

Disaster robotics has become a research area in its own right, with several reported cases of successful robot deployment in actual disaster scenarios. Most of these disaster deployments use aerial, ground, or underwater robotic platforms. However, the research involving autonomous boats or Unmanned Surface Vehicles (USVs) for Disaster Management (...

The Q-Flop is an alternative memory element for designs that are prone to metastability. It has been substantially explored by past research work, specially in synchronization schemes. However, there is very limited support to test insertion on these critical components. This brief presents a testable Q-flop cell and a methodology to integrate it t...

Reports on the RAS 2017 Humanitarian Robotics and Automation Technology Challenge.

Resilient architectures emerged as a promising solution to remove worst-case timing margins added due to process, voltage and temperature variation, improving system performance while reducing energy consumption. Asynchronous circuits can also improve energy efficiency and performance due to the absence of a global clock. A recently proposed circui...

Shared memory and message passing are traditional parallel programming models used on multiprocessor system-on-chip environments. However, these models are traditionally meant for static scenarios where all communicating entities are known a priori by the user and are available at the same time and space to complete the interaction. Therefore, the...

This paper presents a systematic review of studies concerning the use of robotics for the programming education of individuals with visual impairment. This study presents a thorough discussion and classification of the surveyed papers, including: different programming teaching methodologies based on robotics for people who are blind; the use of sev...

Aggressive scaling of CMOS process technology allows the fabrication of highly integrated chips such as NoC-based MPSoCs. However, fault probability increases when devices’ size reduces. Hence, fault tolerant design has an important role in current nanometric technologies, leading to research on fault mitigation techniques for NoC-based MPSoCs. Mos...

Although it is possible to design and manufacture MPSoCs with hundreds of processors, there is still a gap in the ability to debug hardware, software, and applications for such chips. Current state-of-the-art works related to MPSoC debugging suffer from poor integration, scalability in data storage, and simple graphical data representation. This wo...

Type D flip-flop cell and its scannable version called Muxed-D are the most used sequential components in cell-based synchronous designs because it simplifies timing analysis and it is less susceptible to race problems. However, as technology nodes shrink, it becomes more difficult, especially for high-performance designs, to cope with a hard globa...

The continuing development of the silicon technology leads to systems with hundreds of processors interconnected by a network on chip (NoC-based MPSoCs). On one hand, the nanotechnology enables to develop such complex systems, but, on the other hand, the vulnerability to faults increases. The literature presents partial fault-tolerant approaches, t...

Programming autonomous multi-robot systems can be extremely complex without the use of appropriate software development techniques to abstract away the hardware heterogeneity and to overcome the complexity of distributed software to coordinate autonomous behavior. Moreover, real-world environments are dynamic, which can generate unpredictable event...

Analysis by Transcript gram was developed as a solution to reduce the noise in the micro array measuring technique of the Transcriptome, and has demonstrated potential to be applied as a method of disease diagnostics. The noise reduction in the measurement is achieved by ordering the proteins of a given protein interaction network in a linear way,...

Mechanisms for runtime fault-tolerance in Multi-Processor System-on-Chips (MPSoCs) are mandatory to cope with transient and permanent faults. This issue is even more relevant in nanotechnologies due to process variability, aging effects, and susceptibility to upsets, among other factors. The literature presents isolated solutions to deal with fault...

The design of reliable MPSoCs is mandatory to cope with faults during fabrication or product lifetime. For instance, permanent faults on the interconnect network can stall or crash applications even though the network has alternative fault-free paths to a given destination. This paper presents a novel fault-tolerant communication protocol that take...

Advances in design integration have enabled the integration of large Multiprocessor Systems-on-Chip (MPSoC). Such systems are prone to the execution of complex applications if high degree of parallelism is employed on the communication infrastructure. Network-on-Chip (NoC) has emerged as a new communication paradigm for large MPSoCs with advantages...

Intra-chip communication architectures evolved from buses to networks-on-chip, in order to provide design scalability and increased bandwidth. However, the predominant test architecture for SoCs is still based on buses. While this approach presents advantages, such as simple design and a mature set of automation tools, its scalability is questionab...

The advances in deep submicron technology have made the development of large Multiprocessor Systems-on-Chip (MPSoC) possible and Networks-on-Chip (NoCs) have been recognized to provide an efficient communication architecture for such systems. With the positive effects on the device's integration some drawbacks arise, such as the increase of fault s...

Mechanisms for fault-tolerance in MPSoCs are mandatory to cope with faults during fabrication or product lifetime. For instance, permanent faults on the interconnect network can stall or crash applications even though the network has alternative fault-free paths to a given destination. This PhD work presents a fault-tolerant communication protocol...

Conventional approaches using the Network-on-Chip (NoC) as Test Access Mechanism (TAM), called NoC TAM, model the test sources/sinks and the routing algorithm as constraints to the test scheduling, reducing its efficiency. This paper is based on a new NoC TAM model where these constraints do not exist, potentially resulting in shorter tests. The co...

Routing algorithms for NoCs were extensively studied in the last 12 years, and proposals for algorithms targeting some cost function, as latency reduction or congestion avoidance, abound in the literature. Fault-tolerant routing algorithms were also proposed, being the table-based approach the most adopted method. Considering SoCs with hundred of c...

This is the second and the last chapter of this book devoted to on-line Network-on-Chip (NoC) testing strategies. As mentioned before, the main difference of on-line and off-line tests is that the former detects run-time faults during system’s mission mode, while in the latter is typically used to detect manufacturing defects while the system is in...

The design and manufacturing of integrated circuits is currently based on the ­integration of a number of pre-designed intellectual property (IP) blocks, or cores, in a single chip. Although the reuse has always been present in the design of electronic circuits, this practice has been extended and formalized in the last two decades or so, becoming...

In complement to the previous chapter, this one discusses strategies to detect and diagnose manufacturing faults in the communication channels, thus covering altogether, the test of the whole Network-on-Chip (NoC) infrastructure. The huge number of interconnects allied to the shrinking of the chip dimensions make the NoC prone to a growing number o...

In this chapter we cover the first proposed test approaches that reuse the NoC as Test Access Mechanism (TAM) in a core-based system. First, the basic reuse strategy is presented, including the very few modifications implemented in the network interface, and the definition of the test packets to make the test possible. Then, two test scheduling app...

The test scheduling approaches discussed in Chap. 4 demonstrated that NoCs can be as a cost-effective TAM as a dedicated bus-based mechanism. Those approaches are based, however, on a single NoC model and on a few assumptions about the NoC, wrappers, and cores. Indeed, guaranteed services (GS) NoCs were assumed to meet the timing constraints of an...

This part of the book is devoted to on-line Network-on-Chip (NoC) testing strategies, while the previous part is devoted to off-line NoC testing strategies. The main difference is that the former detects run-time faults during system’s mission mode, while in the latter is typically used to detect manufacturing defects while the system is in test mo...

This chapter focuses on the testing of part of the Network-on-Chip (NoC) infrastructure, discussing strategies to detect and diagnose manufacturing faults in the routers. Test approaches for these NoC building blocks have based their strategies on functional test, scan-based testing or built-in self-test (BIST). The refereed fault models differ fro...

The design cycle of a complex system has greatly improved since the advent of the core-based design paradigm. Nevertheless, as technology evolves, new problems become the focus of attention. Currently, industry seems to be on pace in terms of design productivity and time-to-market, but yield, power dissipation, and reliability issues are still a ch...

As the number of IP modules in Systems-on-Chip (SoCs) increases, bus-based interconnection architectures may prevent these systems to meet the performance required by many applications. For systems with intensive parallel communication requirements buses may not provide the required bandwidth, latency, and power consumption. A solution for such a c...

Task mapping defines the best placement of a given task in the MPSoC, according to some criteria, as energy or Manhattan distance minimization. The ITRS roadmap forecast in a near future MPSoCs with hundreds of processing elements (PEs). Therefore, dynamic mapping heuristics are required. An important gap is observed in the mapping literature: the...

The use of existing Networks-on-Chip (NoCs) for test data transportation has been proposed to avoid conventional ded-icated Test Access Mechanism (TAM), improving the mod-ularity of the test architecture. This paper presents a wire length estimation method used to evaluate the cost of ded-icated TAMs for NoC-based SoCs early in the design flow. Thi...

The use of spare tiles in a networks-on-chip based multi-processor chip can improve the yield, reducing the cost of the chip and maintaining the system functionality even if the chip is defective. However, the impact of this approach on application characteristics, such as energy consumption and execution time, is not documented. For instance, on o...

Networks-on-Chip (NoCs) can be used for test data transportation during manufacturing tests. On one hand, NoC can avoid dedicated Test Access Mechanisms (TAMs), reducing long global wires, and potentially simplifying the layout. On the other hand, (a) it is not known how much wiring is saved by reusing NoCs as TAMs, (b) the impact of reuse-based ap...

The yield of homogeneous network-on-chip based multi-processor chips can be improved with the addition of spare tiles. However, the impact of this reliability approach on the chip energy consumption is not documented. For instance, in a homogeneous MPSoC, application tasks can be placed onto any tile of a defect-free chip. On the other hand, a chip...

The yield of homogeneous network-on-chip based multi-processor chips can be improved with the addition of spare tiles. However, the impact of this reliability approach on the chip energy consumption is not documented. For instance, in a homogeneous MPSoC, application tasks can be placed onto any tile of a defect-free chip. On the other hand, a chip...

The innovations on integrated circuit fabrics are continuously reducing components size, which increases the logic density of systems-on-chip (SoC), but also affect the reliability of these components. Chip-level global buses are especially subject to crosstalk faults, which can lead to increased delay and glitches. This paper evaluates different c...

A novel strategy to detect interconnect faults between distinct channels in networks-on-chip is proposed. Short faults between distinct channels in the data, control and communication handshake lines are considered in a cost-effective test sequence for Mesh NoC topologies based on XY routing.

The increasing complexity and the short life cycles of embedded systems are pushing the current system-on-chip designs towards a rapid increasing on the number of programmable processing units, while decreasing the gate count for custom logic. Considering this trend, this work proposes a test planning method capable of reusing available processors...

A new core test wrapper design approach is proposed which transports streaming test data, for example scan test patterns, into and out of an embedded core exclusively via (some of) its functional data ports. The latter are typically based on standardised protocols such as AXI, DTL, and OCP. The new wrapper design allows a functional interconnect, s...

This paper presents new DfT modules required to use networks-on-chip as test access mechanism. The paper demonstrates that the proposed DfT modules can be also implemented on top of low cost networks-on-chip, i.e. networks without complex services. The DfT modules, which consist of test wrappers and test pin interfaces, are designed such that both...

An extended fault model and novel strategy to tackle interconnect faults in network-on-chips are proposed. Short faults between distinct channels are considered in a cost-effective test sequence for mesh NoC topologies based on XY routing.

This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. We demonstrate that these interconnects abstract the interconnect details and provide predictability in the data transfer, which are desirable not only for the functional domain but also for the test application. The proposed...

The increasing complexity and the short life cycles of embedded systems are pushing the current system-on-chip designs towards a rapid increase in the number of programmable processing units, while decreasing the gate count for custom logic. Considering this trend, this work proposes a test planning method capable of reusing available processors as...

Network-on-chip has recently emerged as alternative communication architecture for complex system chip and different aspects regarding NoC design have been studied in the literature. However, the test of the NoC itself for manufacturing faults has been marginally tackled. This paper proposes a scalable test strategy for the routers in a NoC, based...

This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores embedded into a system on chip. The resulting test time of the system is evaluated considering the number of reused processors, the number of external interfaces, and pow...

This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores embedded into a system on chip. The resulting test time of the system is evaluated considering the number of reused processors, the number of external interfaces, and pow...

With the advance in hardware integration, system-on-a-chip (SoC) test activities using only automatic test equipments (ATEs) result in an expensive option. Hardware-based test may reduce the ATE dependency. However, hardware-based test imposes some constraints like area overhead and processing speed degradation. The main objective of this work is t...

The goal of this paper is to evaluate the performance of embedded digital systems generated from a system level description language. The target language is SDL, which is automatically synthesized with a codesign tool, resulting in VHDL and C descriptions. The codesign tool is responsible for software, hardware and communication synthesis. Two case...

The goal of this paper is to evaluate the performance of embedded digital systems generated from a system level description language. The target language is SDL, which is automatically synthesized with a codesign tool, resulting in VHDL and C descriptions. The codesign tool is responsible for software, hardware and communication synthesis. Two case...

This paper presents the implementation and evaluation of a hardware and software co-simulation tool. Different simulators, which can be geographically distributed, compose this environment. The communication between simulators is done using a cosimulation backplane. The co-simulation backplane reads a file describing how the modules are connected,...

The goal of this paper is to evaluate the performance of digital systems generated from a high-level description language. The target language in this work is SDL. The SDL description is automatically synthesized with a codesign tool, resulting in a VHDL description. The codesign tool is responsible for software, hardware and communication synthesi...

This paper presents the implementation of a hardware and software co-simulation environment. Different simulators, which can be geographically distributed, compose this environment. The communication between simulators (gcc, ModelSim) is done using Unix sockets, through a router program. The router reads a file containing the communication between...

This paper presents the implementation and evaluation of a hardware and software co-simulation tool. Different simulators, which can be geographically distributed, compose this environment. The communication between simulators is done using a co-simulation backplane. The co-simulation backplane reads a file describing how the modules are connected,...

This paper presents the hardware implementation of a multiplatform control system for house automation using FPGAs. Such a system belongs to a domain usually named domotics or smart house systems. The approach combines hardware and software technologies. The system is controlled through the Internet and the home devices being connected use the CAN...

We present a new approach to estimate the reliability of complex circuits used in harmful radiation environments. This goal can be attained in an early stage of the design process. Usually, this step is performed in laboratory, by means of radiation facilities (particle accelerators). In our case, we estimate the expected tolerance of the complex c...

We present a new approach to design reliable complex circuits with respect to transient faults in memory elements. These circuits are intended to be used in harmful environments like radiation. During the design flow, this methodology is also used to perform an early-estimation of the obtained reliability level. Usually, this reliability estimation...

We present a new approach to design reliable complex circuits with respect to transient faults in memory elements. These circuits are intended to be used in harmful environments like radiation. During the design flow this methodology is also used to perform an early-estimation of the obtained reliability level. Usually, this reliability estimation...

Hardware-based test imposes some constraints like area overhead and processing speed degradation. In addition, with the advance in hardware integration, system-on-a-chip (SoC) test activities using only automatic test equipments (ATEs) results in an expensive option. The main objective of this work is to investigate and evaluate pros and cons of so...

This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. We demonstrate that these interconnects abstract the interconnect details and provide predictability in the data transfer, which are desirable not only for the functional domain but also for the test application. The proposed...

This work presents the implementation of a control system for house applications, belonging to a domain called domotics or smart house systems (1-2). The approach combines hardware and software technologies. The system i s controlled through the Internet, the home devices being connected u sing the c ontrol protocol. Users can remotely control thei...

This paper proposes a flexible and reusable BIST controller for the test of logic IP cores. Such a controller, called ProBIST, provides test programmability and flexibility for the BIST architecture, making it easier the reuse of the IP core and the test structure. The ProBIST processor can be programmed according to the core user's requirements. I...