Alain Bravaix

• PhD, HDR, Senior Member IEEE
• Head of Department at ISEN Yncréa Méditerranée

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This study investigates the commonality Of TDDB under Off-state conditions across a range of CMOS nodes, from 130nm to ultra-scaled devices, i.e. 28nm FDSOI CMOS. To achieve this, Off-mode gate-oxide breakdown is analyzed under non-uniform electric field to investigate the effects of stress-induced leakage current, channel current, and lateral elec...

A single photon avalanche diode (SPAD) cell using N-channel extended-drain metal oxide semiconductor (N-EDMOS) is tested for its hot-carrier damage (HCD) resistance. The stressing gate-voltage (VGS) dependence is compared to hot-hole (HH) injection, positive bias temperature (PBT) instability and off-mode (VGS = 0). The goal was to check an accurat...

Off-state gate-oxide breakdown under non-uniform electric field is performed to investigate the impact of Stress induced leakage current, channel current and lateral electric field in dielectric breakdown mechanism related to RF operations using ultra short channel devices, i.e. 28nm FDSOI MOSFET. Oxide breakdown is characterized under DC stress wi...

The huge improvements in integrated circuits manufacturing has faced great challenges between process optimization, performance requirements and the trade-off between low power operation and reliability for long term use. Both the variability at time zero and the time variability due to external constraints and aging phenomena make mandatory the va...

A detailed analysis of Off-state gate-oxide breakdown (BD) mode and its location under non-uniform electric field is performed in 28nm FDSOI N-MOSFET devices. We show that hard breakdown (HBD) occurs exclusively from the middle of the channel to the drain overlap extension for Off-state TDDB. HBD is characterized under DC stress with different gate...

This book illustrates simply, but with many details, the state of the art of reliability science, exploring clear reliability disciplines and applications through concrete examples from their industries and from real life, based on industrial experiences. Many experts believe that reliability is not only a matter of statistics but is a multidiscipl...

Aging phenomena are first evidenced at device level to cell level considering a precise knowledge of the leading degradation mechanisms and interactions useful for processing optimization focusing performance vs. reliability requirements. Digital to analog circuits are then studied for product qualification based on the former results that needs sp...

We present a detailed analysis of Off-state Time Dependent Dielectric Breakdown (TDDB) under non-uniform field performed in MOSFET devices from 28nm FDSOI, 65nm SOI to 130nm nodes. Oxide breakdown in thin gate oxide is characterized under DC stress with different gate-length LG and as function of drain voltage VDS and temperature. We show that the...

Improving device aging models requires to consider hot-carrier degradation (HCD) between On/Off modes and interaction of these different damage rate mechanisms as well as the dynamic effects. As DC characterization of HCD modes might be insufficient, it is rather necessary to check the quasi-static validity when we seek to model the degradation und...

The study of parameter drift due to interface defect generation in “Off” mode or near V this very complex, because it is often concomitant with hot hole trapping which induces turnaround effects. Improving device aging models requires to consider hot-carrier degradation (HCD) in “On/Off states”, interaction of these different modes as well as any d...

P- and N- channel Extended Drain MOSFETs (EDMOS) are analyzed through its sensitivity to Hot-Carrier (HC) degradation using accelerated lifetime technique. N- and P- channel EDMOS are optimized for a gate-length LG = 0.5 μm, with gate-oxide thickness at 2.3 nm. We have evaluated more precisely the HC damage caused from channel to the extended drain...

In this work, we have demonstrated that many elements are needed on top of conventional foundry reliability knowledge to enable robust automotive products in compliance with all restrictive norms. For intrinsic reliability, both reliability models (a design compatible WLR description), and dynamic aging compensation schemes are required. For extrin...

A novel control loop enables Dynamic Adaptive Voltage Scaling in a demonstrator with digital cores tightly coupled with monitors and Dynamic Controller. Control loop robustness is validated by Markov chains and experimental results. Monitors allow circuits to execute instructions from workloads in fault-free way with power savings up to 50%.

We have developed the possibility of using healing phases on hot-carrier (HC) degraded transistors from devices to logic cells (1) by the combined effects of oxide charge neutralization and channel shortening (2) using back bias VB sensing effects in forward (FBB) mode in 28 nm FDSOI CMOS node. This is done for DC to AC operations from Input-Output...

This paper shows the advantages of using body bias. Experiments are performed in 14 nm and 28 nm UTBB FDSOI transistors and ring oscillators (ROs). The impact of body bias on performance and reliability is highlighted. The body biasing offers significant advantages for adapting the tradeoff between reliability and performance in logic circuits with...

As the operating temperature increases, the tradeoff between performance and reliability becomes tricky as the classical hot-carrier (HC) picture has to be modified into the energy-driven formalism, taking into account the scattering mechanisms and thermal effects in ultrashort channel, which lead to current-driven damage in nanometer-scaled MOSFET...

The development of most applications in the microelectronics industry is driven by an increase in the working frequency. Each product can be used under various types of mission profiles, thus forcing a large variety of signal types on each transistor. One growing concern involves the capability to guarantee the working frequency not only of a fresh...

For advanced CMOS nodes, high performance is reached with the down scaling of both critical gate length and dielectrics stack. The aggressive reduction of dielectric thickness leads to a reduction of reliability margin due to breakdown. However, the first breakdown (BD) event does not always cause a functional failure in digital circuits. Lifetime...

Aging induced degradation mechanisms occurring in digital circuits are of a greater importance in the latest technologies. Monotonic degradation such as Bias Temperature Instability (BTI) or Hot Carrier Injection (HCI) but also sudden degradation such as Dielectric Breakdown (DB) are identified as the major sources of reliability hazard. The impact...

Hot carrier Injection mechanism is an important reliability concern of CMOS devices. While the critical gate dimension length is scaled down, this mechanism of degradation is exacerbated due to the increase of the local electrical field. For different planar and FinFET of N-channel MOS technology nodes, the scalability of this mechanism is presente...

This book provides readers with a variety of tools to address the challenges posed by hot carrier degradation, one of today’s most complicated reliability issues in semiconductor devices. Coverage includes an explanation of carrier transport within devices and book-keeping of how they acquire energy (“become hot”), interaction of an ensemble of col...

A comprehensive study of HC reliability and process change variation for submicron fully depleted Silicon On Insulator (FDSOI) MOSFET’s is presented. The different process variation within the FDSOI technology and their impact on HC degradation are examined (i.e., channel length, source/drain resistance, HTO (oxide thickness Tox)-, LDD). Based on t...

With device scaling, electric fields across the gate oxide have increased and supply voltages have been reduced not as much as the gate-oxide thickness, intensifying the probability of dielectric breakdown events for transistors. In this context, the more the oxide thickness is reduced, the more the oxide breakdown degradation is progressive. Howev...

With technology scaling, highly integrated devices have become increasingly sensitive to the slightest parameter drift. One of the main causes of parameter degradation in recent technologies is the Hot Carrier Injections (HCI), a progressive wear out phenomenon whose understanding and modeling has become mandatory in new CMOS nodes. Therefore, we p...

Based on experimental measurements at bitcell level combined with SPICE and Monte-Carlo simulations, an analytical method is presented to accurately predict fresh/aged Vmin distributions. The impact of BTI variability modeling and real workloads considerations is also deeply analyzed in this paper.

Endurance is investigated on one transistor floating body RAM cells processed on a silicon-on-insulator substrate with ultrathin buried oxide, and programmed using the bipolar junction transistor current inherent in MOSFETs. During the hole generation step, defects are generated close to the drain. These defects not only reduce the retention time b...

This paper presents understandings on BTI variability based upon an extensive dataset. This enables to select between various theoretical statistical models and to propose a novel description approach for the NBTI-induced mismatch for different technological nodes and a comparison with time-zero variability. The impact from transistor to gate level...

we present a multi techno trend of HCI time acceleration and VD power law exponent for various processes. We review the results of defect localization analysis based on a rigorous correlation and interaction study for different HCI degradation and BTI modes. Finally, we check HCI impact on TDDB to get an accurate comprehension about defect nature....

Hot Carrier induced degradation is modeled using the carrier energy distribution function including Carrier-Carrier Scattering process. Silicon-hydrogen bond breaking through single particle and multiple particles interactions is considered in the modeling of the microscopic defect creation along the channel length. The model is applied to short ch...

This paper introduces for the first time a new test structure for electromigration which allows increased statistics and reliability tests in a testchip under typical High Temperature Operating Life experimental ranges. Following the electrical analysis, a large panel of failure analysis methodologies was suitably used to categorize defects such as...

High-K Metal-Gate 28nm node (C28) with equivalent gate-oxide thickness EOT= 1.35nm has been compared to low power 40nm CMOS node (1.7nm) on silicon bulk. Hot-Carrier damage in C28 originates from the same permanent ∆N IT mechanism under current driven Multiple Particle (MP) interactions, relative to the SiON interface layer while border to bulk oxi...

We present new reliability features related to the use of a wide range of bulk back biasing in advanced UTBB FDSOI devices. NBTI and HCI stresses were done addressing degradation dependencies vs. bulk bias with the help of TCAD simulations in order to validate our new proposed NBTI physical model in UTBB FDSOI CMOS node.

Based on capacitive measurements combined with TCAD simulations, in a wide range of bulk biases, the impact of NBTI on both oxide-silicon interfaces of FDSOI transistors is evaluated. Physical modeling is proposed to fully analyze the degradation mechanisms and reproduce the experimental behaviors through the help of accurate simulations of the bac...

Hot Carrier induced degradation is modeled using the carrier energy distribution function including Carrier-Carrier Scattering process. Silicon-hydrogen bond breakage through single particle and multiple particles interactions is considered in the modeling of the microscopic defect creation along the channel. Good agreement with lateral profile mea...

A new methodology of defect characterization, through combination of measurements and simulations, is used to monitor the defect creation rate leading to gate-oxide breakdown. Two defect time-power creation rates were extracted, thus modifying the classical understanding of Weibull slope variation with oxide thickness. Based on our methodology, an...

Based on simulation results, we show that defects at the Si/Box interface of FDSOI transistors can have a detrimental impact on reliability. In particular, attention is paid to Hot Carriers degradations (HC) on ultra thin film FDSOI NMOSFETs for which defects can be created very close to the back gate interface. A new technique based on capacitance...

The persistence of hot-carrier degradation down to low voltages is analyzed in recent CMOS nodes through the effect of multivibration excitation (MVE) of the Si-H bonds and deexcitation by multiphonon emission. This new mechanism is described by an energy framework and originates from the channel current density independently of voltage and geometr...

Up to now, the reliability achieved by COTS components was largely sufficient for avionics, in terms of failure rate as well as time to failure. With the implementation of new and more integrated technologies (90 nm node, 65 nm and below), the question has arisen of the impact of the new technologies on reliability. It has been stated that the life...

This paper presents a theoretical framework about interface states creation rate from Si–H bonds at the Si/SiO2 interface. It includes three mains ways of bond breaking. In the first case, the bond can be broken thanks to the bond ground state rising with an electrical field. In the two others cases, incident carriers will play the main role either...

A new approach of MOSFETs' Breakdown (BD) analysis and modeling is proposed. This work is based on microscopic characterization of defects involved in the BD process. To do so, oxide defects Not (different from interface defects Nit) are profiled through the depth of the oxide using Charge Pumping technique (CP) [1]. Low Frequency Noise (LFN) measu...

Microscopic characterization of interface defects along the channel length is used to monitor the HC induced defect generation. The modeling of HC degradation is adapted to a microscopic scale and is found to be consistent with obtained lateral profiles.

As CMOS technology continues to downscale to a deep submicron level (40 nm and beyond), Soft Oxide Breakdown (SBD) is becoming a real problem that could lead to a serious degradation in the performances and the functional operations of SoC. In this paper we study the SBD, using two models, and quantify its impact on the functionality of a 40 nm SRA...

PBTI in La-doped HfSiON/TiN stacks is investigated using Ultra Fast IV measurements. Excellent PBTI lifetime of these oxides is demonstrated. We also show that PBTI is explained only by trapping in stress induced defects and not by trapping in pre-existing ones. Dependence on oxide field, temperature activation and recovery of PBTI are also investi...

Degradation modeling is based usually on macroscopic parameters which can yield to wrong conclusions, since similar degradation might result from very different microscopic situations. The focus on degradation modeling at a microscopic level is proposed. Other authors only compare results from different characterization methods on their common meas...

A Germanium-on-Insulator (GeOI) wafer was fabricated using low temperature direct wafer bonding method. A hydrogen implanted Ge donor wafer was bonded to a thermally oxided Si handle wafer with in-situ oxygen radical activation before bonding in a vacuum chamber. Ex-situ anneals were use to enhance the bond strength or exfoliate the implanted Ge wa...

Hot-Carrier degradation is analyzed with 3 mode lifetime modeling extended to the cases of PMOSFETs and Off state modes in last CMOS nodes. Damage worsens in subthreshold region with positive temperature activation due to interface traps generation in the gate-drain overlap (GDO) and localized charge trapping into the spacer oxide. Care has been do...

Power law time-to-breakdown voltage acceleration is investigated down to ultra-thin oxides (1.1 nm) in the ESD regime in inversion and accumulation. Breakdown modes, oxide degradation and device drifts under ESD-like stress are discussed as function of the oxide thickness. The consequent impacts on the ESD design window are presented.

A novel method is proposed to extract interface state density Dit at both front and back gate interfaces. This accurate technique based on CV and GV measurements, enables to measure low Dit densities ~1010 traps/cm2/eV, at both interfaces on standard FDSOI transistors. In particular, it was found that DitBG is very low ~3.1010 traps/cm2/eV, and abo...

A large range of commercial deep submicron VLSI devices are used for avionic designs. Due to the scaling down, an ever higher level of integration and the use of new materials in foundries, the main failure mechanisms are changing while new ones appear. Lifetimes related to these failure mechanisms are suspected of being shorter and shorter so fail...

This paper presents a theoretical framework about interface state creation rate from Si–H bonds at the Si / Si O ₂ interface. It includes three main ways of bond breaking. In the first case, the bond can be broken, thanks to the bond ground state rising with an electrical field. In two other cases, incident carriers will play the main ro...

Channel hot-carrier degradation presents a renewed interest in the last NMOS nodes where the device reliability of bulk silicon (core) 40 nm and Input/Output (IO) device is difficult to achieve at high temperature as a function of supply voltage VDD and back bias V_BS. A three mode interface trap generation is proposed based on the energy...

A general framework is proposed to characterize digital library gates for NBTI and HCI ageing effects. Required parameters extraction is demonstrated for practical cases using accurate, state-of-the-art reliability simulation flow. Both NBTI recovery and HCI models are required to accurately assess digital product degradation.

The understanding of the relationship between circuit lifetime and device DC hot carrier (HC) stress lifetime is becoming increasingly important for advanced nodes since supply voltage (Vdd) and channel length (L) do not scale anymore in similar proportions. This paper proposes a novel approach to tackle HC risk assessment through a combination of...

A practical and accurate design-in-reliability methodology has been developed for designs on 90-65-nm technology nodes to quantitatively assess the degradation due to hot carrier and negative bias temperature instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology,...

Power law time-to-breakdown voltage acceleration is investigated down to ultra-thin oxides (1.1 nm) in the ESD regime in inversion and accumulation. Breakdown modes, oxide degradation and device drifts under ESD like stress are discussed as function of the oxide thickness. The consequent impacts on the ESD design window are presented.

Practical and accurate Design-in Reliability methodology has been developed for designs on 90-45nm technology to quantitatively assess the degradation due to Hot Carrier and Negative Bias Temperature Instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology illustrati...

The distinct channel hot-carrier (CHC) degradation mechanisms have been observed in NLDEMOS processed from a SOI CMOS technology. The charge-pumping (CP) technique has evidenced the larger hot-hole efficiency in the damage mechanisms at maximum substrate current condition where a net hole trapping is observed in the overlap region which is further...

In this work, we confirm that the energy is the driving force of Hot Carrier effects. When the energy is high, the Energy-driven framework allows to retrieve Lucky Electron Model-like equations. But when the energy is lowered, high energy electrons generated by Electron-Electron Scattering become the dominant contribution to the degradation. For ev...

This paper presents an improvement of the R-D model explaining analytically the 0.5 exponent observed during HCI stress. An original model based on diffusion equation is proposed where the balance between the hot-hole-induced generation of dangling bonds and the passivation mechanisms via a Multi-Vibrational Hydrogen Release is enlightened. The sec...

In this paper, we propose to distinguish the distinct carrier degradation modes as a function of the energy range developing a complete lifetime extrapolation technique down to the low voltage operation. This provides a starting point of a more accurate modeling of CHC effects during product operations. This work shows that CHC effects in nMOSFET c...

In this paper, we confirm that the energy is the driving force of hot-carrier effects. In high-energy long-channel case, the energy-driven paradigm allows to retrieve lucky electron model-like equations although the explanations are different. When the energy is lowered, high-energy electrons generated by electron-electron scattering become the dom...

This work views NBTI and various conditions of channel hot carrier (CHC) degradation in PMOS and NMOS devices from a unified perspective. This is accomplished by a novel technique using sequential application of stress biases and monitoring the degradation on-the-fly. Thereby, we are able to observe and segregate the distinct mechanisms co-existing...

In this work, we confirm that the energy is the driving force of hot carrier effects. In the high energy-, long channel-case, the LEM picture is still valid. But when the energy is lowered, high energy electrons generated by electron-electron scattering (EES) become the dominant contribution to the degradation. Finally, for even lower energy, the h...