Ajay Kumar Dadoria

Ajay Kumar Dadoria
Maulana Azad National Institute of Technology, Bhopal | MANIT · Department of Electronics and Communication Engineering

Doctor of Philosophy

About

28
Publications
6,646
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99
Citations

Publications

Publications (28)
Preprint
With the quick progress in the area of digital electronics results in miniaturization of semiconductor Industries. In Deep Sub Micron regime, because of leakage current, power consumption is turn out to be a major issue; hence constant efforts are being made by the researchers for investigating the various ways to minimize this. There are various m...
Article
Full-text available
Miniaturization of semiconductor industries paved the way for rapid development in the field of digital electronics. In DSM range, power dissipation has become a major concern due to leakage currents; hence, researchers are continuously trying to evolve ways to mitigate this. Out of many such ways the use of carbon nanotube technology is a promisin...
Article
Full-text available
Power dissipation, propagation delay and noise are major issues in digital circuit design. In this paper, a new leakage-tolerant domino circuit is presented which has lower power consumption and higher noise immunity without significant delay increment for 8 and 16 input OR gates are designed and simulated using existing and proposed techniques in...
Article
This paper describes three novel techniques such as drain gating PMOS transistor (DGPT), drain gating NMOS transistor (DGNT) and drain gating NMOS–PMOS transistor (DGNPT) for mitigation of leakage power, which are proposed to be used for low-power (LP) applications. The proposed techniques have leakage controlling sleep transistor inserted with sle...
Article
Full-text available
This work impacts on the huge potential of FinFET technology, which can replace bulk MOS below 32 nm. Here, two new techniques are introduced to mitigate leakage power as leakage controlling pass transistor P-type LCPT (P) and leakage controlling pass transistor N-type LCPT(N) techniques. Some existing and proposed circuits are simulated in high pe...
Chapter
Leakage power dissipation is the dominant contributor to total power dissipation today in CMOS integration design. Scaling is the prime thrust for development of CMOS circuits, which increases in the number of faults and leakage current in manometer scale in ultra low power circuit design. Here, in this paper we first reviewed the leakage power of...
Article
With the continuous scaling down of technology in the field of integrated circuit design, low power dissipation has become one of the primary focuses of the research. With the increasing demand for low power devices, adiabatic logic gates prove to be an effective solution. This paper briefs on different adiabatic logic families such as ECRL (Effici...
Article
Device scaling demands for a reduction in power supply, high transistor density, lower threshold voltage and reduction in oxide thickness for mitigation of leakage currents. In this paper, two new Drain Gating PMOS Technique (DGPT) and Drain Gating NMOS Technique (DGNT) for mitigation of leakage power are proposed used for low power application. Th...
Article
Aggressive scaling of single gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increases exponentially with reduction of channel length. This paper discusses a Double gate FinFET technology which mitigates leakage current and higher ON state current when scaling is done beyond 32nm. Her...
Article
Scaling of the MOSFET faces greater challenge because of extreme power density due to leakage current in ultra-deep sub-micron (UDSM) technology. To overcome this situation double gate device such as FinFET is used which has excellent control over the thin silicon fins with two electrically coupled gates that mitigate shorter channel effect and exp...
Conference Paper
In this paper we presented a new 13T full adder design based on hybrid --CMOS logic design style. Adders are one of the most basic building blocks in digital components present in the Arithmetic Logic Unit (ALU). The performance of an adder have a significant impact on the overall performance of a digital system. The new design is compared with som...
Chapter
Deep Sub Micron (DSM) technology demands for lower supply voltage, reduced threshold voltage and high transistor density which leads to exponentially increase in leakage power when circuit is in standby mode. Here review of FinFET transistor along with existing low power techniques in DSM circuits like sleep, LECTOR etc. are done. Then Lector with...
Conference Paper
With the continuously growing quest for miniaturization of circuit technology, one of the prime focuses of the research has shifted in the direction of ultra low power circuit designs. Over the years, adiabatic circuit designs have been studied and found to be effective in achieving low power in VLSI circuits. This paper briefs some of the adiabati...
Conference Paper
Full-text available
Deep Sub Micron (DSM) technology demands for lower supply voltage, reduced threshold voltage and high transistor density which leads to exponentially increase in leakage power when circuit is in standby mode. Here review of FinFET transistor along with existing low power techniques in DSM circuits like sleep, LECTOR etc are done. Then Lector with F...
Article
As technology scales down beyond sub 22 nm regime shorter channel effect dominate, single gate MOSFET face great challenge in nanometer while scaling which results in exponential increase in sub-threshold and gate oxide leakage current. To overcome non-planer CMOS device with multi gate technique is adopted to increase the performance and lesser ar...
Conference Paper
Leakage currents are one of the major design concerns in Deep sub-micron (DSM) technology due to rapid integration of semiconductor industries by reducing the transistor size. Many parameter has been reduces with technology scaling such as Threshold voltage, oxide thickness, channel length and supply voltage (Vdd) has been reduced to keep power con...
Conference Paper
In this paper, basically the delay and the noise margin parameter associated in the circuit has been analyzed. The paper gives a better approach for the reduction in delay variation and compares the result with different-different types of domino logic circuits. The other domino logic circuits used to discriminate the result of proposed circuit are...
Article
Full-text available
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over the world today, the battery-powered e...

Questions

Question (1)
Question
Journals are taking advantage of publication but actually, they are dependent on authors, reviewers. In this whole publication process reviewer is a person who directly not getting any benefit from the journal/publication (Even paid journals). I am searching for such journals that do this or provide some other fruitful advantage.
I think there should be some criteria for journals as well that if they charge directly or indirectly then reviewer or other people who are working as a team should also be benefitted either mentioning name as a reviewer on paper or shares.

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