Ahmad Khadem-Zadeh

Sahand University of Technology | SUT · Department of Electrical Engineering

Today, the high accuracy of deep learning has led to use in various domains such as image and voice classification. However, vast computations of deep neural networks (DNNs) have caused the inefficiency of traditional processors, resulting in the emergence of hardware accelerators. DNN accelerators have increased performance by exploiting opportuni...

Deep neural networks (DNNs) have been employed to different devices as a popular machine learning algorithm (ML) owing to deploy the Internet of Things (IoT), data mining in cloud computing, and web search engines, which MLs had an impressive effect on IoT’s edge level nodes. Deploying DNN-based applications leads to memory access problems, includi...

Wireless network-on-chip (WiNoC) has been introduced as an efficient communication paradigm that can provide high bandwidth and low latency wireless links among long-distance cores. However, the increase of demand for using these shared wireless links and the presence of few numbers of these channels on a chip leads to port contention in WiNoCs. Th...

The multi-path transmission is an appropriate transmission method for high data rate packets like video streaming. To provide video streaming with high quality, the video packets are divided into different frames for transmitting through various paths. Nevertheless, regarding the results of numerous inherent features of vehicular ad hoc networks (V...

An input selection strategy is an important part of a router that is done by an arbitration process. When an output channel is requested by two or more input channels simultaneously, the best input channel will be selected by the input selection strategy. This research presents a new input selection strategy called DTIS (Destination Traffic based I...

MapReduce framework is an effective method for big data parallel processing. Enhancing the performance of MapReduce clusters, along with reducing their job execution time, is a fundamental challenge to this approach. In fact, one is faced with two challenges here: how to maximize the execution overlap between jobs and how to create an optimum job s...

The interaction between cores and memory blocks, in multiprocessor chips and smart systems, has always been a concern as it affects network latency, memory capacity, and power consumption. A new 2.5-dimensional architecture has been introduced in which the communication between the processing elements and the memory blocks is provided through a lay...

Today's, a promising solution, namely wireless network‐on‐chip (WiNoC) is utilized in multi‐core systems to overcome the constraints of conventional on‐chip networks. In WiNoC architectures, wireless routers (WRs) provide high capacity wireless links to reduce the latency of multi‐hop communications. However, the buffer size of the WR antenna is li...

Wireless network on chip (WiNoC) has been proposed as a promising solution for on-chip interconnection network due to high scalability, high bandwidth, and low latency. However, the variations of traffic pattern distribution and data flow in WiNoCs have made wireless interfaces-equipped routers (WRs) prone to congestion. Congestion is one of the mo...

A multi-processor architecture was proposed to address power consumption limitations in chips in order to increase performance and lower power consumption. In this architecture, the highest power consumption comes from the chip connections. Optical connections can reduce power consumption and increase performance via a new architecture called Photo...

In 2.5D stacking technology, multiple chips have stacked side‐by‐side on a silicon interposer layer. The network‐on‐chip in the central processing unit (CPU) layer makes it possible to connect processing cores to each other. The interposer layer prepares the connection between the CPU cores and other chips such as memory chip. The memory chip usual...

Due to the advent of new technologies, devices, and communication tools such as social networking sites, the amount of data produced by mankind is growing rapidly every year. Big data is a collection of large datasets that cannot be processed using traditional computing techniques. MapReduce has been introduced to solve large-data computational pro...

An important challenge in radio frequency identification (RFID) systems is the collision concern. When an interrogator send a request, it has several tags to answer to in its transmission range, and a tag collision has occurred. The interrogator must be able to recognize tags as rapidly as possible. A collision problem is a power‐consuming occurren...

Stacking technology is an approach to improve scalability of 2D network-on-chip systems. 3D stacking technology places multiple chips vertically, while silicon chips are stacked side-by-side on a silicon interposer layer in the 2.5D stacking technology. 2.5D stacking can solve many of the 3D stacking difficulties such as thermal problem. The cores...

The Micro Packet Switched based Network on Chip (NoC) is emerged to address traditional non-scalable buses-based Systems on Chip (SoC) challenges such as out of order transactions, flow control and higher latencies. The NoC is disposable to a different of defects in its life which cause of such drawbacks as data missing, efficiency reduction, and e...

The Micro Packet Switched based Network on Chip (NoC) is emerged to address traditional non-scalable buses-based Systems on Chip (SoC) challenges such as out of order transactions, flow control and higher latencies. The NoC is disposable to a different of defects in its life which cause of such drawbacks as data missing, efficiency reduction, and e...

Selection strategy is an essential part of an adaptive routing algorithm that influences the performance of the networks-on-chip (NoC). A selection strategy is used for selecting the best output channel from the available channels according to the network status. This study presents a new output selection strategy called destination intensity and c...

Multiple memory stacks can be integrated with a processor chip in the silicon interposer technology (“2.5D” stacking). In 2.5D architecture, there are two different network layers for both coherence and memory traffic. The CPU layer is used for coherence Core-to-Core traffic, while the interposer layer is associated with Core-to-Memory blocks traff...

Cloud computing has expanded considerably in industry and research and is based on a pay-as-you-go payment model. In cloud computing environment, on one hand, jobs sent to the cloud to execution have a variety of attribute such as deadline, length, bandwidth requirements. On the other hand, various virtual machines have been created at different co...

Radio‐frequency identification (RFID) is a wireless communication technology. Radio frequencies can cause interference in a dense RFID system, thus decreasing efficiency. In recent years, many protocols have been proposed to reduce reader collisions based on multiple‐access techniques. The main weakness of Time Division Multiple Access (TDMA)‐based...

Unfortunately, the affiliation details of the authors have been published incorrectly. The correct details are given below.

In this paper, the influence of the mapping algorithm on the physical layer parameters and photonic network-on-chip performance is demonstrated. Four mapping algorithms, namely hop count, congestion, no-turn, and turn, have been suggested. The proposed mapping algorithms illustrate the impact of hop count, congestion, moving in the direct and indir...

In mobile ad hoc networks, clustering refers to the process of identifying the set of clusterheads that optimize one or more network objectives. To optimize each objective, the nodes of the network should be evaluated and compared in terms of one or more corresponding attributes. In many-objective problems, as the number of favorable network object...

In the current paper, we propose a new online search, fault detection, and fault location approach for short faults in network on chip communication channels. The approach proposed consists of a built-in self-test as well as a packet/flit comparings module embedded in the network adapter and a router, respectively. The approach is mainly characteri...

In mobile ad hoc networks, clustering refers to the process of identifying the set of clusterheads that optimize one or more network objectives. To optimize each objective, the nodes of the network should be evaluated and compared in terms of one or more corresponding attributes. In many-objective problems, as the number of favorable network object...

Photonic Network-on-Chips is a new generation of Network-on-Chips and has been proposed as a novel solution for the communication infrastructure of chip multiprocessors as well as a different solution to eliminate limitations of Network-on-Chips. Photonic Network-on-Chips has important properties such as increasing communication bandwidth, lowering...

In this paper, a new BIST based test approach to detecting short faults on the communication channels data links in network-on-chip is proposed. The rationale underlying the novelty of the proposed approach is that it is capable of locating the faulty channels while simultaneously performing the testing as well as updating the Routing Tables (RT) i...

As an excellent interconnection model, Network on chip (NoC) addresses different on-chip communication problems and can meet different requirements of performance, cost and reliability. Currently, with the growth of technology practice, wire-based interconnections are more and more unreliable. Consequently, growing sources of unreliability directly...

In this paper, several efficient migration algorithms have been proposed to improve existing non-preemptive sub-mesh allocation strategies in multiprocessors which are two-row boundary migration algorithm (TRBMA) and different types of combined migration mechanisms. These methods are presented to solve the external fragmentation problem in contiguo...

In this paper, we consider the problem of processor allocation on mesh-based multiprocessor systems. Also, we employ the idea of selecting appropriate size of sub-mesh to decrease delay and increase continuity. Indeed, processor migration is utilized in these systems to minimize fragmentation and the overall processing time of the tasks. To this en...

The Quality of Service (QoS) routing protocol plays a vital role in enabling a mobile network to interconnect wired networks with the QoS support. It has become quite a challenge in mobile networks, like mobile ad-hoc networks, to identify a path that fulfils the QoS requirements, regarding their topology and applications. The QoS routing feature c...

This paper presents a novel and efficient mapping algorithm based on machine learning methods. It produces the best mappings with different metrics which were totally evaluated by support vector machine (SVM), decision tree classifier (DTC), and multiple clustering. It helps to find the optimal application-specific network-on-chip (NoC) based on us...

The demand for robust computation systems has led to the increment of the number of processing cores in current chips. As the number of processing cores increases, current electrical communication means can introduce serious challenges in system performance due to the restrictions in power consumption and communication bandwidth. Contemporary progr...

Network-on-chip (NoC) performance largely depends on the underlying deadlock-free and efficient routing algorithm. The effectiveness of any adaptive routing algorithm strongly depends on the underlying selection strategy. When the routing function returns a set of admissible output channels with cardinality greater than one, a selection function is...

In this paper, we propose a novel mapping algorithm for providing Quality of Service (QoS) under bandwidth constraints in 3D Network-on-Chip (NoC). The QoS is warranted in such a way that all minimum feasible paths considering the required and available bandwidth are explored by the mapping algorithm. The maximum required bandwidth on the network l...

Support Vector Machine (SVM) is one of the classification methods in machine learning. It shows excellent performance in many pattern recognition applications. SVM map an input sample into a high dimensional feature space and try to find an optimal hyperplane. Although it has some challenges that one of them is non linear models, but a model can be...

As the integration of transistors on today’s embedded systems scales, so does the shrinking size of chips, thus making the on-chip communication a challenging issue on the VLSI designs. However, network on chips have emerged as a promising technology to tackle the on-chip communication constraints. Likewise, the reliability issues have become the s...

NoC performance largely depends on the underlying deadlock-free and efficient routing algorithm. Selection strategies play a pivotal role in the effectiveness of the routing algorithm by selecting the final output channel when there is more than one possible output link returned by an adaptive routing. In this paper a novel selection strategy, L...

In this paper, we introduce a new protocol, named TDFCA (Trusted Data Fusion by using Cellular Automata) in Wireless sensor Networks. TDFCA uses Cellular Automata rules to find the most suitable cluster head, perform data fusion, and find the most trusted neighbors for sending the fusion result to base station. The network is intended for the long-...

The performance of network-on-chip (NOC) largely depends on the underlying routing techniques. A routing technique has two constituencies: output selection and input selection. This paper focuses on the improvement of input selection part. Two traditional input selections have been used in NOC, first-come-first-served (FCFS) input selection and Rou...

Network-on-Chip(NoC) has been proposed as a solution to provide better modularity, scalability, reliability and higher bandwidth compared to bus-based communication infrastructures. The performance of Network-on-Chip largely depends on the underlying routing techniques. A routing technique has two constituencies: output selection and input selectio...

The performance of Network-On-Chip(NOC) largely depends on the underlying routing techniques. A routing technique has two constituencies: output selection and input selection. This paper focuses on the improvement of input selection part. Two traditional input selections have been used in NOC, First-Come-First-Served (FCFS) input selection and Roun...

Network on Chip (NoC) has been proposed as a new paradigm for designing System on Chip (SoC) which supports high degree of scalability and reusability. One of the most important issues in an NoC design is how to map an application on NoC-based architecture in order to satisfy the performance and cost requirements. In this paper a novel procedure is...

Vehicular ad hoc networks (VANETs) are appropriate networks that can be used in intelligent transportation systems. Among challenges in VANET, scalability is a critical issue for a network designer. Clustering is one solution for the scalability problem and is vital for efficient resource consumption and load balancing in large scale networks. As o...

The performance of Network-on-Chip (NoC) largely depends on the underlying routing techniques. In this paper we present and evaluate a fault and congestion aware routing scheme called FADyAD which combines the advantages of both deterministic and adaptive routing schemes. On the other hand, the routers switching between deterministic and adaptive r...

In this paper, a novel procedure is introduced to find an optimal application-specific Network on Chip, considering communication cost and fault-tolerant requirements. The procedure, which is called Ruby, uses a genetic algorithm and a mapping solution to generate a wide range of mappings. A designer can select the optimal mapping from those genera...

This paper presents a new topology for network-on-chip (NoC) called “Sorena”. The proposed topology is made by merging of 4-node basic models and then connecting edge nodes. Using a change in coordinate system of nodes, a simple, fast and deadlock-free routing algorithm has been suggested. Compared to 2D Mesh which is the most common topology in on...

In this paper a fast and efficient spare switch selection algorithm is presented in a reliable NoC architecture based on specific application mapped onto mesh topology called FERNA. Based on ring concept used in FERNA, this algorithm achieves best results equivalent to exhaustive algorithm with much less run time improving two parameters. Inputs of...

Nowadays, with technology shrinking and the huge demand for supporting multiple applications has led designers to use multiple IP cores within a single chip. Therefore, the designers have proposed Networks-on-chip to overcome the problems of future complex systems. Mapping IPs directly affects NoC design parameters such as latency and power consump...

The Residue Number System (RNS) is an unconventional system. This system is a useful tool for Digital Signal Processing (DSP) since it can support parallel, carry-free, high-speed, low power and secure arithmetic. One of the most important things we should consider for RNS is the choice of the moduli set. It should cover the system’s speed, its dyn...

System on Chip is a system consists of a number of intellectual property cores (IP cores) which are connected together utilizing electrical bus technology. When the number of IP cores increases, Network on Chip (NoC) architectures with regular topology instead of traditional bus based architecture are used. Mapping of IP cores on a given architectu...

In this paper, a heuristic mapping algorithm which maps tasks, using priority lists and the crinkle moving pattern is proposed. To evaluate this algorithm, a set of real (i.e. Video Object Plan Decoder) and random applications have been used and the results have been compared. By reducing the number of hops between IP cores, the energy consumption...

Mapping of IP cores on a given platform is one of the three aspects of Network-on-Chip design. Mapping priority of IP cores is mostly based on a single communication in previously proposed algorithms. In this paper we present Chain-Mapping (CHMAP), as an algorithm for mapping cores onto a mesh-based Network-on-Chip architecture. The main aim of the...

Networks on chip (NoCs) are communication infrastructures that offer parallelism and scalability. In this paper we present high performance dynamically allocated multi-queue (DAMQ) buffer schemes for fault tolerance systems on chip applications that require an interconnection network. Two virtual channels shared the same buffer space. Fault toleran...

Network on Chip is emerging as a solution to the existing interconnection architecture constraints. Performance parameters like latency, throughput are critical issues in interconnection network design. Routing algorithms have a prominent impact on communication and performance in on chip interconnection networks. This paper presents a new dynamic...

To find a way to access a path to provide quality of service (QoS) requirements, we can use the constraint-based routing technique. Until now algorithms uses an additive constraint along with a bandwidth constraint (e.g. delay or hop count) have been used. It was for the requirement of QoS. Selecting the path is used not only for the guaranty QoS,...

Dynamic and efficient routing is one of the key challenges in wireless ad hoc networks. In this paper, based on a reactive AODV protocol, a novel semi-proactive routing protocol, named SP-AODV, is presented that uses proactive routing for some special nodes. The efficiency of the new protocol lies in the fact that some nodes with certain conditions...

Topology Control and energy saving is one of the most important challenges in wireless sensor networks because of Special characteristics of these networks such as limited transmission range, low bandwidth, limited power resource and the impossibility of recharging. In this paper, k-fault tolerant clustering topology control algorithm is presented....

NoC is a potent solution to address design complexity and productivity problems whose its key component is the interconnect architecture which directly affects both cost and performance parameters. The purpose of this paper is to present the basic ideas behind the development of our new hierarchical network-on-chip (NoC) architecture, called ldquoN...

As technology scales, fault tolerance is becoming a key concern in on-chip communication. In this paper we present a methodology to design fault-tolerant routing algorithms for regular direct interconnection networks. It supports fully adaptive routing, does not degrade performance in the absence of faults, and supports a reasonably large number of...

Due to the ever-increasing complexity of System on Chip (SoC) design, and non-efficiency of electric bus to exchange data between IP cores in Giga scale, the Network on Chip (NoC) is presented with more flexible, scalable and reliable infra-structure. As mapping of IP cores on a given platform is one of three aspects of NoC design, with the focus o...

The NoC paradigm is one, if not only one, fit to enable the integration of an exceedingly large number of computational, logical and storage blocks in a single chip. The paper presents a novel technique called CGMAP,which finds a mapping of the vertices of a task graph to the tiles of a mesh based NoCarchitecture, with an objective of improving the...

This method decrease usage power (expenditure) in networks on chips (NOC). This method data coding for data transferring in order to reduces expenditure. This method uses data compression reduces the size. Expenditure calculation in NOC occurs inside of NOC based on grown models and transitive activities in entry ports. The goal of simulating is to...

Directed diffusion is a data-centric routing protocol used in wireless sensor networks and uses only local interaction between neighbor nodes. One of the problems of this approach is the mechanism used for routing selection which mostly, leads to select the shortest path between sinks and sources. In this case the nodes in the shortest path will fa...

In this paper we present the basic ideas behind the development of our novel ring based network-on-chip (NoC) architecture, called ldquoCoronardquo. To achieve minimum hop count, shortest path routing has been applied. Consequently, this ends in average latency reduction (averagely 45%). NS-2 tool is utilized to estimate average latency and packet...

One of the most important challenges in mobile ad hoc networks is to use an efficient and dynamic routing protocol, as the nodes can move randomly, which requires the routing protocol to respond quickly to the network topology change. In this paper, a new hybrid routing protocol, based on a reactive AODV routing, is introduced. It follows the proac...

In this paper we present a methodology to design fault-tolerant routing algorithms for two-dimensional mesh networks. Our methodology, Dynamic intermediate node algorithm (DINA) supports fully adaptive routing, does not degrade performance in the absence of faults, and supports a reasonably large number of faults without significantly degrading per...

In this paper, a heuristic Dynamic Spiral Mapping (DSM) algorithm for 2-D mesh topologies is proposed. Based on the DSM we have presented two different approaches: the Full Dynamic Spiral Mapping (FDSM) and the Partial Dynamic Spiral Mapping (PDSM). To compare the efficacy of the algorithm, the reconfiguration time of the FDSM and PDSM are compared...

The authors in (B. Arslan and A. Orailuglu, 2004) propose circular-scan chain architecture to reduce test time and cost in SOCs. The technique presented in this paper is based on circular-scan architecture (B. Arslan and A. Orailuglu, 2004). The basic idea of circular-scan architecture is use of the captured response of the previously applied patte...

This paper presents a Backtracking adaptive routing algorithm for NoC which enhances the reliability of routing. As the number of transactions (in a task graph) exceeds a certain level. The Backtracking routing algorithm presents better performance results & less non-established paths (no-paths). Comparing the West First, West First with Backtracki...

Residue Number System (RNS) is an integer and non weighted number system that is useful tool for Digital Signal Processing (DSP) since it can support parallel, carry-free, high-speed and low power arithmetic. Redundant Residue Number System is an extension of RNS which also supports error detection and correction. The Multi-Level Residue Number Sys...

In the literatures application mapping and task routing has been address as one of the recent open problems in network on chip design[1]. The well performing of these procedures will directly affect the performance and cost measures of NoC design. Some of these measures which we have considered are the total energy consumption, the algorithm comple...

In this paper, a heuristic core mapping algorithm for 2- D mesh topologies called Spiral is proposed. To compare the efficacy of the algorithm, the results of the proposed algorithm are compared with those of the genetic and random mapping algorithms. The experimental results of synthetic traffic profiles reveal that the Spiral algorithm improves t...