Abhijit R. Asati

Birla Institute of Technology and Science Pilani | BITS Pilani · Electrical and Electronics Engineering Program

Recently, with the increase in the precision of convolutional neural networks (CNN) on a wide variety of classification and recognition tasks, the demand for their deployment has dramatically increased. Even the focus is on lightweight, faster, and low-power implementations. In this paper, we have implemented a CNN model onto an embedded platform,...

A convenient way to estimate and optimize the delay of VLSI digital circuits is the popular logical effort-based optimization. In this paper, we analyzed the effect of various circuit parameters such as logical effort (G), branching effort (B), electrical effort (H), and parasitic effort (P) on the delay of a given circuit for two different technol...

In modern VLSI design, the focus is shifting toward low-power VLSI design techniques to reduce the power density on the chip. Adiabatic logic is suitable in design of low-power VLSI circuits. In this work, we focus on design and analysis of digital code converters. The code converters designed in this work are, namely, gray to binary, binary to gra...

The convolutional neural network (CNN) models have proved to be very advantageous in computer vision and image processing applications. Recently, due to the increased accuracy of the CNNs on an extensive variety of classification and recognition tasks, the demand for real-time hardware implementations has dramatically increased. They involve intens...

This paper proposes an area, speed and power-optimized band-pass digital signal processing filter targeted for Kintex-7 Field Programmable Gate Array device. The filter was designed using MATLAB and Simulink and code generated using HDL Coder from MathWorks. The implementation was created using a novel high-level synthesis design method, which redu...

Connected smart vehicles in automotive industries have increased, resulting in high vehicle-to-vehicle, vehicle-to-infrastructure, and vehicle-to-cloud connectivity. Increased data rates are required to achieve high bandwidth requirements to support such communication networks. Despite having numerous advantages, high connectivity between devices p...

In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in softwar...

Dynamic voltage and frequency scaling (DVFS) is useful for low power digital circuit design. The work proposes a novel DVFS module offering any finer clock frequency change to produce an appropriate supply voltage to feed a digital circuit driven by DVFS module. In DVFS with varying supply and clock conditions the chances of setup and hold timing v...

Harris corner detection is an algorithm frequently used in image processing and computer vision applications to detect corners in an input image. In most modern applications of image processing, there is a need for real time implementation of algorithms such as Harris corner detection in hardware systems such as field-programmable gate arrays (FPGA...

This study presents dedicated hardware for iris localization that can be used as a coprocessor in the development of real-time and low-cost embedded iris biometric systems. Though the hardware architecture is described for iris localization in the visible wavelength (VW) images, the concept used can be applied to near infrared (NIR) images as well....

The last two decades have seen a revolution in telecom technology with the evolution of three wireless mobile communication standards, namely, GPRS to 3G, 3G to 4G, and 4G to 5G. 5G offers faster download speeds and enables high connectivity between devices such as mobile phones, displays, smart homes, and smart cars because of its high reliability...

In radar-based advanced driver assistance systems, baseband processing is necessary to detect the speed, distance, and angle of elevation of the target (e.g., vehicle, pedestrian, traffic sign, etc.). The target and the source often move at high speeds; therefore, the computation rate must be sufficiently high to perform actions (e.g., braking) in...

Sobel edge detector is an algorithm commonly used in image processing and computer vision to extract edges from input images using derivative of image pixels in x and y directions against surrounding pixels. Most artificial intelligence and machine learning applications require image processing algorithms running in real time on hardware systems li...

Carbon nanotube Field Effect Transistors (CNTFET) offer various benefits as compared to other FETs. Many circuits can be constructed using PCNTFETs (P-type CNTFET) and NCNTFETs (N-type CNTFET) similar to the PMOS and NMOS of the CMOS technology. The CNTFETs employ carbon nanotubes in the channel of the device to provide a path for the ballistic con...

This study presents a circle Hough transform (CHT) architecture that provides memory reduction between 74 and 93% without and with little degradation in the accuracy, respectively. For an image of P × Q pixels, the standard (direct) CHT requires a two-dimensional (2D) accumulator array of P × Q cells, but the proposed CHT uses a 2D accumulator arra...

This paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transform (CHT) based algorithm to localize irises in the images c...

In scaled technologies with lower supply voltage, conventional Static Random Access Memory (SRAM) cell suffers from unsuccessful read & write operation due to high off state current in sub-threshold region at nanometre technologies. This work proposes new functional low-power designs of SRAM cells with 7, 8, 9 and 12 transistors which operate at on...

This study presents hardware implementation of 5 × 5 median filter that uses a new low-latency median filter (LLMF) core in order to find the median of 25 integer values. The proposed LLMF core architecture computes the median of 25 integers in just three clock cycles. The maximum frequency of operation of the proposed median filter architecture is...

This paper proposes an edge-map generation technique for pupil detection in near infrared (NIR) images and its hardware implementation. The proposed edge-map generation technique is based on generating two different edge-maps of same eye image using Gaussian filtering, image binarization and Sobel edge detection operations and then combining them t...

This paper proposes an accurate iris localization algorithm for the iris images acquired under near infrared (NIR) illuminations and having noise due to eyelids, eyelashes, lighting reflections, non-uniform illumination, eyeglasses and eyebrow hair etc. The two main contributions in the paper are an edge map generation technique for pupil boundary...

Logarithm and exponential functions are frequently used in signal processing, communication and information theory. They are primarily used for hardware calculations, handling multiplications, divisions, powers, and roots effectively. This paper presents a ROM based approach for the evaluation of base-2 logarithm and exponential at single precision...

This paper proposes an accurate iris localization algorithm for the iris images acquired under near infrared (NIR) illuminations and having noise due to eyelids, eyelashes, lighting reflections, non-uniform illumination, eyeglasses and eyebrow hair etc. The two main contributions in the paper are an edge map generation technique for pupil boundary...

Validation of the robustness, efficiency of allocation and scheduling heuristics in large scale parallel and distributed systems is usually done using synthetic randomly generated workloads, represented by task graphs. Randomly generated graph are required for verification of algorithms in multidisciplinary streams. This requires that the number of...

The paper presents a variability-aware modified 9T SRAM cell. In comparison to 6T SRAM cell the proposed cell achieves 1.3× higher read-SNM and 1.77× higher write-SNM with 79.6% SINM (static current noise margin) distribution at the expense of 14.7× lower WTI (write trip current) at 0.4 V power supply voltage, while maintaining similar stability in...

The paper presents a variability-aware modified 9T SRAM cell. In comparison to 6T SRAM cell the proposed cell achieves 1.3× higher read-SNM and 1.77× higher write-SNM with 79.6% SINM (static current noise margin) distribution at the expense of 14.7× lower WTI (write trip current) at 0.4 V power supply voltage, while maintaining similar stability in...

Iris segmentation in the iris recognition systems is a challenging task under noncooperative environments. The iris segmentation is a process of detecting the pupil, iris’s outer boundary, and eyelids in the iris image. In this paper, we propose a pupil localization method for locating the pupils in the non-close-up and frontal-view iris images tha...

Rapid increases in chip complexity, increasingly faster clocks and proliferation of portable devices have combined to make power dissipation an important design parameter. In battery operated digital devices the demand of low power consumption and low energy dissipation in order to maximise battery life are the matter-of-course. Typical energy opti...

In this chapter, the design and comparative analysis is done in between the most well-known column compression multipliers by Wallace and Dadda in sub-threshold regime. In order to reduce the hardware which ultimately reduces area, power and overall power delay product, an energy efficient basic modules of the multipliers like AND gates, half adder...

This paper involves the design and comparative analysis of Han-Carlson and Kogge-Stone adders in sub-threshold regime using three different hybrid logic families. The performance metrics considered for the analysis of the adders are: power, delay and PDP. Simulation studies are carried out for 8, 16, 32 and 64 bit input data width. The proposed cir...

The paper presents a novel 8T SRAM cell with access pass gates replaced with modified PMOS pass transistor logic. In comparison to 6T SRAM cell, the proposed cell achieves 3.5x higher read SNM and 2.4x higher write SNM with 16.6% improved SINM (static current noise margin) distribution at the expense of 7x lower WTI (write trip current) at 0.4 V po...

Iris localization is an important step for high accuracy iris recognition systems and it becomes difficult for iris images captured in unconstrained environments. The proposed method localizes irises in unconstrained infrared iris images having non-ideal issues such as severe reflections, eyeglasses, low contrast, low illumination and occlusions by...

The computing efficiency of modern column compression multipliers offers a highly efficient solution to the binary multiplication problem and is well suited for VLSI implementations. The various analyses are established more on compressors circuits particularly with Multiplexer (MUX) design. Conventionally, compressors are anatomized into XOR gate...

The paper presents the analysis and implementation of ultra low-power, low voltage and low area 4-bit carry look ahead adder circuits. Sub-threshold design technique has been used to reduce the power consumption and area while maintaining low complexity of logic design in the proposed circuit. Simulation results illustrate the superiority of the ci...

Designing of low power circuits is one of the most important research topic currently. Specially, for Medical Implant devices which run on non-rechargeable batteries power consumption becomes the most important issue as these batteries are very expensive. Majority of the human body signals are of low frequency which makes power consumption more imp...

Widespread internet usage has led to data protection and accurate verification of personnel, resulting in extensive use of biometrics. In the proposed work, we have discussed Daugman's algorithm, a commercially prevalent iris biometric system. The main aim is to compute false accept rate (FAR) and false reject rate (FRR) for any standard iris datab...

Partitioning and scheduling of dataflow graphs(DFGs) has been a matter of extensive research for ASIC based development. With the advent of partial reconfigurable hardware the need to schedule DFGs with restricted resources is required. In this research we test and extend the conventional scheduling algorithm suited for reconfiguration. In algorith...

In this paper the structural pattern required to create a generic HDL code for a fast Baugh Wooley multiplier has been described. The ripple carry adder in the final stage of the conventional Baugh Wooley multiplier was replaced by a Linear Carry Select Adder, resulting in a modified Baugh Wooley architecture. The post-synthesis results of the mult...

I-V characteristic is one of the important results produced by a device simulator. In this article, a novel and interactive matrix based algorithm is presented to draw the device structure in 2-D or 3-D style and to plot the I-V characteristic of the device for user specified doping and biasing conditions. Algorithm creates 2-D or 3-D matrix of the...

The digital system design process can be accelerated by concurrent design of hardware and software. This process requires the migration of functions that are computational extensive to hardware. This paper presents a framework for identifying such functions by proposing an algorithm. The framework uses the time profiling and clustering technique to...

Energy band diagram is one of the important results produced by a device simulator. In order to provide more flexibility and emphasis over this domain, an algorithm is presented which can be used to draw the device band diagram in any plane in either direction for a user specified biasing conditions. Algorithm uses a three dimensional matrix of the...

Barrel shifter is one of the important data path elements and widely used in many key computer operations from address decoding to computer arithmetic, using basic operations like data shifting and rotation. In this paper MUX based barrel shifter circuits are designed and implemented in 0.6μm, N-well CMOS process using three different logic design...

Redundant binary number appears to be appropriate for high-speed arithmetic operation, but the delay and hardware cost associated with the conversion from redundant binary (RB) to natural binary (NB) number is still a challenging task. In the present investigation a simple approach has been adopted to achieve high speed with lesser hardware and pow...

Most of the time, power supplies fail to provide a constant voltage supply and some external voltage signal may override on the power supply giving unwanted fluctuation at the output node. This paper discusses 3 techniques to improve the Power Supply Rejection Ratio (PSRR) in amplifier circuits. 1) Cascoding technique – Cascoding increases the gain...

This paper presents a novel fixed-point 16-bit word-width 16-point FFT/IFFT processor architecture designed primarily for the signal and image processing application. The 16-point FFT is realised by using Cooley-Tukey decimation in time algorithm. This approach reduces the number of required complex multiplications compared to a normal discrete Fou...

Array multipliers are preferred for smaller operand sizes due to their simpler VLSI implementation, in-spite of their linear time complexity. The tree multipliers have time complexity of O (log n) but are less suitable for VLSI implementation since, being less regular, they require larger total routing length, which may degrade their performance. S...

The Array multipliers are generally preferred for smaller operand sizes due to their simpler VLSI implementations, in-spite of their linear time complexity. The tree multipliers have time complexity of O (log n) but are unsuitable for VLSI implementation since they require larger total routing length, which may degrade performance. The properties o...

The PMOS/NMOS width ratio (�?) and W/L ratio of NMOS device is an important ratio in the design of digital logic cells using conventional CMOS logic design style. In this paper we propose a simulation-based method applied to CMOS inverter to accurately estimate an optimum W/L ratio of NMOS device and PMOS/NMOS width ratio when fanout loading of 1,...

A high-speed radix-64 parallel multiplier using novel reduced delay partial product generator is proposed. The use of radix-64 Booth encoder and selector for partial product generation by Sang-Hoon (Sang-Hoon Lee et al., 2002) reduces the number of partial product rows by six fold. The Booth selector selects one among X, 2X, 3X, 4X, 8X, 16X, 24X an...

The high-speed dynamic True Single Phase Clock (TSPC) logic design style offer fully pipelined logic circuits using only one clock signal, which makes clock distribution simple and compact. The conversion of simple logic gates to pipelined TSPC logic gates increases transistor count since standard cell implementation for a logic function uses both...