Abdoul Rjoub

Jordan University of Science and Technology | Just · Department of Computer Engineering

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In addition to its monotonous nature and excessive time requirements, the manual school timetable scheduling often leads to more than one class being assigned to the same instructor, or more than one instructor being assigned to the same classroom during the same slot time, or even leads to exercise in intentional partialities in favor of a particu...

This paper underlines a closed form of MOSFET transistor's leakage current mechanisms in the sub 100nmparadigm.The incorporation of drain induced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (Isub) was investigated in detail. The Band-To-Band Tunneling (IBTBT) due to the source and Dra...

А. Lead is a widely spread environmental pollutant and its concentration is dramatically increasing in our ecosystems. Jordan is facing this signifi cant problem because of the dramatic increase in population size, especially due to the crisis of Syrian refugees. In this study, nine barleys (Hordeum vulgare L.) genotypes (two cultivars and seven la...

In this paper, a Carbon Nanotube Field Effect Transistor gate to channel capacitance Gaussian distribution model is proposed. The proposed model is based on assumption of random placement of CNTs within the channel region, in lieu of the traditional uniform distribution exhibited in the literature. The proposed model is inspired from the fact that...

The demand for high performance, low power/secured handheld equipment increased the need for high speed/low energy and e±cient encryption/decryption algorithms. Recently, e±cient techniques were suggested to increase the standard of security as well as the speed of portable and handheld devices. Also, those techniques cause increment in the lifetim...

A new simulation model based on artificial intelligence techniques optimises the width of transistor at nanoscale level in order to reduce the power delay product is presented in this paper. The proposed model is composed from three models: graph model (GM), mathematical model (MM) and heuristic model (HM). These models cooperate together homogeneo...

This paper presents two approaches targeting the reduction of power dissipation, the delay time and silicon area of S7 and S9 blocks of MISTY1 encryption algorithm. The essential part of both approaches is to reduce the number of logic gates (XOR and AND gates) used in S7 and S9 blocks ciphers. The first approach reduces the number of logic gates b...

In this paper, a simulation study of Carbon Nano Tube Field Effect Transistor inverter performance is presented using the Southampton model. Evaluation of results from this study was made in terms of propagation delay time and total power consumed by the circuit. Tradeoff between these factors has led to the use of power delay product as a good ind...

This paper presents an efficient algorithm to control and reduce the sub-threshold leakage current at nanoscale transistor level. The proposed algorithm called fast input vector algorithm (FIVA) is based on input vector control (IVC) technique. Simulation results showed that the proposed algorithm is faster than other algorithms implemented using t...

this paper proposes a new approach for designing the output waveform nanoscale CMOS inverter using the unit step input. The output waveform is obtained by solving the corresponding differential equations of the circuit. Various phenomena due to Short Channel Effects are included in the equation to achieve more accurate model. Based on this model, t...

Simple and accurate models for Gate leakage current (I g) in nanoscale Metal Oxide Semiconductor Field Effect Transistor (MOSFET) are proposed in this paper. The accurate modeling for Oxide Electric field (ox E) and Oxide voltage (V ox) due to Short Channel Effect (SCE) between the gate and inverted channel is the key for higher accuracy. The Oxide...

Simple and accurate models for Gate leakage current (Ig) in nanoscale Metal Oxide Semiconductor Field Effect Transistor (MOSFET) are proposed in this paper. The accurate modeling for Oxide Electric field (E ox) and Oxide voltage (Vox) due to Short Channel Effect (SCE) between the gate and inverted channel is the key for higher accuracy. The Oxide P...

This paper provides an extension to the earlier work wherein a comparison between different models that had studied the effects of several parameters scaling on the performance of carbon nano tube field-effect transistors was presented. The evaluation for the studied models, with regard to the scaling effects, was to determine those which best refl...

In this paper, an accurate new model for drain induced barrier lowering (DIBL) tunneling in silicon on insulator (SOl) metal oxide semiconductor field effect transistor (MOSFET) is proposed. The effect of drain (Vd,) and substrate (Vb,) voltages variation on DIBL is discussed. The dependency of channel length variation (M), junction depth (rj), and...

In this paper, a new accurate and low delay leakage current (h) model for complementary metal oxide semiconductor (CMOS) inverter is presented. During the overshooting period, the input-to-output coupling capacitance (eM) influence has been modeled regarding the short channel effect (SCE). Polynomial approximation is used to simplify and accelerate...

This paper presents a comparison between different models that have studied the effects of several parameter scaling on the performance of Carbon Nano Tube Field Effect Transistors. This evaluation for the studied models, with regard to the scaling effects, is to determine those which best reflect the very essence of Carbon Nano Tubes. Whereas the...

In this paper, a new accurate and efficient model for subthreshold leakage current is proposed for nanoscale metal oxide semiconductor field effect transistor (MOSFET). The influence of drain induced barrier lowering (DIBL) and gate induced drain lowering (GIDL) due to short channel effect (SCE) on subthreshold leakage is modeled and included in th...

In this paper, a new model for total backscattering coefficient (RBT) is proposed for both elastic and inelastic carrier scattering in silicon metal oxide semiconductor field effect transistor (MOSFET) nanoscale devices. The effect of the injection velocity (Vinj) as a function of the electric field (E) and low field mobility (μ0) is included and a...

two recent Voltage Programmed Pixel Circuits (VPPC) are compared in this paper. The principles for each circuit operation are discussed to determine the advantages and trends about design complexity and the performance of functionality. The Automatic Integrated Circuit Modeling Spice (AIM-Spice) Simulator is used for verification process. The simul...

two recent Voltage Programmed Pixel Circuits (VPPC) are compared in this paper. The principles for each circuit operation are discussed to determine the advantages and trends about design complexity and the performance of functionality. The Automatic Integrated Circuit Modeling Spice (AIM-Spice) Simulator is used for verification process. The simul...

In this paper, the effective carrier transport back scattering (BS) models for describing the low field mobility (µ 0) in nanoscale Metal Oxide Field Effect Transistor (MOSFET) with short channel effect (SCE) are discussed. The impact of acoustic and optical phonon scattering mechanisms on the total leakage current has been analyzed with more accur...

In this paper, recent MOSFET transport models in Nanoscale technology have been analyzed and compared. Modeling scenarios for each of these models are presents and compared with the others. Modeling of some nanoscale parameters such as mobility (µ), temperature (T), injection velocity (V inj), backscattering coefficient (R B), and effective electri...

Leakage power is the dominant source of power dissipation for Sub-100 nm VLSI (very large scale integration) circuits. Various techniques were proposed to reduce the leakage power at nano-scale; one of these techniques is MTV (multi-threshold voltage). In this paper, the exact and optimal value of threshold voltage (V th) for each transistor in any...

The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution becaus...

In this paper a method for calculating the starting point of conduction of parallel and serial transistor structures in CMOS gates for the nanoscale regime is introduced. The calculation of the starting point is necessary for modeling the operation of complex gates. The influence of the parasitic capacitances is determined and the subthreshold and...

In this paper, recent modeling techniques of Compact Metal Oxide Semiconductor (CMOS) transistor are presented and analysed in details. The challenges of modeling in Nanoscale technology with efficient solutions are also analyzed. The effect of some Nanoscale effective parameters on the characteristic (I-V) function are explained: Subthreshold leak...

A new current-programmed pixel design for AMOLED displays is presented in this manuscript. The proposed pixel is designed by using organic thin-film transistors and it exhibits high immunity to the threshold voltage variations of the transistors threshold voltage shift, caused by the bias stress and the intrinsic properties of the organic materials...

Hough Transform (HT) is a popular line detection algorithm in image processing and machine vision applications, favored for its tolerance to noise and partial occlusion. However, due to its computational complexity, software and hardware implementations for real-time video processing are usually limited to low resolutions and frame rates. We propos...

In this paper the operation of the pass transistor driving RC loads is investigated for nanoscale technologies. The widely accepted CRC π-model is used for the representation of RC loads. The different operational conditions of the circuit are determined and the differential equations which describe its operation are solved analytically. Appropriat...

Due to the significance of leakage power for CMOS circuits at Nanoscale, a new technique for Sub-threshold leakage current reduction based on Input vector control (IVC) is proposed. The proposed algorithm is called Fast Input Vector Algorithm (FIVA). It is characterized as faster than other algorithms, its speed doubles strongly of other algorithms...

As a result of the evolution to nano-technology, the demand for accurate Static Timing Analysis (STA) at transistor level for high speed/high performance digital integrated circuits is increased. Despite the existence of many research attempts to resolve the timing analysis problems, (STA) remains the best solution because of the extremely fast run...

The influence of the nanotechnology on the most frequent used dual edge trigger flip-flops (DET-FF) is presented in this paper. The performance and behavioural of those flip-flops are discussed and analysed analytically. Simulation results show that each time scaling down the SPICE parameters, some of the tested flip-flops did not work properly; it...

The current switching from μ-technology to n-technology generated a new challenges for CMOS circuit design. The optimization of power and delay together becomes the main issue in CMOS circuits design. Based on transistor level, a new algorithm for optimizing the Power Delay Product (PDP) for digital CMOS circuits is proposed in this paper. This alg...

In this paper the operation of the pass transistor for rising ramp signals in both terminal inputs, is analyzed. The differential equation of the circuit structure is solved, making the appropriate approximations, and analytical formulas for the output voltage is derived. Second order effects for nanoscale devices are taking into account. Compariso...

The influence of multi-threshold voltage technique on reducing the leakage power in CMOS circuits at transistor level based on Nanoscale SPICE parameters is investigated in this paper. Based on Artificial Intelligence search algorithms, three new algorithms are proposed to determine the exact threshold voltage for each transistor in order to minimi...

This paper studies the operation of the pass transistor structure taking into account secondary effects which become intense in nanoscale technologies. The different regions of operation are determined and the differential equation which describes the pass transistor operation is solved analytically. Appropriate approximations about the current wav...

Leakage power is the main dominant source of power dissipation for Sub-100nm VLSI circuits. Various techniques were proposed to reduce the leakage power dissipation; one of these techniques is Multi-Threshold voltage. In this paper, the exact and optimal values of Threshold Voltage (Vth) for each transistor of the design are found for any sequentia...

In this paper the performance of 8-transistor based Full adder is analyzed, evaluated, and compared with that of three different types of Full Adders based on Complementary Pass Transistor XOR Logic gate. Simulation results using nano-scale SPICE parameters are obtained for the above mentioned FAs. It is shown that the performance of the 8-transist...

This paper presents, for the first time, a full custom layout design for a Data Dependent Permutation (DDP)-Cobra H64-bit cipher, using pipelining techniques in the internal rounds blocks to increase the throughput of the design. As a result, the silicon area and the power dissipation are reduced too. The design achieves a small area by simplifying...

In this paper we extensively analyze and evaluate the leakage current power dissipation based on the most popular Header/Footer approaches. Five different Nano-Scale SPICE parameters are used to evaluate each approach in this paper. An efficient approach based on Header/Footer technique to reduce the leakage current and increase the speed operation...

The total power consumed by computer system depends upon the efficiency of its bus architecture. So the designers have attempted to invent low power bus architecture. This paper describes and compares the features of different techniques for low power bus architectures. The current state of the art of bus architecture will be the focus of this pape...

Problem statement: The educators argue that in the post modern world changes in the nature of work, globalization, the information reva luation and today's social challenges will all impa ct on educational priorities and thus will require a n ew mode of assessment. Approach: The objectives of this study were to: (1) Present a novel software pa ckag...

One-way hash functions are the main cryptographic primitives which are used in the network protocols for user authentication and message integration. In the literature, implementations have been proposed either in hardware or software. The rich number of implementations is expected considering the number of constraints of a target application. When...

The main idea of this paper is to discuss a new approach to optimize the value of leakage current in MOS transistors. It based on looking for optimal values of the main SPICE parameters which influence the value of the leakage current. These Values make in totally the leakage current, minimal value. The logic and the flow diagrams seem working corr...

The main idea of this paper is to discuss a new approach to optimize the value of leakage current in MOS transistors. It based on looking for optimal values of the main SPICE parameters which influence the value of the leakage current. These Values make in totally the leakage current, minimal value. The logic and the flow diagrams seem working corr...

A new layout design for a data dependent permutation (DDP)-Cobra H64-bit cipher optimized for low-power and high speed operation is presented in this paper. The layout is characterized as a design for mobile and handheld equipment. The design achieves low power consumption by using low power logic gates in layout level. Through the technique of pip...

This paper presents a novel software package tool creates multi-forms multiple-choice and true/false exams as well as the correspondence answer keys for each form automatically. The multiform exam can be created randomly from question database or manually with shuffled answers for each question. In order the proposed package to be widely used; vari...

A low-power design circuit using low-swing voltage technique is proposed in this paper. The proposed technique could be used in order to decrease the power dissipation in three different types of logic gates namely the complementary pass-transistor logic (CPL), the cascade voltage switch logic (CVSL), and the domino logic. The main idea of the prop...

Low power, high-speed bus architectures, based on low swing voltage technique, using multithreshold voltage transistors are proposed in this paper. Three different classes of driver/repeater/receiver circuits are introduced. The driver circuits are comprised of high threshold voltage MOSFET transistors, in order to reduce their output swing level v...

Low power, high-speed bus architectures, based on low swing voltage technique, using multithreshold voltage transistors are proposed in this paper. Three different classes of driver/repeater/receiver circuits are introduced. The driver circuits are comprised of high threshold voltage MOSFET transistors, in order to reduce their output swing level v...

New low-power design architecture based on low-swing voltage technique is proposed in this paper. A new CMOS inverter of three output-voltage levels is used to achieve this target. To verify the validity of the proposed technique, three different logic families are used. SPICE simulation results for the three logic families show that more than 45%...

Low-Power High-Speed Flip Flops (LPHSFF) are proposed in this paper. They are based on CMOS multi-threshold voltage techniques. High threshold voltage MOSFET transistors are applied on the non-critical paths of flip-flops in order to suppress the stand-by leakage-current, while low threshold voltage MOSFET transistors are applied on the cross-coupl...

A new low-power design method based on multiple low swing internal voltage values is proposed in this paper. It can be applied in logic circuits, which are designed with different logic family techniques such as Complementary Pass Transistor Logic (CPL), Domino Logic and Cascade Voltage Switch Logic (CVSL). The goal of this method is the reduction...

Novel low-power circuits based on low swing voltage technique, in the internal nodes of bus architectures, are proposed. Different classes of driver/receiver and repeater circuits are presented. They are implemented on conventional CMOS technology. The proposed technique is based on inserting a variable number of MOSFET transistors in the driver ci...

A new low-power design method based on multiple low swing internal voltage values is proposed in this paper. The proposed technique can be applied in logic circuits, which are designed with different logic family techniques such as Complementary Pass Transistor Logic (CPL), Domino Logic and Cascade Voltage Switch Logic (CVSL). The goal of this meth...

New driver/receiver CMOS circuits design, for low-power VLSI applications, are proposed. They are based on the low swing technique. A significant reduction in power dissipation is achieved, due to the reduced swing voltage on the interconnection loads. Comparisons of the delay time of the proposed circuits with the conventional CMOS driver/receiver...

A new low-swing/low-power CMOS driver architecture for VLSI applications is proposed. The architecture based on low swing technique using the conventional CMOS static logic. Simulation results based on the proposed design show significant improvements in both power dissipation and power-delay product compared to other low swing techniques driver ar...

A low swing voltage design technique is proposed. The new design could be used successfully in order to decrease the power dissipation in Complementary Pass-Transistor Logic (CPL) as in Cascade Voltage Switch Logic (CVSL) logic gates. The achieved gate output voltage-level swing reduction, results in a significant reduction of their power consumpti...