Aadil Anam

• Researcher at IIT Kanpur M.Tech PhD Jamia Millia Islamia New Delhi
• Research Fellow at Indian Institute of Technology Kanpur

In this article, a Schottky barrier β‐Ga2O3 MOSFET is proposed. It shows improvements in drain saturation current, Ion/Ioff ratio, transconductance, and off‐state breakdown voltage. The proposed design, which implements the Schottky barrier source and drain contacts, has led to reduced on‐state resistance (Ron), reduced forward voltage drops, faste...

In this paper, we introduce a novel III–V compound material-based junction-free (JF) L-shaped gate normal line tunneling field-effect transistor (III–V JF L GNLTFET) for improved output performance at 0.5 V operation. The key design metric, i.e. JF or junctionless design, in our device eliminates issues like random dopant fluctuations (RDF) and hig...

Silicon-based spin qubits have emerged as promising candidates for scalable quantum information processing. This study first time investigates the behaviour of ultra-scaled 10 nm gate length and 3 nm channel thickness nanoscale double gate metal-oxide semiconductor field-effect transistors (MOSFETs) over a broad temperature range, from deep cryogen...

In this paper, a comparative analysis of ambipolarity suppression in conventional PNPN-TFET(D-1) is studied using TCAD simulation. By replacing the drain with metal silicide, and by implementing the dopant-segregated Schottky-barrier drain (DSSBD) in conventional PNPN-TFET, two new devices named PNPM-TFET(D-2) and DSSB-PNPM-TFET(D-3) has been propo...

In this noteworthy paper, we present a novel and comprehensive investigation into the optimization of performance parameters for the conventional U-Gate III-V line TFET through TCAD simulation. Our unprecedented threefold optimization strategy encompasses multiple facets, marking a significant contribution to the field. Firstly, in our pursuit of e...

In this paper, a charge plasma-based inverted T-shaped source-metal dual line-tunneling field-effect transistor (CP-ITSM-DLTFET) has been proposed to improve the ON current (ION) by increasing the line-tunneling area. In the proposed structure, the charge plasma technique is used to induce the dopants in the source/drain region. Due to its doping-l...

In this paper, two III-V material-based junctionless tunnel FET devices, D-1 and D-2, are proposed. The proposed device D-1 has a low bandgap (GaSb-based) dual source and a higher bandgap (GaAs-based) T-channel junctionless, and the proposed device D-2 has the same architecture as D-1 in addition to a metal strip implant in the gate oxide near both...

In this paper, the undoped vertical dual-bilayer tunnel field effect transistor (UV-DBL-TFET) at a low operating voltage (0.5 V) is introduced, and its DC and RF performance parameters are compared with those of the conventional charge plasma-based symmetrical gate electron–hole bilayer TFET (CP-SG-EHBTFET). The charge plasma technique is used in t...

In this paper, the complementary charge-plasma (CP) based symmetrical-gate electron–hole bilayer (EHB) tunnel field-effect transistor (TFET) at a low operating voltage (⩽0.5 V) is introduced. Where, by using CP technique, the source/drain and EHB-channel is induced by depositing metal electrode with appropriate work function. Moreover, the immunity...

In this paper, the design and performance analysis of GaSb/Si-based Negative Capacitance (NC) Tunnel Field Effect Transistor (TFET) are comparatively analyzed at both device and circuit levels. The simultaneous incorporation of the GaSb (low energy bandgap material) at the source region and ferroelectric material at the MOS gate stack in the propos...

In this paper, a dielectrically modulated symmetrical double gate, having dual gate material, Tunnel Field-Effect transistor with Buried strained Si1-xGex source structure, has been investigated as a biosensor. This structure is proposed for the very first time to electrically detect the biological molecules at very low power consumption. In the pr...