Question
Asked 3rd Apr, 2014

What are the reasons for clock skew in digital circuit systems?

What are the reasons for differences in clock signal arrival times across the chip (clock skew) apart from gate delays (gates driving the clock) and wire delays?

Most recent answer

22nd Sep, 2020
Umapathi Nagappan
Jyothishmathi Institute of Technology and Science
In designing digital logic circuits clock skew means the difference between the input clock signal arrival in different time and the clock skew can be caused by different things, such as the length of the interconnecting wire, the input capacity, and the variance in intermediate blocks or devices on the clock inputs of the devices that use the clock.

All Answers (14)

3rd Apr, 2014
Aneesh Raveendran
Centre for Development of Advanced Computing, Bangalore
please read VLSI DSP by parhi.....You will get the exact idea of the clock skew
3rd Apr, 2014
Aneesh Raveendran
Centre for Development of Advanced Computing, Bangalore
The difference in arrival times of the clock signal at any two flops which are interacting with one another is referred to as clock skew. Clock skew is classified into two categories (+ve skew and -ve skew).
If the clock at the capture flop takes more time to reach as compared to the clock at the launch flop, we refer to it as Positive Clock Skew.
when the clock at capture flop takes less time to reach the clock at the launch flop, we refer to it as Negative Clock Skew.
1 Recommendation
5th Apr, 2014
Mohammad Waris
Space Application Center
Actually it is the difference of delays on clock network for source and destination flipflop.
1 Recommendation
5th Apr, 2014
Narendra Varma Alluri
International Institute of Information Technology, Hyderabad
Thanks Mohammad Waris , i just want to know the reasons for those delays.
apart from physical wire delays and gate delays if there are any in the clock path are there any other reasons possible for creating delays in the clock path.
5th Apr, 2014
Aneesh Raveendran
Centre for Development of Advanced Computing, Bangalore
An asynchronous clock(same clock frequency form different sources) can cause clock skew.
9th Apr, 2014
Guangda Zhang
The University of Manchester
The asynchronous circuits should be good choice to tackle clock skews.
10th Apr, 2014
Felix Lang
Universität Stuttgart
See a small list of reasons at http://en.wikipedia.org/wiki/Clock_skew ;-)
2 Recommendations
21st Apr, 2014
Víctor Navarro-Botello
Universidad de Las Palmas de Gran Canaria
In a wide and rigorous definition, clock skew is just due to different gate and wire delays.
But in this wide definition, you must include differences in the load and/or fanout conditions which can alter the gate and wire delays. Note that even small mismatches of devices (transistors and capacitors) can affect in some way the load condition of the clock signal, thus, causing clock skew.
Furthermore, even temperature or stress differences can alter the drive and/or load conditions, causing gate/wire delay differences, and thus, clock skew. Even different inputs to the flipflops which clock signals are connected to, can cause different load conditions at the clocks signals, causing clock skews (this source of clock skew is not significative at all in practical cases).
I hope this can help you,
2 Recommendations
12th Jun, 2014
Mike Valliant
Temple University
Examining a model that includes T-line and analog gate conditions, problems stand out. There are temperature dependent parasitic RLC lead lag networks, variation between gates as previously mentioned, and the signal paths are also capacitivly coupling signal to ground. Of these I believe the last has the most noticeable effect. By filtering away high frequency portions of the signal the edge is rounded increasing its rise time in addition to the simple wire propagation.delays.
Another interesting suspect that Mr. Navarro-Botello already briefly mentioned is capacitive and inductive coupling between signal paths. If the coupled signals are in the same direction high capacitance or low inductance will cause SUT to skew fast, opposite case holds as well.
2 Recommendations
8th Jul, 2014
Narendra Varma Alluri
International Institute of Information Technology, Hyderabad
Thank you , Victor Navarro-Botello and Mike Valliant for the info. it was quite helpful.
In what way does the sizing of semiconductor devices and the semiconductor material composition affects the skew in-terms of various capacitive and inductive coupling effects ?? Any Publication regarding this would be much helpful.
1 Recommendation
8th Jul, 2014
Mike Valliant
Temple University
The smaller things get the larger the influence of all the errors I mentioned. Also their relatively more significant as signal levels decrease with size. Heat becomes more important. Materials will change the coupling coefficients  between unconnected paths and have different temperature conductance curves and T-line parameters in the path. These are just the obvious things. Sadly I don't have access to a good academic library anymore, I would just be using google.
 
good luck with the research!
Mike V.
Deleted profile
 clock skew happens due to difference of delays in clocktree for receiving and sending flipflops.
Secondly, in multiclock designs, skew happend between different clocks, for this all clocks need to be synchronised using some popular synchronisation techniques. One of the solution is to use asynchronous designs, use FIFOs for proper functioning. Then another challange comes in DFT of the design.

Similar questions and discussions

Related Publications

Thesis
Different VLSI architectures are examined and their suitability for various matrix problems are evaluated. The architectures considered include chain, broadcast chain, chain with memory, mesh, broadcast mesh, and hexagonally connected processor arrays. In evaluating a VLSI design, the main concern is the time the VLSI system needs to complete its t...
Chapter
VLSI Design and Education Center (VDEC) was established in 1996 as an inter-university center at the university of Tokyo for promoting education of VLSI design in Japan1. VDEC is a kind of COE of VLSI design education, which covers mainly three functions; (1) providing educational information for VLSI design, (2) providing CAD software tools and (3...
Conference Paper
Full-text available
With the growth in multimedia technology, demand for highspeed real time image compression system has also increased. JPEG 2000 standard is developed to cater such application requirements. However, the sequential execution of the bit plane coder (BPC) used in this standard consumes more clock cycles. To improve the performance of the BPC, a new co...
Got a technical question?
Get high-quality answers from experts.