Bonding PDMS to microelectronic chip: any of you has experience in doing that?

What are the thicknesses of each of metal layer 1 to metal layer 6 in 180 nm CMOS Ip6M? Also what are the thicknesses of each of the oxide layer separating them and the silicon layer at the end? What is the thickness of the passivization layer on top? Also kindly provide the source of information.

I had found some literature that develops MEMS stress sensor (CMOS, N-MOS, P-MOS). However, I can't find commercial solutions for this type of sensor. Is there any replacement? (Stress measurement, tiny dimension).

Many thanks

Considering any CMOS technology, I am eager to know what is the upper limitation of MOSCAP design. Also I want to know that MOSCAP is larger than conventional on chip capacitors or not. For instance how to compare 1pF MOSCAP and a 1pF on chip capacitor regarding die occupation. Totally avoiding passive elements in chips can save lots of area, so I am looking for methos for realizing larger capacitors with smaller die occupation.

I am a researcher in Silicon Photonics (also known as CMOS photonics). Sometimes I was in trouble because I do not have real experience of CMOS-compatible process, and I will doubt if the designed process for photonics material or device is really CMOS-compatible. For example, co-sputtering technique, high temperature thermal annealing, are CMOS-compatible? What is the criteria to judge?

Any discussion is welcome. Thank you very much!

We live in a world powered by computer circuits. Modern life depends on semiconductor chips and transistors on silicon-based integrated circuits, which switch electronic signals on and off. Most use the abundant and cheap element silicon because it can be used to both prevent and allow the flow of electricity; it both insulates and semiconducts.

Until recently, the microscopic transistors squeezed onto silicon chips have been getting half the size each year. It’s what’s produced the modern digital age, but that era is coming to a close. With the internet of Things (IoT), AI, robotics, self-driving cars, 5G and 6G phones all computing-intensive endeavors, the future of tech is at stake. So what comes next?

source: Silicon chips are reaching their limit. Here's the future | TechRadar

Which structure of the transistor is the most sensitive to pressure? A vertical NPN transistor and a vertical/lateral PNP transistor are considered. Which structure of the transistor will be the least sensitive to temperature and will have the lowest noise component of the output signal?

Hi, does anyone have experience in MIMETAS 3D Human Blood-Brain Barrier Tissue Model? I have a problem with 40 primary HBMEC tubules. Cells attached in perfusion channels but later no way to get tubules, for some reason, they do not form tubules. Cells looks and proliferate in flasks absolutely fine. Plate on rocker with an inclination of 7° and an interval of 8 minutes is optimal for this type of cells. I use seeding with passive pumping. Would be happy with any comments or suggestions.

Hello,

im trying to use the RFID tag in order to sensing something with passive mode.

so far, thought about the SL900A chip as an candidate,

since it has quite many reference paper which use SL900A as an transponder tag.

however, it seems do not in stock anymore.

is there any chip that you can suggest as an replacement for SL900A?

long to short,

1. RFID transponder tag

2. Passive mode

3. Sensing interface

that is the all the features what im looking for now.

if it is possible, 900MHz frequency range might be better to use.