Overcoming the difficulty in reproducibility and deterministically defining the metal phase of metal-semiconductor heterojunctions is among the key prerequisites to enable next-generation nanoelectronic, optoelectronic and quantum devices. In this respect, a comprehensive understanding of the charge carrier injection and the electronic conduction mechanisms, which are distinctly different from conventional MOSFETs, are necessary. Here, we provide an in-depth discussion of the transport mechanisms in Si and Ge nanowires (NWs) embedded in Schottky barrier (SB) FETs (SBFETs). Key for the fabrication of these devices is the selective and controllable transformation of Si and Ge NWs into Al, which enables high-quality monolithic and single-crystalline Al contacts, fulfilling compatibility with modern CMOS fabrication. To investigate the transport in Al-Si and Al-Ge heterostructures, detailed and systematic electrical characterizations carried out by bias spectroscopy in the temperature regime between T = 77.5 K and 400 K. Thereof, activation energy maps have been extracted to evaluate the effective SB height for electrons and holes in both material systems. The Al-Si material system revealed symmetric effective SBs, which is interesting for reconfigurable electronics relying on reproducible nanojunctions with equal injection capabilities for electrons and holes. In stark contrast, the Al-Ge material system revealed a highly transparent contact for holes due to Fermi level pinning close the valance band and charge carrier injection saturation by a thinned SB, while thermionic and field emission mechanism limit the overall electron conduction. In this regime, nanometer scale Ge departs from its bulk counterpart and delivers a strong and reproducible negative differential resistance followed by a sudden current increase indicating the onset of impact ionization above a certain threshold electric field. Most importantly, the presented description of the temperature dependent transport mechanisms in Al-Si and Al-Ge nanojunctions contributes to a better understanding of metal-group-IV based SBFETs, which are highly anticipated for the implementation of electronic device functionalities beyond the capabilities of conventional FETs.

In this work, monolithic, and crystalline Al–Ge–Al heterostructure nanowire field effect transistors (FETs) with Ge channel lengths ranging from 18 to 826 nm are analyzed from a low-frequency noise perspective. 1/f and random telegraph noise (RTN) are analyzed in an accumulation mode, where the hole channel is formed by applying a back-gate potential VG. The normalized power spectral density of drain current fluctuations of 1/f noise at medium currents follows nearly an 1/ID trend. 1/f noise is analyzed within both the mobility and carrier number fluctuation models (MFM and CNFM), respectively. Taking the MFM into account, the Hooge noise parameter spreads with lower values for shorter devices. Using the same data and the CNFM, the density of interface states Dit in the oxide-Ge system was estimated using the transconductance extracted from the quasi-static transfer I/V characteristics . Contact noise has also been observed in some devices at high currents. RTN analyzed in time domain exhibits a relative RTN amplitude in the 0.3%–20% range. Capture and emission time constants as a function of VG exhibit a typical behavior for metal oxide semiconductor FETs. The extracted noise parameters are comparable with Ge and III–V nanodevices of top-down and bottom-up technologies.

In this work, bottom-up and top-down structured Al-Si-Al heterostructure devices are integrated in a three top-gate architecture enabling reconfigurable transistors. Therefore, VLS grown Si nanowires (NWs) and nanosheets structured from silicon-on-insulator substrates are used as starting material. Utilizing TEM and EDX, the Al-Si interface was analyzed and proven to be single elementary and monocrystalline without any intermetallic phase common in e.g. Ni-silicide. Evaluating the key parameters of these transistors regarding the on- and off-currents as well as threshold voltages for n- and p-type operation revealed a high degree of current symmetry in both modes. Remarkably, the Al-Si material system exhibits a high symmetry without any additional measures, such as interface or strain engineering commonly applied in other metal-semiconductor systems. Due to the growth of thermal SiO2, the devices exhibit a stable and reproducible electric behavior leading to a low device-to-device variability further allowing suitable integration in logic circuits. In this respect, the investigated Al-Si material system revealed its relevance for reconfigurable logic cells, which highly rely on symmetric on- and off-currents as well as threshold voltages. Hence, selected implementations of basic logic gates were realized. Here, we demonstrate an inverter and a combinational wired-AND gate based on bottom-up NWs. In this respect, exploiting the advantages of the proposed multi-gate transistor architecture, offering additional logical inputs, the device functionality can be expanded by transforming a single transistor into a logic gate. Importantly, the demonstrated Al-Si material system and thereof shown logic gates provide high compatibility with state-of-the-art complementary metal-oxide semiconductor technology. Additionally, the proposed material system allows us to up-scale the current driving capabilities required for advanced logic circuits. Remarkably, this approach still maintains a sufficient degree of current symmetry, proving its suitability for logic circuits. In this respect, a top-down parallel wire approach without compromising reconfigurability was investigated. Most notably, this CMOS-compatible platform may pave the way for adaptive and even self-learning digital circuits, which feature energy efficient and low footprint computing paradigms.

Overcoming the difficulty in reproducibility and deterministically defining the metal phase of metal-semiconductor heterojunctions is among the key prerequisites to enable next-generation nanoelectronic, optoelectronic and quantum devices. In this respect, a comprehensive understanding of the charge carrier injection and the electronic conduction mechanisms, which are distinctly different from conventional MOSFETs, are necessary. Here, we provide an in-depth discussion of the transport mechanisms in Si and Ge nanowires embedded in Schottky-barrier FETs. Key for the fabrication of these devices is the unique selective and controllable transformation of Si and Ge nanowires into Al, which enables high-quality monolithic and single-crystalline Al contacts, fulfilling compatibility with modern CMOS fabrication. TEM and EDX confirmed both the composition and crystalline nature of the presented heterostructures, with no intermetallic phases formed during the exchange process. To investigate the transport in Al-Si and Al-Ge heterostructures, detailed and systematic electrical characterizations carried out by bias spectroscopy in the temperature regime between T = 77.5 K and 400 K. Thereof, activation energy maps have been extracted to evaluate the effective Schottky barrier height for electrons and holes in both material systems. The Al-Si material system revealed highly symmetric effective Schottky barriers, which is highly interesting for reconfigurable electronics relying on reproducible nanojunctions with equal injection capabilities for electrons and holes. In stark contrast, the Al-Ge material system revealed a highly transparent contact for holes due to Fermi level pinning close the valance band and charge carrier injection saturation by a thinned Schottky barrier, while thermionic and field emission mechanism limited the overall electron conduction, indicating a distinct Schottky barrier for electrons. In this regime, nanometer scale Ge departs from its bulk counterpart and delivers a strong and reproducible negative differential resistance (NDR) followed by a sudden current increase indicating the onset of impact ionization above a certain threshold electric field. Importantly, embedding the proposed Al-Ge heterojunctions into a three-gate FET architecture provides a unique fusion of the concept of reconfiguration and NDR embedded in a universal adaptive transistor that may enable energy efficient programmable circuits with multi-valued operability that are inherent components of artificial intelligence electronics. Most importantly, the presented description of the temperature dependent transport mechanisms in Al-Si and Al-Ge nanojunctions contributes to a better understanding of metal-group IV based Schottky barrier FETs, which are highly anticipated for the implementation of electronic device functionalities beyond the capabilities of conventional FETs.

Si1-xGex is a key material in modern complementary metal-oxide-semiconductor and bipolar devices. Importantly SiGe and Ge are promising materials to enable higher drive currents, reduced power consumption and enhanced switching speeds. However, despite considerable efforts in metal-silicide and-germanide compound material systems, reliability concerns have so far hindered the implementation of metal-Si1-xGex junctions that are vital for diverse emerging "More than Moore" and quantum computing paradigms. In this respect, we report on the systematic structural and electronic properties of Al-Si1-xGex heterostructures, obtained from a thermally induced exchange between ultra-thin Si1-xGex nanosheets and Al layers. Remarkably, no intermetallic phases were found after the exchange process, alleviating process variability compared to Ni-silicide/Ni-germanide contacts. Instead, abrupt, flat and void-free junctions of high structural quality could be obtained. Interestingly, ultra-thin interfacial Si layers formed between the metal and Si1-xGex segments, explaining the morphologic stability. Integrated into omega-gated Schottky barrier transistors with the channel length being defined by the selective transformation of Si1-xGex into single-elementary Al leads, a detailed analysis of the transport was conducted. Thereby, the vertical Si-Si0.67Ge0.33 heterostructure showed high potential for reconfigurable field-effect transistors (RFETs). This emerging device concept is capable of dynamically switching between p-and n-type operation during run-time, overcoming the static nature of conventional CMOS and reducing the transistor count and the circuit path delay. Further, RFETs enable an efficient implementation of dynamically reconfigurable logic gates, allowing e.g. switching between NAND to NOR functions, or intrinsic XOR functionality. The here proposed top-down fabricated SiGe-based reconfigurable transistor technology comprising a vertical Si-Si0.67Ge0.33 heterostructure enables high and symmetric on-currents of both n-and p-type operation, which has so far fallen short in Ge based RFETs due to interface instability to their contacts and gate oxides. The implementation of a three top-gate transistor in combination with a hysteresis-free SiO2/HfO2 gate insulator stack, enhances polarity control and leakage current suppression to limit static power dissipation. Importantly, the obtained Al-Si-SiGe multi-heterojunction and advanced reconfigurable transistor design is the first Ge based technology showing the envisioned stability and performance enhancements.