Solid State Technology

The addressable inverter matrix consists of 222 inverters each accessible with the aid of a shift register. The structure has proven useful in characterizing the variability of inverter transfer curves and in diagnosing processing faults. For good 3-micron CMOS bulk inverters investigated in this study, the percent standard deviation of the inverter threshold voltage was less than one percent and the inverter gain (the slope of the inverter transfer curve at the inverter threshold voltage) was less than 3 percent. The average noise margin for the inverters was near 2 volts for a power supply voltage of 5 volts. The specific faults studied included undersize pull-down transistor widths and various open contacts in the matrix.
The integrity of the metal-poly oxide and the gate oxide was evaluated for several 5-micron CMOS-bulk processes. The pinhole array capacitor consists of diffused and poly fingers that form a network of MOS transistors (elements), which are capped by a deposited oxide and metal layer. The smallest structure used in this study contained about 15,000 elements and the largest structure contained about 68,000 elements. Each structure was divided into several subarrays. The structures are placed a number of times on each wafer. From a yield analysis of the subarrays, the elements per defect were found to be typically in excess of 50,000 elements/defect for the metal-poly oxide and 100,000 elements/defect for the gate oxide. From the switching behavior of the transistors, the gate oxide defects were tentatively identified as gate-to-body shorts rather than gate-to-diffusion shorts.
Techniques and materials have recently been developed to obtain high dielectric films /K of 300 to 800/. High dielectric barium titanate particles are mixed in a barium titanate glass.
Integrated circuit failure analysis with scanning electron microscopy taking into account ball bond contamination and open metallization at contact windows
A design analysis of a high density multilevel thick film digital microcircuit used for large scale integration is presented. The circuit employs 4 mil lines, 4 mil spaces and requires 4 mil diameter vias. Present screened and fired thick film technology is limited on a production basis to 16 mil square vias. A process whereby 4 mil diameter vias can be fabricated in production using laser technology was described along with a process to produce 4 mil diameter vias for conductor patterns which have 4 mil lines and 4 mil spacings.
A review is presented of a vapor-phase growth method that has been developed for this synthesis of a broad spectrum of III-V compounds. The predominant feature of this technique is the use of gases as the source chemicals, thereby providing improved control of the chemical composition, homogeniety, crystalline perfection, and impurity concentrations and distributions of the epitaxial layers. As as result, a number of notable advances have been made with respect to the material properties and device utilization of several III-V compounds. The chemistry of the deposition processes was studied by means of a mass spectrometer coupled to the vapor-phase growth system. Results oif these studies are presented and discussed.
In this paper, we investigated the impact of immersion lithography on wafer edge defectivity. In the past, such work has been limited to inspection of the flat top part of the wafer edge due to the inspection challenges at the curved wafer edge and lack of a comprehensive defect inspection solution. Our study used a new automated edge inspection system that provides full wafer edge imaging and automatic defect classification. The work revealed several key challenges to controlling wafer edge-related defectivity, including choice of resist, optimization of EBR recipes, and wafer handling.
Among various nondestructive inspection techniques a key role is played by optoelectronic methods. They can assist in most inspection activities such as discontinuity control, body geometry measurements, study of chemical and physical properties, and in construction of instruments for technical diagnostics. One of the basic needs of today's optoelectronic instrumentation is hardware miniaturization, reliability and accuracy characteristics. Major advances in solid state physics and semiconductor technology make semiconductor data photoreceivers practicable. The paper outlines the structure of a range of data semiconductor photoreceivers and describes design principles of some of them. Examples of their use in nondestructive monitoring systems are given.
With phased array techniques it is possible to influence the sound field on a large scale by electronically steering the elements of an array probe: by phase steering, normal, focused and angle probes can be substituted by a single array probe; by amplitude shading the side lobes of the sound field can be reduced. With electronically steered array probes it is possible to have high detectability as well as high lateral resolution by synthesizing a large sector by fast electronically steering a narrow sound beam (sector scan). The fast electronic beam steering makes it possible to build up real-time imaging systems (sector scanner, compound scanner). The paper reports on electronic beam forming and defect characterization by sector and compound scanning.
The Monte Carlo method has been used to develop a stochastic digital simulation model of a radiographic image registration process as an integral system. The model accurately predicts the real interactions occurring in the radiographic system, and it will be used to quantitatively determine the signal to noise ratio at each density level of an image. As such, it can provide a general tool for characterization of different detectors and for optimization studies in medical and industrial radiography.
An investigation has been carried out to determine whether the computer processing of digitized radiographs might be able to enhance those features on the image which are attributed to corrosion in the sample. The relatively simple technique of histogram equalization was successful in enhancing the corrosion detail. A possible method is also proposed for analyzing the history of a corrosion site.
Design formulas are developed for both fixed and extendable overhangs as a function of window height, geographic latitude, and solar altitude. The extendable overhang is adjusted seasonally. Design parameters are suggested for near optimum solar control in direct gain passive systems. A method of estimating the effect of an overhang on solar gain is also developed. Examples of the solar performance for both fixed and adjustable overhangs are presented for 36 deg N latitude.
The move toward 300mm and total automation has heightened the importance of equipment-to-factory integration. One of the fundamental sticky points is the correctness of the information of the SECS/GEM link. We have matured to the point where we can successfully get SECS/GEM links operating; however, data communication over these links leaves a lot to be desired. For example, critical data are often not available, not provided with sufficient context to be understood, or not reported in a timely fashion. Events are often not James Moyne reported or are reported out of order. These types of problems are often addressed through preemptive testing of the SECS/GEM interface. Preemptive testing of the SECS/GEM link should be considered a requirement. However, even with successful testing, there is another class of important problems in equipment integration. These focus on data quality necessary to support data-intensive activities such as APC. Increasingly, components of APC, such as run-to-run (R2R) control and FDC, are becoming an essential part of equipment integration. APC is often required to provide the process capability, throughput, and yield necessary to remain competitive. However, APC is only as good as the data it receives, and the majority of this data comes from the equipment interface. Common problems with the equipment interface with respect to APC include: FDC data to monitor equipment health cannot be reported fast enough or collection of data impacts the speed of the equipment automation interface; the tool doesn't provide for actuation of individual process program parameters via the SECS interface to support R2R control; and the reported data are of sufficiently poor quality (lack of context, freshness, accuracy, or accuracy indication, etc.) so that APC algorithms cannot be effectively implemented. The community has realized that the SECS/GEM interface is not well suited for APC data reporting. They have begun specifying a second tool "equipment data acquisition" interface that will eventually be Utilized to support APC data collection. The emergence of this second interface will go a long way toward addressing this data quality issue; however, it is important to note that APC systems that use this data must always be robust so that they discriminate against bad data. For example, R2R control systems should be able to handle missing, out-of-order, or erroneous metrology data. FDC systems must have a configurable data collection system so that data collection can be matched to the processing power of the tool. Finally, data quality test solutions are needed to identify equipment data problems and limitations. Equipment-to-factory integration is a protocol and a data issue. We have maturing testers to verify the protocol capability. We need to enhance these test capabilities and feed the lessons learned and best practices back into enhancement of integration standards. With respect to the data issue, we must also provide test capabilities to verify data quality of equipment interfaces. Test solutions for data quality should emerge over the next year. However, we must also make sure that our APC systems are robust enough to deal with data quality issues in an automated fashion.
Jet electrochemical deposition plating [1-2] has shown excellent capability for void-free Cu filling of narrow openings with very large aspect ratios. JECD facilitates high-speed plating, with fully bright deposits at higher speeds. Additional "leveler" additives and pulse plating are not necessary for the elimination of spikes, bumps, or humps. JECD also provides wide process latitude, Here we suggest an enhanced inhibition model explaining the mechanism and the beneficial effects of JECD. We also report an innovative multiple-Cu seed layer [2-3] combining at least one PVD and one CVD Cu layer.
Unlike traditional design rule checks, which have a clear pass or fail definition, yield issues are dependent on a number of variables and are more difficult to pin down. Chip and wafer planarity, metal and oxide adhesion, and electrical charge effects can have a major impact on total chip yield. By identifying trouble spots and implementing a "cure," it may be possible to achieve a yield greater than that created by simply meeting the design rules and guidelines. For example, rather than placing diodes arbitrarily - even if consistent with design rules - better yield can result if parasitic effects are considered when placing them.
Ion implant manufacturers face process- and productivity-driven equipment performance challenges as device design rules shrink into the ≤0.18-μm regime and wafer size moves from 200 to 300 mm. These challenges apply to all three implanter segments (high current, medium current, and high energy) and can be separated into two distinct categories: process-level and productivity-level challenges. Approaches to these challenges vary among ion implant equipment manufacturers. Several key process- and productivity-level challenges will have the greatest effect on future equipment designs. These are the formation of ultra-shallow junctions in the sub-100-nm range in production environments (high-current implanters); the cost-effective formation of high-dose, high-energy buried layers (high-energy implanters); and the precision placement of dopants in sub-0.25-μm channels (medium-current implanters).
A 0.18μm embedded flash process has been developed that offers high yields with its small size. The core CMOS characteristics were kept same in the process. The embedded memory process involves the assimilation of memory cells and HV devices into a core CMOS process flow. However, process integration efforts focused on two process modules - memory cell formation and gate formation. The memory storage media are deep traps introduced in the nitride-top oxide interface of the ONO stack.
The implementation of reticle enhancement technology (RET) for achieving sub-0.2k1 imaging was analyzed by using off-axis illumination method. The chromeless phase lithography (CPL) aerial image formation was found to have pairs of phase edges which differed significantly from attenuated phase-shifting mask (attPSM). The results showed that the three dimensional topology effects were not found in the CPL reticles.
Recent magnetically enhanced reactive ion etcher (MERIE) technology development focuses on damage performance, high-selectivity processes, and improved reliability. A pulsed magnetic field reactor, whose design is based on magnetic field manipulation studies, uses an existing MERIE coli configuration to produce highly uniform plasma over a wide process window. A new process chemistry demonstrates high setectivities on both traditional and pulsed MERIE reactors. Finally, advances in polymer management and power transfer improve chamber reliability and system productivity.
Transistors in ICs have conventionally been isolated by growing thick SiO2 thermally in the regions between them. This so-called local oxidation of silicon (LOCOS) masks off the active areas with a layer of silicon nitride (Fig. 1a). The main drawback of LOCOS, the unacceptably large dimension of the "bird's beak," limits its utility for the smaller geometries in sub-0.25-μm designs. Shallow trench isolation (STI), in contrast, uses deposited dielectrics to fill trenches etched in the silicon between the active areas. In principle, it is only limited by the lithography, etch, and gap-fill depositions, which have thus far scaled with transistor technology. Therefore, STI is an attractive alternative to LOCOS for deep submicron ICs. This article discusses key considerations in the development of the STI module and highlights potential problems for large-scale implementation of STI in wafer fabrication.
A conventional lithographic illumination system with binary masks does not provide the processing latitude needed to meet the critical dimension (CD) specifications for 0.30μm random-logic poly gates. The use of a high numericalaperture stepper and a resist process with bottom antireflection coating combined with annular illumination and an attenuated phase-shifting mask resulted in enlarged individual process windows. The overlapping combined lithography window, however, was narrower than the conventional illumination system. The incorporation of opical proximity correction (OPC) improved these windows and across-chip illnewidth uniformity. This optically enhanced i-line process with OPC effectively printed 0.30-μm circuits with CD variations of less than ±10%.
Two new optically-based surface imaging processes for fabricating sub-0.5 μm features are described. In the first, a monolayer film is patterned with deep UV radiation and then metallized by electroless deposition to form a thin metal layer only on the unexposed areas. The metallized film provides an effective reactive ion etch barrier. Features with 0.3 μm linewidth in polysilicon and working transistor test structures have been demonstrated with this process. In the second approach, a 1 to 2 μm (planarizing) photoresist layer is exposed in its near-surface region. A thin metal layer is then formed on unexposed photoresist regions by electroless deposition and serves as an etch mask for subsequent pattern transfer. In this process variation, features with < 0.5 μm linewidth have been printed using i-line and 248 nm excimer laser tools.
Electroplating sub-100nm Cu interconnects using large elecrotlyte baths faces limitations in the area of defect control repeatability and gap-fill consistency. A modular plating cell design with an independent electrolyte circulation loop supports a multistep plating process with different chemistries in different cells, enabling approaches to meet both gap fill and film planarization for sub-100nm Cu metalliztion. The small-volume plating cell with a periodic refill of plating chemicals also allows minimum buildup of organic additive breakdown products and particles in the plating bath.
Recent advances in lithography simulation have made full-chip lithography rule checking (LRC) a mandatory inspection procedure for many fabs handling sub-100nm designs. This article proposes a hot-spot removal approach that is fast, comprehensive, and achieves manufacturing convergence.
Transistor junction characteristics [1] 
Comparison of key issues for sub-100nm CMOS for bulk silicon and (fully-depleted) SOI transistors
SEM images of the SOI layer edge profile for a) as-cleaved and b) fully-processed Nanocleave SOI wafers.
Planar CMOS transistors on bulk silicon wafers are expected to reach their limits at gate sizes of about 50nm in 2005-06. Many of the process and materials constraints that combine to force this change in technology path are relaxed or removed for CMOS devices fabricated on SOI wafers. This article outlines the principal issues limiting junction formation for sub-100nm CMOS on bulk silicon and presents an alternative roadmap using SOI wafers. An SOI wafer fabrication technology is described that provides a room temperature, atomic layer cleaving process with unprecedented levels of control on silicon layer thickness, as well as a clear path for extension towards the ultrathin SOI regime.
To continue the scaling trend of CMOS technology, the anticipated high gate leakage current in ultrathin gate dielectrics must be suppressed. In addition, dielectrics must also suppress boron diffusion and act as a barrier. A stack of oxide and nitride layers is an attractive replacement for the gate dielectric. In this article, we present a gate dielectric composed of an oxide-on-nitride stack that provides two orders of magnitude lower leakage current than thermal oxide, minimal saturation current degradation, boron penetration suppression, and improved reliability. Good wafer-to-wafer repeatability is demonstrated over a period of a few months.
Key developments such as improved spike anneal temperature control, enhanced low-temperature processing capability, and a radical-based oxidation process are extending the capabilities of rapid thermal processing for applications such as ultra-shallow junction activation and anneal, silicidation, and shallow trench isolation liner oxide formation to meet projected industry roadmap requirements for sub-100nm device design nodes [1].
As semiconductor designs are downscaled to sub-100nm nodes, low thermal budgets and critical requirements for microscopic uniformities, such as low micro-roughness, along with process dependency on crystal orientation and materials, will all be more important. To address these issues, radical process changes will be needed.
Shrinking feature sizes are making devices increasingly vulnerable to gas-phase contamination. Aggressive gas-impurity milestones set in the International Technology Roadmap for Semiconductors (ITRS) call for a 90% reduction in levels of moisture, oxygen, carbon dioxide, and methane in bulk gases for leading-edge processes between 2004 and 2006. Existing gas supply, analysis, and purification techniques have proven to be reliable at current levels, but the industry faces significant challenges to reach ITRS targets for 2006. Moreover, "off-the-roadmap" purity targets set by individual semiconductor manufacturers for specific markets present additional hurdles, especially for gas analysis. This article examines the tradeoffs of APIMS and GC in addressing these challenges.
Experts state that concurrent design and development will play a key role in the success of 10nm lithography technology. Research teams are working on developing disruptive new transistor architectures and materials beyond HKMG and FinFET to enable more energy efficient CMOS scaling and improve upon 10nm lithography technology. Scaling the sub-10nm era will be more challenging, while providing opportunities for unique thinking and approaches within the design ecosystem to achieve these objectives. There is also great potential in wafer-level integration and multiple technologies to achieve these objectives.
A metal oxide semiconductor capacitor (MOSCAP) was used to evaluate the impact of the metal composition and beam line ion implementation on eWF. Ion implantation was performed for some of the samples after high-k dielectric and work function metal deposition on blanket wafers. High frequency capacitance voltage and current voltage measurements were recorded for the MOSCAP samples. A single damascene structure was used to measure sub-20 nanometer line resistance. A planar MOSFET was also used for evaluating impact on VT and variability. Nitrogen ion implantation into the ALD TiAl enabled further WF tuning by 100-150 mV steps.
  • Anon
The three volumes contain 200 papers presented at the conference, 136 of which are indexed separately. The papers deal with techniques, apparatus and applications, and they are grouped under general topics that include the following: eddy currents, ultrasonics, radiography, acoustic emission, nuclear reactors, non-metallic materials, composite materials, welds, manufactured products, extraction and process, imaging techniques, automatic inspection, personnel certification, standards and others.
Standard compound-semiconductor manufacturing techniques, such as lift-off contact metallization and unique epitaxial structures, while viable for low transistor-count applications, have process yield limitations that prevent increased integration of these submicron devices into ever-smaller circuit dimensions. Emerging applications require the adoption of silicon industry standard processes and device structures to enable volume manufacturing of tens of thousands of active compound semiconductor devices in a single circuit with acceptable yield.
Developing 157nm lithography capability in time for production requires the solution to several daunting materials challenges. Among the most difficult of these is finding a suitable 157nm photoresist. The transitions from i-line to DUV and from DUV to 193nm both required development of new materials because the old ones were opaque at the shorter wavelength. Again, researchers are learning that all existing imaging materials were opaque at 157nm and that they must search for materials capable of balancing the requirements of transparency, etch resistance, and developer solubility. Encouraging progress is being made, but much remains to be done in a very short time.
Within the past year, the extension of optical lithography to 157nm has received widespread support because it offers the prospect of improved resolution based on decades of optical lithography experience. This article provides an update on the progress in 157nm, from photoresists to pellicles and exposure tools.
Electrodeposition processes have evolved to achieve increasingly fast bottom-up copper growth in the features, as well as high nucleation densities that protect the thinnest areas of copper seed as the plating process begins [1-3] to take advantage of the improved seed layers in smaller features. This combination of PVD and electroplating has already been extended to fill feature dimensions beyond what was believed possible several years ago, and efforts are now directed toward development of processes capable of filling 1X nm memory structures and 16nm logic interconnects.
Vertical and lateral 193nm resist shrinkage was observed under e-beam exposure using the critical dimension (CD)-scanning electron microscopy (SEM) imaging technique. The diffferent CD changing behaviors for lines, spaces and edge widths were characterized using SEM technique. The critical parameters affecting resist shrinkage in CD-SEM measurements were also identified. It was shown that ArF resist shrinkage is dependent on resist formulation materials, electron beam energy and penetration, electron dose and feature sidewall angle.
A prototype bilayer resist system, based on a silicon-containing methacrylate imageable layer and a crosslinked styrenic copolymer undercoat, shows sub-0.15-μm resolution after 193-nm exposure and O2 etch. The resistance to the substrate-etch plasma is better than current DUV resists. Making bilayer resists feasible for sub-0.18-μm manufacturing requires solutions for some recently identified etch process and materials issues.
A viable resist for ≤100nm design rules is available in time for pilot line development of 193nm lithography. This resist has been optimized for specific device layers by engineering its organic chemistry. Practical application has produced 60nm features using 193nm exposure with phase shift masks and a unique antireflective coating technology that tailors thin-film optical properties.
The introduction of 193nm lithography into 130nm production lines has improved lithographic capability, but has also created significant integration issues at the etch steps. The culprits are inferior etch resistance, reduced mechanical stability of printed features, and a reduction in thickness relative to 248nm resists. The industry is responding with novel integration schemes such as metal hardmasks, new etch chemistries, and pre-etch treatments.
Hybrid optical maskless lithography (HOMA), in which all critical features are images using a maskless template provided by a dense interferometrically generated grating, can be used to enhance the capabilities of 193nm immersion for the 32nm node. The HOMA method is a hybrid combination of high-resolution maskless (optical interferometric) and lower resolution optical projection. Both exposures are capable of very high throughputs. The use of HOMA method for semiconductor lithography can have implications for the design process. All critical features, gates, contacts, and metal will need to be placed on a coarse grid. Coarsegrid restrictions can help simplify the design process by making layouts resolution enhancement techniques (RET)-compliant by construction without requiring complex RET corrections at the end of the design cycle.
Originally slated for 180nm, 193nm lithography will be introduced at the 130nm mode. Still, some manufacturers question the readiness of 193nm for production because of the immaturity of 193nm resists and the scarcity of high-quality CaF2 lenses, which are affecting the availability of production tools. Recent improvements in 193nm resists and CaF2 yields suggest, however, that 193nm can support production lines.
Until recently, the sole measure of a reticle's cleanliness prior to use was inspection. As new mask processes are introduced and exposure wavelengths shrink, the science of cleaning has taken a giant leap forward. Residuals on the mask surface and in the environment around the mask become more relevant: reactions in DUV radiation can be fatal to the reticle's performance. Maskmakers must now be proactive and find ways to verify the robustness of new materials and carefully assess process changes. An investigation focusing on haze formation and accelerated lifetime testing is presented and the relationship between surface and environmental reactions is examined.
Increased lithography cluster tool productivity is required to reduce the cost of ownership (COO) of today's advanced 193nm processes. Coater/developer systems, which make up one half of a lithography cluster, have multiple process steps. Typically, the overall tool throughput is determined by the longest process stage. However, efforts to reduce process times, especially photoresist development, must be made without impact to critical dimension (CD) uniformity and baseline defect levels. A new developer nozzle hardware and process have been developed and evaluated on multiple 193nm photoresists that significantly decrease process time and chemical consumption.
Top-cited authors
Robert Tolles
  • Applied Materials
Masduki Asbari
  • Universitas Insan Pembangunan Indonesia
John H Lau
Dewiana Novitasari
Daniel L. Flamm
  • Microtechnology Law & Analysis (Patent Attorney & Scientist/Engineer)