Microelectronics Reliability

Published by Elsevier
Print ISSN: 0026-2714
Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET using constant voltage stress has been examined by means of a switch matrix technique. As a result, the NAND gate rise time increases by greater than 65%, which may lead to timing errors in high frequency digital circuits. In addition, the NAND gate DC switching point voltage shifts by nearly 11% which may be of consequence for analog or mixed signal applications. Experimental results for the degraded pMOSFET reveal a decrease in drive current by approximately 43%. There is also an increase in threshold voltage by 23%, a decrease in source to drain conductance of 30%, and an increase in channel resistance of about 44%. A linear relationship between the degradation of the pMOSFET channel resistance and the increase in NAND gate rise time is demonstrated, thereby providing experimental evidence of the impact of a single degraded pMOSFET on NAND circuit performance.
A compact model for early electromigration failures in copper dual-damascene interconnects is proposed. The model is based on the combination of a complete void nucleation model together with a simple mechanism of slit void growth under the via. It is demonstrated that the early electromigration lifetime is well described by a simple analytical expression, from where a statistical distribution can be conveniently obtained. Furthermore, it is shown that the simulation results provide a reasonable estimation for the lifetimes.
Electromigration induced failure development in a copper dual-damascene structure with a through silicon via (TSV) located at the cathode end of the line is studied. The resistance change caused by void growth under the TSV and the interconnect lifetime estimation are modeled based on analytical expressions and also investigated with the help of numerical simulations of fully three-dimensional structures. It is shown that, in addition to the high resistance increase caused by a large void, a small void under the TSV can also lead to a significant resistance increase, particularly in the presence of imperfections at the TSV bottom introduced during the fabrication process. As a consequence, electromigration failure in such structures is likely to have bimodal characteristics. The simulation results have indicated that both modes are important to be considered in order to obtain a more precise description of the interconnect lifetime distribution.
A methodology is presented for improved process and circuit development of substrate-pumped nMOS protection. ESD process development is accelerated by applying factor analysis to completed non-ESD experiments. Factor analysis is complimented by a straightforward diagnosis of nMOS snapback. This approach enabled verification of two process solutions, including a novel method, in one fab cycle-time. HBM data that shows the Substrate-Pumped nMOS can provide dramatically higher protection than estimated from conventional I<sub>t2</sub> measurements. This motivates improved ESD circuit development. The nMOS clamp transistor is characterized as an actively biased LNPN, which is how it is used in a Substrate-Pumped protection circuit. A system-oriented approach to circuit development is described that is based upon empirical characterization of well-defined circuit components under conditions approximating ESD.
In this study, three major reliability aspects, hot carrier effects, latch-up and electrostatic discharge (ESD) have been simultaneously studied on a 0.25 μm complementary metal-oxide silicon (CMOS) technology. For this purpose, three source–drain architectures large angle tilted implementation drain (LATID, MDD, Abrupt) processed on different kinds of substrate (bulk and epitaxial ones) are compared with respect to these three reliability aspects. This work clearly demonstrates the dependence existing between them. The source–drain architecture affects, of course, the hot carrier reliability but also the ESD performances. A thinner epitaxial substrate is effective in reducing latch-up occurrences, but degrades the ESD failure threshold. Consequently, global technology optimisation will be a trade off between these various reliability aspects.
This work reports an effective ESD protection circuit design for CMOS IC's by using well-coupled field-oxide device (WCFOD). The bipolar action of the field-oxide device is triggered by well-coupling technique. The ESD-trigger voltage of WCFOD is lowered below the snapback-breakdown voltage of an output transistor, so it can perform efficient ESD protection for output transistors. A 0.5-μm high-speed 256K SRAM product had been fabricated with this proposed well-coupled technique to practically verify the excellent efficiency for output ESD protection. The ESD failure voltage of this SRAM product has been improved up to above 6KV without any extra ESD-Implant process, whereas the original output buffer just can sustain the HBM ESD stress of IKV only.
In this work we describe the resistance changes due to Cu transport and precipitation during electromigration in 0.5 μm wide Al-0.5%Cu lines. A wafer-level, high resolution resistometric technique allowed us to detect significant resistance drops during the initial phase of the electromigration test. TEM microstructural analysis and SEM observations were also performed. Large CuAl2 aggregates were observed in the lines that underwent a high stressing current. The transport and coalescence of Cu atoms explains fairly well the observed resistance drops, that are likely to be due to a decrease of the scattering events associated with tiny precipitates.
F-N injection in NO nitrided gate oxides, grown on n-type 4H-SiC, has been investigated at room temperature and 300°C. The results show that NO nitridation has a positive effect on the Fowler-Nordheim electron injection at high electric fields. The electron injection barrier height is very close to the theoretical value at room temperature. The temperature dependence of the electron injection barrier height is reduced by nitridation
Comparison of (a) transfer characteristic and (b) mobility between the experimental data and simulation with the parameter values listed in Table I.
Subthreshold characteristics of the MOSFET and from SPICE simulations.
In this paper, mobility parameters for n-channel 4H SiC MOSFETs are extracted and implemented into 2D device simulation program and SPICE circuit simulator. The experimental data were obtained from lateral n-channel 4H SiC MOSFET's with nitrided oxide-semiconductor interface, exhibiting normal mobility behavior. The effects of interface-trap density on the model parameters are discussed.
High temperature storage can degrade moulding compounds for chip encapsulation to such an extent that the adhesion to surfaces like copper (lead frames) or polyimide (chip coating) decreases drastically causing delamination. Also during normal operation of electronic components heat is generated locally (bond wire or chip surface) degrading the moulding compound and reducing the adhesion which in extreme cases can destroy the metallisation or the bond wires.
Accelerated life testing is a common way to determine the reliability of devices under use conditions. Typically, parts are aged at different (high) temperatures and the resulting failure times are used to predict the time to failure at use (low) temperature. For semiconductor devices, the failure times often follow a lognormal distribution. In this paper the author considers using the maximum likelihood method in the accelerated life test calculations and shows that it offers an improvement over the least squares method.
Topography and deformation measurements (T.D.M.) under thermomechanical solicitation is a new approach for localising and quantifying deformation of electronic assemblies. Cooling and heating capabilities, with different temperature rate and maximum, following JEDEC thermal profiles for example, have been applied on different components before and after assembly using real time topography and deformation measurements. The interest in being able to perform z and (x, y) deformation measurements for traction/compression and shear stress evaluation will be shown. Using acoustic microscopy before and after thermal stress gives the possibility to detect both the conditions in which elastic limits may have exceeded at interfaces, which interface is concerned and the speed at which delamination occurs. Complementarities of this new technique with acoustic microscopy and simulation will be shown for failure prediction applications.
A study of the electric field dependence of the TDDB activation energy is presented for 12 nm down to 4.7 nm thin oxides. It is shown that the TDDB activation energy depends linearly on the stress electric field and that this behavior depends strongly on the oxide thickness. Moreover, a relationship between the TDDB activation energy attenuation per MV/cm and the oxide thickness has been found. As will be demonstrated, these results are of great importance for the rigorous estimation of the oxide lifetime of both present and future technologies.
The implementation of an analog median filter with a fuzzy adaptation mechanism is discussed. The adaptive median filter is based on transconductance comparators, which saturation current is used to adapt the local weight operator. All the simulations were made using a BSIM3 Level 49 model and 1.5 μm MOSIS technology parameters.
This paper introduces a new distributed active MOSFET rail clamp network that offers surprising advantages in layout area efficiency, bus resistance tolerance, design modularity and ease of reuse. SPICE simulation results using an extended vertical PNP bipolar transistor compact model and a new method for optimizing distributed rail clamp networks are presented along with chip-level test results.
PMOS transistor degradation due to Negative Bias Temperature Instability (NBTI) has proven to be a significant concern to present CMOS technologies. This is of particular concern for analog applications where the ability to match device characteristics to a high precision is critical. Analog circuits use larger than minimum device dimensions to minimize the effects of process variation, leaving PMOS NBTI as a possible performance limiter. This paper examines the effect of PMOS NBTI induced mismatch on analog circuits in a 90nm technology.
Advanced techniques for focused-ion-beam (FIB) device modification have been developed for complex, multistep modifications to circuitry on planar chip technology. Applying gas-assisted etching (GAE) techniques for high-aspect-ratio milling and the selective milling of both conductive and insulating films enhances process latitude. Localized ion-beam-induced deposition of an insulating film provides reconstructive capability in previously modified areas. The application of both techniques for complex device modification of VLSI devices fabricated with CMOS process technology is reviewed.
The gradually increasing complexity of the processing models and necessity to simulate in higher dimensions persistently challenge computational efficiency of the modern process simulators. In this paper, an outlook on the current status and trends in numerical techniques for efficient multidimensional bulk process simulation is given. Grid generation, grid adaptation, discretization and solving techniques are considered as the principle numerical building blocks of modern process simulation tools. The major task and obstacles for each of these numerical segments are recognized and some recently proposed techniques to circumvent current limitations as well as possible directions for future research are discussed
This paper reviews the history of control electronics in both the automotive and aerospace industries, plotting the improvements in reliability as the expectations of customers have increased, and the need for dependability as the functions have become safety critical. The convergence of the requirements of automotive and aerospace electronics are noted, along with similarities and outstanding differences. Cost effective methods of overcoming the differences, and using a common approach to enable mutual advancement are discussed.
This work reports on hot electron reliability of 0.25 μm Alo.25−Ga0.75As/In0.2Ga0.8As/GaAs PHEMTs from the viewpoint of both DC and RF characteristics. The changes of DC and RF behavior after high drain bias stressing are shown to be strongly correlated. Both can be attributed to a decrease of the threshold voltage, yielding different effects on gain depending on the bias point and circuitry chosen for device operation: a fixed current bias scheme is shown to minimize the changes induced by the stress.
We present a detailed study of drain current DLTS spectra performed on as-received and failed AlGaAs/GaAs and AlGaAs/InGaAs HEMT's of four different suppliers submitted to hot-electron tests. We demonstrate that a remarkable correlation exists between DLTS features and permanent and recoverable degradation effects. In particular, different behaviours have been found: (i) recoverable effects seems to be correlated with modulation of charge trapped on DX and ME6 centers. (ii) permanent degradation consisting in a decrease in Id and VT is due to negative charge trapping and is associated with a large increase of a peak having Ea=1.22 eV in the DLTS spectra of failed devices; (iii) development of traps in the gate-to-drain access region induces a permanent increase in drain parasitic resistance Rd and decrease in Id, and is correlated with the growth of a "hole-like" peak in DLTS spectra measured after hot-electron tests.
In this paper techniques are described for coupled simulation of complicated 3-D interconnect and nonlinear transistor drivers and receivers. The approach is based on combining: multipole-accelerated method-of-moments techniques for extracting frequency-dependent inductances and resistances for the interconnect; a sectioning method for fitting the frequency-domain data with a rational function; a balanced-realization approach to reducing the order of the rational function in a guaranteed stable manner; and an implementation of fast recursive convolution to incorporate the rational function in SPICE3. Results are presented to demonstrate some of the frequency-dependent effects in a packaging analysis problem
A key issue in modern microelectronics is to improve and optimise device performance and reliability without excessively increasing fabrication costs. In this paper we will show how it is possible to improve the reliability of single-polysilicon quasi self-aligned BJTs of an advanced O.5μm BiCMOS technology by means of base surface As compensation without any additional mask. By carefully optimising the process parameters it is possible to maintain unchanged the characteristics of the intrinsic transistor compared to the reference one (without compensation) with only a slight increase of the parasitic base resistance, as proven by extensive statistical measurements. Depending on the As dose an increase of the device lifetime by up to four orders of magnitude can be obtained.
Best estimates from the literature of thermal conductivities (k), for various ternary III-V semiconductor alloys and their corresponding compounds
Plots of R th , temperature rise normalized to power per unit area in the emitter, versus baseplate temperature.  
Thermal resistances in InP-based HBTs have been determined by electrical measurement and finite-difference calculation. These devices contain substantial layers of ternary alloys, whose thermal conductivities are not well documented, although they are known to be much smaller than those of the corresponding binary compounds. Therefore a comparison of measurement and calculation gives a valuable check on the thermal conductivities, and is important for validating temperature estimates in a wide variety of HBTs, HEMTs and laser diodes. The measurements employed the V<sub>be</sub>-shift technique, while the calculations employed a high-resolution 3-D nodal network model of the transistor structure, including emitter metal interconnects, and the chip carrier. This was solved iteratively, with the best estimates for thermal conductivities from the literature. Comparisons were made from 25 to 200°C baseplate temperature. At 25°C the measurement and calculation yield temperature rises (normalized to power per unit area) of 31.0 and 28.9°C.μm<sup>2</sup>/mW respectively, i.e. there is agreement to within 7%. At higher temperatures, the calculation is hampered by lack of knowledge of the temperature coefficients (n) for the thermal conductivities of the ternary alloys. So these were all assumed to have the same value, which was used as a fitting parameter. A good fit was obtained with n=1.0. These results suggest that the published thermal conductivity value for Ga<sub>47</sub>In<sub>53</sub>As is accurate to within ±10%, and to first order a GaInAs/AlInAs superlattice can be treated as just two layers of the constituent materials with thermal conductivities equal to the bulk values. Also n=1.0 for these compounds, either separately, or as the net effect for this device structure.
A logical method and approach to a very low percentage failure rate problem for HBT PA products is presented. The value of the IR emission technique coupled with junction breakdown measurements demonstrated the capability to identify a potentially bad HBT cell contained in an array of a few hundred HBT cells. HBT cells with low junction breakdown characteristics are demonstrated to be a potential killer to the whole PA. The cause of low breakdown can be either process or epi-layer defects, as well as by ESD or reverse voltage under certain conditions
This paper reports an ESD internal gate-oxide damage occurred on the digital-analog interface of a mixed-mode CMOS IC. A new ESD protection method is proposed to rescue this internal gate-oxide damage by adding ESD-protection devices on the long metal line between digital-analog interfaces. Experimental verification has confirmed that the IC product can be rescued to pass 2-KV ESD stress from the digital/analog VDD to digital/analog VSS pads without causing any internal damage again. Copyright (C) 1996 Elsevier Science Ltd
The degradation of thin gate oxide is described as the continuous generation of electron traps, until a critical electron trap density is reached, corresponding to the formation of a breakdown path. This process is described statistically resulting in an analytic expression of the intrinsic Weibull distribution as a function of trap density. It can be concluded that the slope of the distribution increases with increasing oxide thickness, because an increasing number of traps is required to form the breakdown path. Also, the critical electron trap density increases with oxide thickness because longer paths have a lower probability of being well oriented to cause breakdown.
The general goal of this work is to get a better insight in the different microstructural processes taking place in blanket Al(Si)(Cu) metallisations under variable conditions. Using analytical transmission electron microscopy and secondary ion mass spectrometry stable theta-CuAl2 precipitates are found distributed inhomogeneously in the z-direction of the metallisation with a peak near the substrate side of the metallisation. Additional heating creates larger theta-CuAl2 precipitates distributed inhomogeneously in the z-direction with a peak near the surface of the metallisation as well as in the vicinity of the substrate. Copyright (C) 1996 Elsevier Science Ltd
An analytical threshold voltage model of NMOSFETs including the effect of hot-carrier-induced interface charges is presented. A step function describing the interface charge distribution along the channel is used to account for the hot carrier induced damage, and a pseudo-2D method is applied to derive the surface potential. The threshold voltage model is then developed by solving the gate-to-source voltage at the onset of surface inversion where the minimum surface potential equals the channel potential. Both the DIBL and body effects are included in the present model as well. Model is successfully verified using simulation data obtained from TCAD (technology-based computer-aided design).
An investigation of interfacial interaction has been performed between an industry oriented epoxy molding compound Epoxy Phenol Novolac (EPN) and its filled variety EPN<sup>F</sup> (with silica particles) and a native silicon dioxide layer (SiO<sub>2</sub>) usually found at chip surfaces. The free surfaces of both solid materials were experimentally analysed by contact angle measurements of three different liquids (water, methylene-iodide (MI) and glycerol). Results are compared to interfacial energies obtained by analysis of the interfaces in bimaterial molecular models, yielding reasonable agreement. A qualitative prediction regarding the influence of water on the interfacial strength between chip and molding compound is attempted.
This work reports some electrical characteristics of ultra-shallow (~90 nm) n<sup>+</sup>p junctions fabricated using plasma immersion implantation of arsenic ions. Both forward and reverse current-voltage (IV) characteristics at operation temperatures ranging from 100 to 450 K were measured. Results show that the ideality factor varies from unity to two indicating both diffusion and GR processes are important in these devices. The ideality factor is found to fluctuate with the temperature, indicating that discrete trap centers exist in these samples. Annealing has a profound effect on the reverse diode characteristics. For fully activated sample, the IV relationship essentially follows a power law, i.e I∝V<sup>m</sup>. The power index m&ap;3 and almost remains unchanged at different temperatures
Studies of solder-bumped flip chip on organic substrates reported in the literature so far suggested the necessity of a polymeric underfill to compensate for the large thermal mismatch between the silicon and the substrate. In our target applications of this process, the underfill not only has to meet the much published mechanical and chemical requirements, it also has to flow through a vertical clearance of 0.020 to 0.0375 mm quickly and also be cured in a relatively short time. Our evaluation of the underfill materials starts with some basic understanding of how the different ingredients in the underfill formulation might affect its physical and chemical properties. The flow characteristics of the underfills have been on first priority in the selection. Then a detailed thermal-mechanical analysis helped us to determine the optimal cure schedule with the desired physical properties. A simple test die/test board system has been designed to evaluate how the underfill might work in a quasi-production process and to allow for our subsequent reliability evaluation. This paper highlights the “pluses and minuses” of the currently available commercial underfills in relation to the optimization of a high-volume production process
Clear relations have been established between E-sort yield and burn-in, EFR and field failure rates for nearly 50 million high volume products in bipolar, CMOS and BICMOS technologies from different waferfabs. The correlations obey a simple model that assumes that the reliability defect density is a fraction of the waferfab defect density and that rootcauses of failures are the same. The model allows a die size independent prediction and assessment of FIT and PPM reliability levels of an IC just based on its yield, eliminating the need for excessive lifetesting. 'Maverick' batches are identified by more than 2 to 3 rejects per batch and can not be eliminated by scrap of low yielding wafers alone. For non-mature technologies only correlations with functional yield are found, the parametric yield loss can be disregarded. Using the results, it is shown how reliability can be improved in a fast and controlled way, even in the 1 digit:FIT and PPM reliability era, by reducing waferfab defect density, elimination of special causes and implementation of screens at product test like voltage screen and Iddq testing. As the effect of yield on PPM reject level is not that strong, the latter approach can be very effective in improving reliability. Copyright (C) 1996 Elsevier Science Ltd
Reproducible back side sample preparation and failure analysis methods becomes increasingly important due to the increasing number of metal levels within semiconductor devices and the ongoing transition to new packages like flip-chip or lead-on-chip. Defects are often located in the lowest chip levels, which make front side electrical defect localization very difficult. Otherwise electrical defect localization in flip-chip and lead-on-chip devices is only possible from the die back side. We developed a failure analysis flow for these die types which contains back side and front side failure analysis methods, consisting of back side photoemission microscopy after bulk Si thinning and electrical recontacting of the die for electrical defect localization. From the type of stress test, test results and fault location, the defect type can often be deduced. With junction leakage, latch up or Al spiking, the die should be prepared for front side analysis, since during further back side preparation, the whole die active area is removed. Gate oxide defects, particles and interrupted conductive interconnects can be analyzed from both the front and back sides of the die. Due to die fragility after bulk Si thinning for electrical defect localization, defect preparation becomes much easier from the back side. After bulk Si removal, optical inspection is possible. Particles or, for example, damage caused by electrostatic overstress might be visible. Gate oxide defects are analyzable by SEM and interrupted conductive interconnects are detectable using passive voltage contrast or electrical probing with AFM
We present a noncontact probing technique for measurement of high-frequency voltage waveforms from the backside of a flip-chip mounted integrated circuit. The signals are accessed by mechanical thinning and focused ion beam milling through the backside. Internal circuit voltages are measured by sensing the local electrostatic force on a small micromachined probe held in close proximity to the circuit measurement point. The instrument currently has a 3 GHz bandwidth and a capacitive loading on the test point of less than 1 fF. The output waveforms from ring oscillator flip-chip test circuits are presented
A model of low-frequency noise in thick-film structures, based on the close relationship of the noise and conduction mechanisms, is presented. The model takes into account the fluctuation of the electron trap during electron transport through the insulating layer by a tunnelling process. Numerical and experimental analyses of the voltage noise spectrum have shown that this noise source influences the level and shape of the noise spectra
In this paper a review is made of the principles and the various applications of charge pumping in submicron MOSFETs. The use of the technique for the analysis of MOSFET degradation, energy and both lateral and vertical spatial profiling of the interface traps is discussed. The role and detection of so-called geometric components is illustrated, and the recently discovered ability of the technique to characterise single interface traps in submicron MOSFETs is demonstrated. Finally, the application of charge pumping in other devices, such as SOI-MOSFETs, EEPROM-cells and power transistors is briefly indicated
Focused ion and electron beams are used for local deposition of conducting or insulating films. Major applications are integrated circuit design edit, prototype modification, repair of masks, and machining of microsystems. In this paper, the dependence of the deposition rates versus the beam parameters for both, ion beam and electron beam induced deposition were investigated and compared with each other. At the same time, a more precise consideration of the influence of secondary electrons on the deposition process was accomplished.
Results are presented on the impact of hot carrier degradation on the low frequency ( ) noise behaviour of p channel MOSFETs. It is found that, in contrast to nMOSFETs, p channel devices exhibit no measurable change in the magnitude of the 1/f noise after severe device degradation at the condition of maximum gate current. The observations have been obtained on a range of device geometries and processes. The degradation results are analysed in conjunction with charge pumping characteristics to explain the insensitivity of the noise to hot carrier degradation in the case of p channel devices. The significance of these results to the performance of p channel devices in analogue applications is discussed.
The work presented in this paper is concerned with the effects of a high temperature gate bias (HTGB) stress on punch-through (PT) and non-punch-through (NPT) insulated gate bipolar transistors (IGBTs). A selection of PT IGBTs and a selection of NPT IGBTs all of the same nominal range were gate biased at their maximum gate-to-emitter voltage with drain and emitter short circuited at 140 °C during 1200 hours. A particular interest was taken in the switching parameters. The turn-on delay time t<sub>don</sub> increases for the PT IGBTs while it decreases for the NPT IGBTs. The switching losses and the rise time increase for the two technologies. The turn-off delay time monotonically decreases for both the PT and NPT IGBTs. The fall time decreases for the PT IGBTs whereas it increases but in a less important way for the other technology. The on state voltage drop increases in both cases and in a more important way for the PT IGBTs. The gale threshold voltage is quiet insensitive to this type of stress for the NPT IGBTs whereas it increases during the first hundred hours of stress and remains unchanged thereafter for the PT IGBTs. The gate leakage current increases strongly for the two technologies while the collector leakage current, such as the threshold voltage, increases to remain constant after some hours of stress for the PT IGBTs.
Top-cited authors
Michael Pecht
  • University of Maryland, College Park
Yi-Shao Lai
  • ASE Group
Mauro Ciappa
  • ETH Zurich
Gaudenzio Meneghesso
  • University of Padova
Enrico Zanoni
  • University of Padova