Filamentous phages are thread-shaped bacterial viruses. Their outer coat is a tube formed by thousands equal copies of the major coat protein pVIII. Libraries of random peptides fused to pVIII domains were used for selection of phages probes specific for a panel of test antigens and biological threat agents. Because the viral carrier in the phage borne bio-selective probes is infective, they can be cloned individually and propagated indefinitely without needs of their chemical synthesis or reconstructing. As a new bioselective material, landscape phages combine unique characteristics of affinity reagents and self assembling proteins. Biorecognition layers formed by the phage-derived probes bind biological agents with high affinity and specificity and generate detectable signals in analytical platforms. The performance of phage-derived materials as biorecognition interface was illustrated by detection of Bacillus anthracis spores and Salmonella typhimurium cells. With further refinement, the phage-derived analytical platforms for detecting and monitoring of numerous threat agents may be developed, since phage interface against any bacteria, virus or toxin may be readily selected from the landscape phage libraries. As an interface in the field-use detectors, they may be superior to antibodies, since they are inexpensive, highly specific and strong binders, resistant to high temperatures and environmental stresses.
A refined technology of SiC p-n junctions is proposed. Usage of boron to compensate the high doping of n layers on structures with different continuous areas is primarily experimentally demonstrated. A comparison between the electrical characteristics of boron compensated and uncompensated diodes is presented. Then a technology using cellular structure for 6H-SiC large area p-n devices is designed and optimized. For these split area structures the micropipes effect is avoided. Based on a matrix structure with 0.16 mm(2) cell area a medium power (600 V breakdown voltage and 1 A at forward voltage of 5 V) p-n diode has been fabricated and tested.
Low-power and very-high-performance 0.25-μm vertical PNP bipolar process is designed and characterized by using the mixed two-dimensional numerical device/circuit simulator (CODECS). This PNP transistor has a 25-nm-wide emitter, a 38-nm-wide base region, a current gain of 17 (without poly-Si emitter effect), and maximum cut-off frequency of 24-GHz. The conventional ECL circuits, designed by this PNP transistor, exhibit an unloaded gate delay of 22-ps at 1.75-mW, and a delay time less than 16-ps/stage for unloaded ECL ring-oscillator
The novel analytical model for the minority carrier transit time has been developed including the recombination effects in both minority-carrier concentration profile and current density distribution. It has been shown that the inclusion of recombination effects is required for the exact modelling of transit time in cases of low effective minority-carrier contact recombination velocities and/or very low lifetime
The influence of strong electric field on an electron emission
from semiconductor surfaces was investigated. We have measured a tunnel
electron emission from the metal to the semiconductor in
metal-insulator-semiconductor heterostructures with a tunnel transparent
insulator layer. A tunnel electron emission from semiconductor tips to
vacuum was also investigated. The using of the semiconductor tip field
emitters gives a possibility to investigate the semiconductor surface at
a especially strong electric field. On the other hand, the investigation
of metal-insulator-semiconductor heterostructures allows to realize the
emission of hot electrons from the metal to the semiconductor, and makes
it possible to create the Auger transistor based on the Al-SiO<sub>2
</sub>-n-Si heterojunctions, which is one of the fastest operating
semiconductor bipolar transistors. The estimations show that
metal-insulator-semiconductor Auger transistor based on solid solution
Ga-In-As-Sb with varying composition makes it possible to increase the
highest operation frequency of Auger transistors up to 5 times compared
with the silicon based Auger transistor and really approaches the
highest frequency to be more then 10<sup>-12</sup>
This paper presents symbolic analysis of Switched-Capacitor (SC) circuits in the z-domain using the Modified Nodal Approach (MNA). The analyses are performed on the SymsimC symbolic simulator, which also enables s-domain network analysis. The results of simulations are demonstrated on practical examples of SC-networks. The influence of finite gain and bandwidth of operational amplifiers on the circuit's behaviour is also examined
This paper presents a comprehensive theoretical study of the Trench Insulated Gate Bipolar Transistors (TEGBT). Specific physical and geometrical effects, such as the accumulation layer injection, increased channel density, increased channel charge and transversal electric field modulation are discussed. The potential advantages of the trench IGBT over its conventional planar variant are highlighted. It is concluded that the trench IGBT is one of the most promising structures in the area of high voltage MOS-controllable switching devices
An integration technique adapted for silicon bipolar technology with full implantation and self-aligned base and emitter contacts is presented. Two high frequency circuits, a Gilbert cell and an amplifier with a bandwidth of 700 MHz that operate from a 2 V supply voltage have been integrated. The circuits content only npn transistors with cutoff frequency between 1.4-16 GHz and BVCBO > 15 V. The amplifier circuit has an adjustable gain range of 10-40 dB (from a command voltage) for a large domain of supply voltages (2-16 V).
The reliability and integrity of HfO2 prepared by direct sputtering of hafnium were studied. By monitoring the current-voltage and current-stressing duration characteristics, we found a significant charge trapping effect in thin film with very short stressing time (< 30 s) but the stress-induced trap generation is insignificant. The breakdown characteristics of hafnium gate oxide were also investigated in detail. We found that several soft breakdowns take place before a hard breakdown. Area and stress-voltage effects of the time-dependent dielectric breakdown were observed. Results suggest that the soft and hard breakdowns should have different precursor defects. A two-layer breakdown model of is proposed to explain these observations.
This paper describes the design and simulation of a new CMOS bridge to frequency converter with gain and offset control. This circuit also includes adjustable operating and centre frequencies. With a balanced bridge, output frequencies from 10.9 kHz to 220 kHz were simulated by varying the capacitor in the active integrator of the VFC circuit. When the gain control frequency was varied between 81 and 172 kHz, the output frequency varied from 28 to 100 kHz. The offset control was simulated for the worse case situation, i.e., the resistors in the bridge were equal to their nominal value plus (or minus) 50 Ω
In this paper, we discuss the application of byte error detecting codes to the design of self-checking circuits for the single stuck-at fault model. We discuss strongly fault-secure realization of a given Boolean function using byte error detecting codes. Even though parity is the most efficient separable code for the detection of single errors, we show that the use of a byte error detecting code can lead to lower cost of self-checking realization of a given function as compared to its self-checking realization using the parity code. We also present a method for the design of totally self-checking checkers for byte error detecting codes. Experimental results obtained for various test circuits are also discussed
The ensemble Monte Carlo simulation is carried out to study effects of the electron pressure term on the mean electron velocity in the GaAs MESFET with a gate length of 0.2 μm. The four components of the mean electron velocity are separately evaluated on the main channel. It is found that the electron pressure component is comparable to the drift one or exceeds it in the low-field drain region. Including the electron pressure component into the drift one produces a large deviation from the Einstein relation and a too large effective mobility of 15000-30000 cm<sup>2</sup>/Vsec. So it is concluded that any device model for the submicron GaAs MESFET should not be based on a drift-diffusion model, but on a model explicitly including the electron pressure term
A new macro-model of a vertical Hall sensor and the corresponding procedure for macro-model parameter extraction are presented. The active volume of the sensor is defined by the process simulation. The modulation effects of the active volume of the sensor and the sources of the non-linearity of the sensor response are examined by means of device simulation. In accordance with the simulation results and measured data a macro-model based on the sensor physics is built. The parameters of this model are extracted from the device simulation data
A nonclassical multi-valued logic based on Post algebra is presented. Besides the conventional Post's cyclic negation, this nonclassical logic algebra defines new operators that simplify the truth-table minimization techniques. An electronic implementation of this algebra for a 3-level logic is proposed. Electronics gates of Post negation and the new operators were designed and simulated using current mode circuits. These gates can be easily interconnected to form flip-flops, counters and other conventional digital gates in a true 3-level gate logic. ASICs with mixed analog/digital high-speed processing can benefit from this current processing ternary logic, which can be easily implemented in bipolar technology
A general method in synthesis and signal arrangement in different pass-transistor network topologies is analyzed. Several pass-transistor logic families have been introduced recently, but no systematic synthesis method is available that takes into account the impact of signal arrangement on circuit performance. In this paper we develop a Karnaugh map based method that can be used to efficiently synthesize pass-transistor logic circuits, which have balanced loads on true and complementary input signals. The method is applied to the generation of basic two-input and three-input logic gates in CPL, DPL and DVL. The method is general and can be extended to synthesize any pass-transistor network.
This paper presents a review of differential and pass-transistor logic used in today's high-performance systems. Various circuit and logic design styles used in contemporary high-performance processors have been reviewed. The new logic is advantageous over standard CMOS in terms of performance and very often in terms of: area, speed and power as well. Evolution of various high-performance latches has been presented
In this work a step by step planar transformer design procedure
for Flyback switch-mode DC-DC converter application is presented. This
transformer has a maximum dimension of 2 cm×2 cm×0.4 cm
aiming to achieve an efficiency of 99% at an operating frequency of 500
kHz. This planar transformer is designed specially for thick film
This paper describes the modelling and simulation of two resolution enhancement techniques in lithography: 1) phase shift mask (PSM) technology and 2) top surface imaging (TSI) with silylation and dry development. The effect of the duty ratio on the image contrast is computed. Simulated one and two dimensional rim shifters and attenuated PSMs are presented. The effect of the aerial image on the silylation profile for the top imaging processes, DESIRE and PRIME, is also presented. The effect of the first etch step on the final resist profiles is examined. The partial pressure and the presence of magnetic fields are also considered
This paper presents the interconnect analysis of the BICMOS and ECL gates, modeled by uniformly distributed Resistance-Capacitance along the wire network for node step voltage. Open and shorted ended responses are analysed. The current and voltage are plotted for lows and high transient time τ=0.0 up to 5. Two Laplace transformations, contour integration, Heaviside theorem, and bisection technique algorithms, are used. The results show that for τ less than 0.1 the responses oscillate around the interconnect length axis having positive and negative values while for τ higher than 0.1 the response is totally positive which is very important criterion during design techniques
A novel BJLD technique is proposed for p-well NMOS PIC
fabrication. Theoretical analysis on the typical structure shows that
VDMOS cells and p-well NMOS ICs can be compatibly integrated in one
chip. Experimental results proved that the BJDL p-n junctions have the
same breakdown properties as the commonly-diffused ones
Theoretically, InP has one of the highest solar energy conversion
efficiencies of any semiconductor material. However, InP wafers are
brittle and expensive which makes large area, single crystal InP device
fabrication difficult. Despite this difficulty, research in InP solar
cells has progressed rapidly over the past 10 years. The reason is high
radiation tolerance. This quality is an essential feature of space power
sources due to the harsh space radiation environment, and InP solar
cells are more radiation resistant than the leading solar cell
technologies, i.e. Si and GaAs. Therefore, InP solar cells are a very
attractive space power source and have been seriously developed as such.
This paper first reviews the chronology of this development and then
takes a focused look at the present understanding of the mechanism of
the radiation response of InP solar cells
In this paper we report the use of silicon bulk micromachining for inexpensive fabrication of miniature silicon springs used as sensing elements in a system for measurement of small moments. Such “torsional microsprings” twist when mechanical moment is applied at the central part of the structure. The springs are designed and fabricated in a way where it is relatively easy to technologically control all geometrical dimensions in micrometer range. Further on, since the spring is made from silicon, the mechanical hysteresis is negligible, which is very important when measuring small moments
This paper gives an overview of CMOS scaling in the range of sub-0.1 μm. Recent advance in the downsizing of MOSFETs by using various new techniques is described. Possible limitation and of MOSFET downsizing is predicted. A future concept of silicon LSIs in the 2010s is discussed.
We examine the effects of device scaling in both vertical and lateral dimensions for the metamorphic high electron mobility transistors (MHEMTs) on the DC and millimeter-wave electrical performances by using a hydrodynamic transport model. The well-calibrated hydrodynamic simulation for the sub-0.1-μm offset Γ-gate In0.53Ga0.47As/In0.52Al0.48As MHEMTs shows a reasonable agreement with the electrical characteristics measured from the fabricated 0.1 μm devices. We have calibrated all the parameters using the measurement data with various physical considerations to take into account the sophisticated carrier transport physics in sub-0.1-μm devices. Being simulated with these calibrated parameters, the optimum device performance is obtained at a source-drain spacing of 2 μm, a gate length of 0.05 μm, a barrier thickness of 10 nm and a channel thickness of 12 nm.
This paper describes the design and experimental characterization of a 0.13 μm CMOS switched-capacitor reconfigurable cascade ΣΔ modulator intended for multi-standard GSM/Bluetooth/UMTS hand-held devices. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt the effective resolution and the output rate to different standard specifications with optimized power dissipation. This is achieved by properly combining different reconfiguration modes that include the variation in the order of the loop filter (3rd- or 4th-order), the clock frequency (40 or 80 MHz), the internal quantization (1 or 2 bits), and the bias currents of the amplifiers. The selection of the modulator topology and the design of its building blocks are based on a top-down CAD methodology that combines simulation and statistical optimization at different levels of the modulator hierarchy. Experimental measurements show a correct operation of the prototype for the three standards, featuring dynamic ranges of 83.8/75.9/58.7 dB and peak signal-to-(noise+distortion) ratios of 78.7/71.3/53.7 dB at 400 ksps/2/8 Msps, respectively. The modulator power consumption is 23.9/24.5/44.5 mW, of which 9.7/10/24.8 mW are dissipated in the analog circuitry. The multi-mode ΣΔ prototype shows an overall performance that is competitive with the current state of the art.1
The effects of varying both the Shallow Trench Isolation's (STI) dimension and geometrical spacings on latchup behavior for 0.18-μm cobalt silicided CMOS test structures were investigated. The as-developed characterization techniques and models aid in the optimization of device layout. The test data extracted for both the parasitic current gains and parasitic resistances over a range of layout dimensions were analyzed and modeled. The influence of biasing voltages on latchup reliability was also studied.
Nonideal factors which play a key role in performance and yield in high-precision operational amplifiers are rigorously investigated. Expressions for the offset voltage (Vos) and the common-mode rejection ratio (CMRR) are derived and correlated. The mismatch accuracy is analyzed for different transistor geometries in a CMOS OTA (operational transconductance amplifier) in 0.35 μm technology by using the Monte Carlo approach.
This work presents the design of LDMOS transistors fully compatible with a standard CMOS process, only requiring mask layout manipulation. A conventional 0.35 μm CMOS process was elected to demonstrate the viability of the approach. The prototyped LDMOS transistor exhibits a breakdown voltage of 24 V, which represents an improvement of 31% when compared with the high-voltage extended-drain NMOS available in the process library, while other static parameters remain in the same range. Furthermore, this solution enables the CMOS integration of a high-voltage pass-transistor, as a consequence of the formation of an isolated lightly doped p-type region inside the n-well.
In this paper, an integrated 2.2–5.7 GHz multi-band differential LC VCO for multi-standard wireless communication systems was designed utilizing 0.35 μm SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post-layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3 V for 5 different frequency bands (2.27–2.51 GHz, 2.48–2.78 GHz, 3.22–3.53 GHz, 3.48–3.91 GHz and 4.528–5.7 GHz) with a maximum bandwidth of 1.36 GHz and a minimum bandwidth of 300 MHz. The designed and simulated VCO can generate a differential output power between 0.992 and −6.087 dBm with an average power consumption of 44.21 mW including the buffers. The average second and third harmonics level were obtained as −37.21 and −47.6 dBm, respectively. The phase noise between −110.45 and −122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between −176.48 and −181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment. Output power of the fundamental frequency changes between −6.087 and 0.992 dBm, depending on the bias conditions (operating bands). Based on the post-layout simulation results, the core VCO circuit draws a current between 2.4–6.3 mA and between 11.4 and 15.3 mA with the buffer circuit from 3.3 V supply. The circuit occupies an area of 1.477 mm2 on Si substrate, including DC, digital and RF pads.
This paper describes a 0.6 micron triple level interconnect scheme for ASIC application. This interconnect scheme has been used with 0.6 micron twin well CMOS technology having polycide gates. Excellent planarization of BPSG films was achieved at a low reflow temperature by using TEOS/03-based APCVD BPSG. Sandwich layers of TiW/Al-1%Cu/TiW were used for interconnects. A void-free Inter-Metal-Oxide (IMO) planarization with good device reliability was achieved using a combination of silicon-rich silane-based PECVD oxide, TEOS-based PECVD oxide and SOG etchback process. In order to achieve the maximum packing density, metal 3 is used as a routing layer and has the same pitch as metal 1 and metal 2 layers. It has been demonstrated that the device and the interconnect reliabilities for this metallization scheme are excellent.
We present a high-frequency fully-differential current-mode buffer to interface off-chip currents with no significant degradation of the frequency response, and to measure current-mode ICs using standard equipment. It has been fabricated in a 0.8 μm double-poly double-metal CMOS technology and features more than 37 MHz bandwidth. In order to show its functionality, this unit has been incorporated to the front end of a switched-current bandpass ΣΔ modulator featuring a 9 bit dynamic range at 10 MHz clock frequency for a 30 kHz signal bandwidth centred at 2.5 MHz.
This paper discusses the design and implementation of a monolithic IGBT gate driver for intelligent power modules (IPMs). The objective of this work is to design and implement a monolithic IGBT gate driver IC with efficient protection functions in a high-voltage (50 V) 0.8-μm CMOS process. The gate driver is designed for medium power applications, such as home appliances. It includes low-voltage logic, 5-V logic regulator, analog control circuitry, high-voltage (50 V) high-current output drivers, and protection circuitry.
A new type of (Ga,Mn)As microstructures with laterally confined electronic and magnetic properties has been realized by growing (Ga,Mn)As films on [1-10]-oriented ridge structures with (113)A sidewalls and (001) top layers prepared on GaAs(001) substrates. The temperature- and field-dependent magnetotransport data of the overgrown structures are compared with those obtained from planar reference samples revealing the coexistence of electronic and magnetic properties specific for (001) and (113)A (Ga,Mn)As on a single sample.
Precise lattice parameter measurements in single crystals are achievable, in principle, by X-ray multiple diffraction (MD) experiments. Tiny sample misalignments can compromise systematic usage of MD in studies where accuracy is an important issue. In this work, theoretical treatment and experimental methods for correcting residual misalignment errors are presented and applied to probe the induced strain of buried InAs quantum dots on GaAs (001) substrates.
By investigating the morphological evolution during epitaxial growth of Ge on Si(0 0 1) substrates, we find that highly uniform distributions of islands can be obtained. The islands are no longer domes but they consist of barns, which are bounded by steeper facets. A detailed morphological analysis indicates the presence of facets at their base, which are not stable for Ge but for Si. Finally, we show that long-range ordering of highly uniform SiGe barns can be obtained when the growth is performed on patterned Si(0 0 1) substrates.
The growth of InAs on GaAs(0 0 1) is of great interest primarily due to the self-assembly of arrays of quantum dots (QDs) with excellent opto-electronic properties. However, a basic understanding of their spontaneous formation is lacking. Advanced experimental methods are required to probe these nanostructures dynamically in order to elucidate their growth mechanism. Scanning tunneling microscopy (STM) has been successfully applied to many GaAs-based materials grown by molecular beam epitaxy (MBE). Typical STM–MBE experiments involve quenching the sample and transferring it to a remote STM chamber under arsenic-free ultra-high vacuum. In the case of GaAs-based materials grown at substrate temperatures of 400–600 °C, operating the STM at room temperature ensures that the surface is essentially static on the time scale of STM imaging. To attempt dynamic experiments requires a system in which STM and MBE are incorporated into one unit in order to scan in situ during growth. Here, we discuss in situ STM results from just such a system, covering both QDs and the dynamics of the wetting layer.
A compact temperature sensor using lateral p-n-p bipolar transistors has been fabricated and tested in a standard 1.0 μm digital n-well CNIOS process. Like their n-p-n counterparts in p-well processes, these lateral p-n-p devices exhibit good lateral β. The accuracy of the temperature sensor is close to the performances obtained in bipolar technology, an output proportional to absolute temperature is obtained (0.54mV/K) from 0 to +70°C, although the sensor can be used in wide-ranging applications after curvature correction. The device has an area of only 0.018 mm2.
A current-mode true RMS–DC converter based on a novel synthesis of translinear loop squarer/divider and simplified current-mode low-pass filter is presented. The circuit employs floating gate MOSFETs that operate in strong inverted saturation region for electronically simulated translinear loop. The converter features very low supply voltage (1.2 V), two-quadrant input current, immunity from body effect, low circuit complexity, and wide input dynamic range. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.
We propose a novel laser active region design that employs a strained and ordered ([nAs)1(GaAs)1 quantum well on a GaAs(111)B substrate for 1.31 μm high-speed applications. The increased Matthevvs-Blakeslee critical thickness for this orientation as compared to the (001) case allows for wider wells with higher indium compositions. In the In0.5Ga4.5As case, however, the bandgap is not significantly affected by the reduced quantum confinement because an increase in the hydrostatic strain component of the Hamiltonian for the (111)-orientation approximately negates any narrowing effects. By using an alternate monolayer superlattice active region to replace the alloy, we find that wavelengths well beyond 1.3 μm can be achieved. We also discuss some of the adBANtages of moving to the (111)-orientation that indicate higher modulation bandwidths are possible using this material system over conventional 1.3 μm laser diodes on InP substrates.
Uncapped InAs/GaAs quantum dots with average height around 15 nm were grown under the regime of ultra-low growth rates (<0.01 ML/s). When GaAs capped, such structures exhibited room-temperature luminescence in the 1.1–1.4 μm range. The effect of phonon bottleneck was not observed and the presence of multiple peaks in the photoluminescence spectra was caused by state filling, as observed in measurements as a function of the excitation-power density. A carrier dynamics that involved thermal emission of carriers into the GaAs barrier and recapture by the quantum dots was observed when the optical emissions were monitored at different temperatures.
We propose the growth of thick ‘spacer’ layers (d) for high-quality 10-stack InAs/GaAs quantum dots (QDs) emitting at 1.23 μm without the use of strain reduction layers (SRLs). All samples were grown using molecular beam epitaxy (MBE) and extensively characterised using X-ray diffraction, optical spectroscopy and microscopy techniques. We demonstrate that for d<50 nm, large ‘volcano-like’ defects are formed at the top of the stacked structure, while for d=50 nm, these features were not observed. The process of suppressing these abnormal defects has resulted in significant photoluminescence (PL) enhancement, paving the way for the realisation of defect-free QD laser devices.
We present a pure CMOS bandgap voltage reference with a low quiescent current and high output current driving capability. The circuit sources a driving current of up to 1.5 mA with the reference voltage kept above 98.5% of its designated 1.2 V, and up to 6 mA before the voltage drops to 90%. The circuit achieves a very low supply current of , a low power of , a line regulation of and a load regulation of . The reference is implemented in a pure CMOS process with at using substrate pnp. A startup circuit, which shuts down itself after a controlled delay using Miller effect, is also introduced. By utilizing the body effect of the input transistors, the turn-on threshold of the startup circuit is raised to about 1 V, making it a perfect match for the reference architecture. Silicon measurements are in good agreement with simulations.
Photoluminescence measurements were carried out to investigate the origin of long wavelength emissions (∼1.6 μm at room temperature) observed from wafers with InAs quantum dots capped with GaAsSb layers. For wafers with high Sb content (22% and 26%) photoluminescence peak energies were found to be linearly proportional to third root of optical excitation power, a characteristic of emission due to a type-II band alignment. This work therefore presents unambiguous evidence that the long wavelength emission of the wafers comes from type-II band alignment between the InAs quantum dots and the GaAsSb capping layers.
900 MHz CDMA, 1.8 GHz PCS, and 450 MHz CDMA RF receivers are implemented and measured. In order to reduce NRE cost and meet the demand of fast time-to-market, a metal-mask configurable method is applied for those receivers using only upper metals, contact and via layers. Also to reduce power consumption, a new mixer linearization method is proposed, along with an optimization methodology of an integrated inductor for a single balance mixer LO buffer, with respect to power consumption and silicon area. In order to apply the proposed inductor optimization methodology into metal-mask configurable circuits, inductor design considerations for metal-mask variant circuits are presented. With the proposed linearization technique and inductor optimization method, low power 900 MHz CDMA/1.8 GHz PCS/450 MHz CDMA mixers are obtained. The proposed receivers are fabricated in a 0.35 μm SiGe BiCMOS process. In the 900 MHz CDMA case, measurement results of the proposed mixer show 12 dBm IIP3 and 10.2 dB conversion gain, and 7.5 dB SSB NF with 10.5 mA current consumption at 2.7 V supply voltage.
The electrical and photoelectrical properties of long wavelength Hg1−xCdxTe structures have been optimized by using an exact numerical analysis. In this analysis we have been taking into account the degeneracy, non-parabolicty, deviation from thermodynamical equilibrium and graded interfaces. The band diagram, electrical field, carrier mobility, photoelectrical gain, responsivity, noise and detectivity have been calculated and optimized as a function of different variable such as alloy composition, doping concentration, thickness, and applied voltage to obtain optimized performance at room temperature. This numerical simulation can be used to optimize the mentioned parameters for other structures such as , operating in photodiode, or photovoltaic mode.
A systematic design approach for low-power 10-bit, 100 MS/s pipelined analog-to-digital converter (ADC) is presented. At architectural level various per-stage-resolution are analyzed and most suitable architecture is selected for designing 10-bit, 100 MS/s pipeline ADC. At Circuit level a modified wide-bandwidth and high-gain two-stage operational transconductance amplifier (OTA) proposed in this work is used in track-and-hold amplifier (THA) and multiplying digital-to-analog converter (MDAC) sections, to reduce power consumption and thermal noise contribution by the ADC. The signal swing of the analog functional blocks (THA and MDAC sections) is allowed to exceed the supply voltage (1.8 V), which further increases the dynamic range of the circuit. Charge-sharing comparator is proposed in this work, which reduces the dynamic power dissipation and kickback noise of the comparator circuit. The bootstrap technique and bottom plate sampling technique is employed in THA and MDAC sections to reduce the nonlinearity error associated with the input signal resulting in a signal-to-noise-distortion ratio of 58.72/57.57 dB at 2 MHz/Nyquist frequency, respectively. The maximum differential nonlinearity (DNL) is +0.6167/−0.3151 LSB and the maximum integral nonlinearity (INL) is +0.4271/−0.4712 LSB. The dynamic range of the ADC is 58.72 dB for full-scale input signal at 2 MHz input frequency. The ADC consumes 52.6 mW at 100 MS/s sampling rate. The circuit is implemented using UMC-180 nm digital CMOS technology.
Heat conduction in integrated circuits spans length scales across several orders of magnitude: From the lattice spacing at a few Angstroms to the substrate thickness at hundreds of micrometers. The smaller length scale becomes increasingly important in devices with feature size well below 100 nm. This paper provides an overview of sub-continuum electro-thermal transport. We use the phonon Boltzmann transport equation to model heat conduction in the device and show that phonons emitted by hot electrons in the drain create a phonon hotspot. The resulting non-equilibrium leads to increased thermal resistance within the device. At the limits of scaling, the resistance is comparable to that due to the substrate and packaging.
Growth of GaAs by molecular beam epitaxy on (110) substrates vicinal to (111)A has been systematically studied by atomic force and Nomarski microscopy at different As/Ga flux ratios, substrate temperatures and growth rates. Depending on the growth conditions, a striking variety of morphological instabilities have been found that range from step bunching in the Ga-supply limited regime to creation of long-range, well-ordered patterns of three-dimensional pyramidal features on the surface under As-deficient conditions. We discuss the microscopic origin of the morphological instabilities and self-organization of the surface features in terms of growth modes, relative adatom populations and step-attachment probabilities.
The MBE double-growth technique that we call cleaved-edge overgrowth has, over the past several years, proved itself to be especially suitable for making quantum wires of the very highest quality. We will review our recent progress in measuring the transport and quantum optics characteristics of these wires, and the MBE growth issues that arise with cleaved-edge overgrowth fabrication. Our transport experiments have resulted in 250 Å wide quantum wires with ballistic mean free paths exceeding 10 μm. We verify the prediction that in the ballistic regime the electron conductivity in a quantum wire is independent of the wire length and shows quantized steps proportional to . The deviation of our observed step heights from exactly is taken as evidence for correlated electron behaviour. The electrons are tightly confined on three sides by atomically smooth GaAs/AlGaAs heterojunctions and in the fourth direction by an electric field. This results in a quantum wire of nominal square cross-section . Magneto-transport measurements reveal quantum wire sub-band separations in excess of 20 meV as well as the symmetries of the wave functions of the one-dimensional modes. For optics studies our quantum wires are made using cleaved-edge overgrowth to form a line junction as two quantum wells are made to intersect with the cross-section forming a letter ‘T’. This line intersection separately forms a quantum wire bound-state for holes, for electrons, and even for excitons. We have characterized our optical wires by PL, by PLE, and by scanning near-field optics. An important application of this work is our demonstration of the first quantum laser using this T-geometry.
An improved quality of (110) GaAs has been grown by molecular beam epitaxy using As2 in lieu of As4. The most pronounced effect of using As2 is a higher doping efficiency of Si δ-doped GaAs layers, resulting in a mobility of the (110) layers, comparable to the reference (100) samples.The high quality of the (110) GaAs was confirmed by low temperature photoluminescence. The spectrum of the GaAs layer shows a single dominant free exciton line with a linewidth of 1.0 meV.