Microelectronic Engineering

Published by Elsevier
Print ISSN: 0167-9317
Publications
Direct and fast (10s of seconds) deposition of flame-made, high surface-area aerosol films on polymers and polymeric microfluidic devices is demonstrated. Uniform TiO2 nanoparticle films were deposited on cooled Poly(methyl methacrylate) (PMMA) substrates by combustion of titanium(IV) isopropoxide (TTIP) - xylene solution sprays. Films were mechanically stabilized by in-situ annealing with a xylene spray flame. Plasma-etched microfluidic chromatography columns, comprising parallel microchannels were also coated with such nanoparticle films without any microchannel deformation. These microcolumns were successfully used in metal-oxide affinity chromatography (MOAC) to selectively trap phosphopeptides on these high surface-area nanostructured films. The chips had a high capacity retaining 1.2 μg of standard phosphopeptide. A new extremely fast method is developed for MOAC microchip stationary phase fabrication with applications in proteomics.
 
Schottky barrier SOI-MOSFETs incorporating a La(2)O(3)/ZrO(2) high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N'-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 10(11) eV(-1) cm(-2), a low subthreshold slope of 70-80 mV/decade, and an I(ON)/I(OFF) current ratio greater than 2 × 10(6) are obtained.
 
In this work the direct transfer of nanopatterns into titanium is demonstrated. The nanofeatures are imprinted at room temperature using diamond stamps in a single step. We also show that the imprint properties of the titanium surface can be altered by anodisation yielding a significant reduction in the required imprint force for pattern transfer. The anodisation process is also utilised for curved titanium surfaces where a reduced imprint force is preferable to avoid sample deformation and damage. We finally demonstrate that our process can be applied directly to titanium rods.
 
We present and demonstrate a novel fabrication method to integrate metallic nanostructures into fluidic systems, using nanoimprint lithography and lift-off on a compositional resist stack, which consists of multi-layers of SiO(2) and polymer patterned from different fabrication steps. The lift-off of the stack allows the final nano-features precisely aligned in the proper locations inside fluidic channels. The method provides high-throughput low-cost patterning and compatibility with various fluidic channel designs, and will be useful for fluorescence and Raman scattering enhancement in nano-fluidic systems.
 
Electrodeposition of ferromagnetic metals, a common method to fabricate magnetic nanostructures, is used for the incorporation of Ni structures into the pores of porous silicon templates. The porous silicon is fabricated in various morphologies with average pore-diameters between 40 and 95 nm and concomitant pore-distances between 60 and 40 nm. The metal nanostructures are deposited with different geometries as spheres, ellipsoids or wires influenced by the deposition process parameters. Furthermore small Ni-particles with diameters between 3 and 6 nm can be deposited on the walls of the porous silicon template forming a metal tube. Analysis of this tube-like arrangement by transmission electron microscopy (TEM) shows that the distribution of the Ni-particles is quite narrow, which means that the distance between the particles is smaller than 10 nm. Such a close arrangement of the Ni-particles assures magnetic interactions between them. Due to their size these small Ni-particles are superparamagnetic but dipolar coupling between them results in a ferromagnetic behavior of the whole system. Thus a semiconducting/ferromagnetic hybrid material with a broad range of magnetic properties can be fabricated. Furthermore this composite is an interesting candidate for silicon based applications and the compatibility with today's process technology.
 
Silicon direct bonding (SDB) has been used to produce silicon-on-insulator (SOI) substrates for dielectrically isolated power devices. The up-drain VDMOS transistors give a low specific on-resistance and allow multiple isolated outputs. The CMOS devices have down to 2 ¿m drawn channel lengths, here used in a channelless sea of gates semicustom array. The vertical NPN and lateral PNP transistors show characteristics comparable to those of a 60 V bipolar process and make advanced analogue functions possible. The presented process allows fabrication of a 2 A half-bridge circuit with integrated drivers and logic functions.
 
The epitaxial CoSi<sub>2</sub> formation on Si(100) by Co/Ti bilayers through solid phase epitaxy is well known. The surface layer consists of TiN or CoTi<sub>x</sub>Si<sub>y</sub>, depending on the experimental conditions. The role of the barrier layer is to reduce the natural oxide and to limit the flux of the Co atoms into the Si substrate. Several other metals, as Cr, V, Ta and Zr have been used as a barrier layer. We investigated Hf as barrier material in comparison with Ti and Zr barriers. All these materials are able to reduce the natural oxide on silicon
 
We report the design, fabrication and characterization of thermomechanical microtransducers realized by industrial IC CMOS technology combined with subsequent maskless anisotropic wet etching. Examples include a thermally excited beam resonator, resistive and thermoelectric gas flow sensors, and a thermoelectric power sensor.
 
We review the present status of compound semiconductor device simulations. Some scaling techniques are discussed for the simulation of abrupt heterojunctions. An example illustrates the method.
 
Continuous down scaling of the interconnect dimensions led to the introduction of copper and low-k dielectric materials. The use of such materials is challenging in the field of mechanical reliability, such as stress-induced voiding in copper interconnects and cracking of low-k dielectrics. Up to now these two failure modes were investigated separately. However, recent experimental observations tend to demonstrate the possibility of a complex interaction of both failure modes, one overwhelming or enhancing the other. In this paper a comparison of the risk of void or crack occurrence is made by the mean of finite element modelling. Further, the interaction between these two failure modes (voiding and cracking) is also studied
 
The use of hybrid integration schemes is investigated using a combination of a SiOC film at the via level and a porous SiLK Y film at the trench level. Sequential finite element analysis is used to determine the mechanics and, subsequently, a hybrid damascene interconnect is built to demonstrate the approach.
 
Nitridation treatments are generally used to enhance the thermal stability and reliability of high-k dielectric. It is observed in this work that, the electrical characteristics of high-k gated MOS devices can be significantly improved by a nitridation treatment using plasma immersion ion implantation (Pill). Equivalent oxide thickness, (EOT) and interface trap density of MOS devices are reduced by a proper PIII treatment. At an identical EOT, the leakage current of devices with Pill nitridation can be reduced by about three orders of magnitude. The optimal process conditions for Pill treatment include nitrogen incorporation through metal gate, ion energy of 2.5 keV, and implantation time of 15 min.
 
Aluminum and some of its alloys are commonly used as metallization for silicon integrated circuits. Due to miniaturization, the critical dimensions of metallization such as line width, contact or via area in ULSI devices, are now approaching the size of a grain in the polycrystalline Al film. Particularly unwanted are hillocks i.e. large grains that outgrow above the initial Al surface. It is generally accepted that hillock growth is related to plastic flow and grain boundary diffusion where the supply of atoms takes place at the bottom of the hillock. The aim of this work is to investigate the possibilities of reduction of the density and/or the size of the hillocks by introducing into the metallization adequate barriers suppressing the grain boundary diffusion
 
For millimeter-wave bands, achieving a very small gate length and an extremely low gate resistance is arguably the single most important technology in manufacturing power GaAs-based pseudomorphic high electron mobility transistor (PHEMT) devices with the properties of high power, high reliability, high throughput and low noise. In order to obtain maximum speed performance from a PHEMT, it is not sufficient to simply use higher mobility materials or structures, it is also necessary to minimize the parasitic resistance (gate resistance and source and drain ohmic contact resistances) and device capacitances if the full potential of the high-speed performance and low minimum noise are to be obtained. To minimize these parameters, the fabrication technologies used are electron beam double exposure with resists of a trilayer structure consisting of PMMA/P(MMA–MAA)/PMMA and a double recess with a volume ratio of mixed solutions (50% citric acid/H2O2/H2O, 1:3:1). The best fmax performance is, however, expected by combining the offset-gate advantages with small gate–source spacing. Our group has manufactured a 0.1 μm scale Γ-gate with a small gate length by offsetting the gate to source and with a large gate cross section using electron beam lithography for optimization. In this work we report the fabrication of devices of 70 μm unit gate width and two gate fingers with a drain–source saturation current density of 450 mA/mm, an extrinsic transconductance (Gm) of 363.6 mS/mm, a current-gain-cutoff frequency (fT) as high as 106 GHz and a maximum oscillation frequency (fmax) of 160 GHz.
 
This paper describes hot-carrier-induced, abnormal gm degradation in 0.04-μm-channel nMOSFETs/SIMOX, which is not easily predicted, and its physical background. The discussion includes device simulations showing that the LDS/LDD structure plays a significant role in the abnormal gm degradation. Accordingly, the single-drain structure is strongly recommended for sub-0.1-μm-channel nMOSFETs/SOI.
 
A comparative study has been performed between AlGaAs/GaAs MODFETs and AlGaAs/InGaAs/GaAs pseudomorphic MODFETS with gate lengths down to 0.1 μm. The structure features a nm-T-gate lithography of high aspect ratio. The electrical analysis focuses on the FET's unity current gain fT. Maximum fT's were 113 GHz for the 0.1 μm MODFET, and 115 GHz for the 0.13μm pseudomorphic MODFET. For comparable gate lengths the In0.2Ga0.8As quantum well transistors had higher cut-off frequencies due to a higher effective electron velocity of vS = 1.24×107cm/s as compared to vS = 1.0×107cm/s for the GaAs channel transistors.
 
The FSG (fluorine-doped silicon glass) was introduced as dielectric for copper interconnects in order to take advantage of its lower dielectric constant. With a gain of 18% in the constant value, it makes the shrink of metal dimension possible for 0.12-μm technology devices with limited cross-talks or delays in the information transmission. In spite of its strong sensitivity to water and moisture absorption, we could integrate this material in the dual damascene structure for copper application for 0.12-μm technology. The use of appropriate capping layer and optimisation of fluorine content made the integration possible with optimal dielectric properties.
 
The hot-carrier degradation induced by first- and second-impact ionization events is compared in advanced N-MOSFETs used for digital applications with a 3.2-nm gate-oxide thickness. Results show that the substrate enhanced electron injection (SEEI) mechanism is still increased in 0.15-μm channel length devices with p-pockets and shallow drain junctions with a measured much higher injection efficiency than that in older technologies. The enhancement of the gate current originates from tunneling contributions and from the secondary–primary-hot electron currents at low energy. The induced damage is explained solely by the interface trap generation and mobility reduction in 3.2-nm thick gate-oxide devices. The difference between first and second hot-carrier damage is related to the extension of the degraded region toward the source. This is in contrast to thicker gate-oxide N-devices where the SEEI effect is weak and where the electron trapping extends from the gate-drain overlap region toward the source in addition to the generated interface traps.
 
Deep-UV lithography using 248 and 193-nm light will likely be the microlithography technology of choice for the manufacture of advanced memory and logic semiconductor devices for the next decade. Since 193nm lithography development has been slow, the extension of 248nm technology to 150nm and beyond is required. Advanced techniques, such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) will be needed in order to maintain sufficient process latitude.This paper will discuss recent work to investigate the capability of 248nm lithography at 150nm. Imaging results using conventional and off-axis illumination (OAI) will be presented. Key resist performance parameters will be discussed, including process latitude, linewidth and line length control and full field critical dimension (CD) control. Although the performance appears to be adequate for early process and device development, further enhancements will be required for a manufacturable process at 150nm.
 
Various methods of copper filling are studied as interconnect metallizations in advanced ultra large scale integration (ULSI) devices. The filling mode comprising organometallic chemical vapor deposition (OMCVD) Cu followed by physical vapor deposition (PVD) Cu reflow for 0.3 μm diameter trench and via filling has been investigated. This paper presents an evaluation of both the long-throw PVD copper, and CVD copper fundamental process steps. The excellent step coverage of CVD Cu as a seed layer is presented. The corresponding initial PVD Cu deposition step requires a low DC power to facilitate Cu reflow before creating the characteristic overhang of the PVD process, which in turn facilitates subsequent void formation. So the PVD DC power was optimised at 1.6 kW. Furthermore, the full sequential integration of the CVD and PVD process was investigated as a function of liner thickness, deposition temperature and DC power. The filling process has been optimised with a relatively thick liner, to avoid dewetting on the TaN barrier, and with a high deposition temperature to obtain sufficient reflow. However, a thin PVD Cu ‘flash’ layer was necessary to resolve interface stability issues between CVD Cu and TaN. Electrical results are compared to those from a standard copper process flow and these first results are 15% higher than with a standard copper metallization.
 
A comprehensive approach based on TCAD and statistical methods has been demonstrated for deep submicron SOI CMOS process optimization and manufacturing sensitivity analysis. Second-order response surface models were fitted to ten device characteristics based on 15 processing conditions identified as significantly affecting the CMOS process. The optimized 0.18 μm SOI CMOS process, representative of deep submicron SOI technology currently under consideration by industry, was determined by numerical analysis of the generated models. A two part sensitivity analysis was then conducted for the optimized process. A Monte Carlo analysis technique was applied to a set of reduced response models to determine the sensitivity of the device characteristics to some anticipated manufacturing process random variations. Results for a 0.18 μm PD SOI CMOS technology are presented, providing optimized process conditions meeting desired device performance measures, and indicating no conspicuous device performance degradation by anticipated manufacturing process variations.
 
A key challenge for 0.18 μm technology is the interconnect RC delay, which is the limiting factor for device performance. This delay can be reduced by the use of a low-k dielectric and copper. Some of the difficulties of integrating these interconnects are discussed, and a new strategy for post dielectric etch cleaning is presented.
 
In this paper, various contributions to the reflection variation at the resist/BARL interface are investigated. Not only deviations in the optical parameters (n, k, thickness T) of the BARL are causing variations in reflectivity, but also thickness variations of transparent layers underneath the BARL. Furthermore, the impact of substrate reflectivity on CD variation for 0.2μm features is investigated, using various SiON layers. Since substrate reflectivity has to be very low for good CD control, and since some reflectivity variations can be unavoidable, the use of a TAR layer in combination with BARL is proposed as a simple solution to maintain good CD control on real product wafers.
 
In this work, the phase formation is compared for Ni- and Co-silicidation with and without Ti cap. In addition, the electrical performance of Ni-silicidation with and without Ti-cap is investigated and compared to the performance of a Co-silicidation process with a Ti cap that has the same Si consumption. The lateral confinement of the silicide in the active areas is also studied.
 
A new generation of interconnect schemes is required for high performance ULSI. This involves developing process modules aimed at reducing RC delay and power consumption, as well as developing new equipment technology to support these processes. In the materials area, the most significant challenge is to define a workable and reliable combination of high conductivity metals (Al(Cu), Cu) with a low dielectric constant insulator (starting with fluorinated silicon oxide). As far as processing is concerned, the key technological issues that we will address in this paper are (i) etching dielectrics and metals with high aspect ratio (4:1 for contact/via and greater than 1.5:1 for lines/trenches) and (ii) filling these aggressive topologies using dielectric films with high gap-filling capabilities and conformal/planarizing CVD and PVD metal deposition. Besides the option of using SiOF dielectric and oxide CMP, four process modules of interconnects can be highlighted: (1) gap-fill oxide/W interconnect and/or via plug/metal etch; (2) gap-fill oxide/via fill and planarized Al/metal etch; (3) metal plug/metal damascene; and (4) Cu dual damascene. Since time-to-market will still be very critical for fabrication at 0.25 μm technology, typically for 200 mm and 300 mm wafers, the challenge is clearly to achieve successful vertical and horizontal integration of these modules. As a result, more than ever, suppliers and chip manufacturers have to work very closely at early stages of technology development. Examples of joint development programs leading to new breakthroughs in technology and reactor design will be discussed.
 
Lead–magnesium niobate–lead titanate (PMN–PT) thin films with and without the TiO2 seed layer were deposited on Pt/Ti/SiO2/Si substrates through pulsed laser deposition. The study aimed to characterize the effect of the TiO2 seed layer on the phase composition and properties of PMN–PT film. Without the TiO2 seed layer, the pure perovskite phase could be obtained in the thinner PMN–PT film while with the TiO2 seed layer, the pure perovskite phase was formed in the thicker PMN–PT film. The ferroelectric properties of PMN–PT films with the TiO2 seed layer were exhibited. As a result, the maximum amount of remnant polarization reached the amount of 32 μC/cm2 for the PMN–PT thin film with the TiO2 seed layer.
 
Using the synchrotron radiation of the Berlin Electron Storage Ring (BESSY) and conventional UV 400 contact lithography a MOSFET tetrode with submicrometer gate length was fabricated. X-ray lithography has been applied therefore in two resist processes to define the gate lengths and the metallization (contact) level. The employed X-ray masks are based on stress compensated Si membranes with electroplated gold absorber structures. The mask flatness and the pattern distortions are smaller than 3 μm and 100 nm respectively and are adequate for achieving a high yield of transistors.
 
Functional NMOS and CMOS circuits with fully-scaled 0.5 μm ground rules have been fabricated using synchroton radiation X-ray lithography for all device levels. The exposures were done at the VUV storage ring of the National Synchrotron Light Source at Brookhaven National Laboratory using a mask/wafer aligner developed at IBM Research. The performance of the aligner on both test wafers and device wafers is discussed, with emphasis on overlay. Characteristics of the fabricated circuits are also presented.
 
This paper presents the 2.4 GHz front-end and the first downconversion section of a fully integrated low-IF receiver. The dual-conversion receiver and rejects the image repeatably by 60 dB using integrated polyphase filters without calibration or tuning. The gain of the RF mixer and IF amplifier is switchable to slide the available dynamic range of the following stages, based on the conditions of the input signal. The front-end and downconversion sections drain 35 mA on average from a 3.3 V supply. Minimum cascade NF is 7.2 dB, and maximum cascade IIP3 is −3.4 dBm.
 
Semiconductor heterostructures of AIIIBV type with a bandgap adjustable by composition assure a good detection in a large spectral range of 0.8–1.6 μm, compatible with optical fibre communication spectral range. The paper presents the In0.53Ga0.47As/InP heterostructures, grown by Cl-VPE technique, and their use for fabrication of high-speed photodetectors as PIN photodiodes and Schottky barrier photodetectors. The PIN photodiodes have high value for responsivity, namely 0.3 A/W at 0.8 μm and 0.82 A/W at 1.3 μm wavelength without AR coating. The response time is 150 ps on 50 Ω load resistance, limited by RC constant. For Schottky barrier photodetectors metal sandwiches of Ni/Pd/Au, Ag/Pd/Au and Ti/Pd/Au were deposited on the heterostructures surface. The barrier height in the range (0.42–0.6) eV was obtained by growing a thin interlayer of n-InP over an n-type InGaAs/InP heterostructure. The responsivity of Schottky photodiodes was in the range 0.16–0.25 A/W and the response time under 100 ps.
 
We have investigated the effect of Auger and photoelectrons on the resolution of x-ray lithography by comparing exposures made in PMMA with CK, CuL, and AlK x-rays. For all three wavelengths the same high-contrast mask was used, and in each case a 30nm-linewidth mask pattern was faithfully replicated without apparent linewidth reduction. These experimental results, which are at variance with numerous published assumptions and predictions concerning the effect of photoelectrons on pattern replication, are consistent with the Monte Carlo calculation of Murata (1985) which shows that energy dissipation falls off by 3dB at 5nm from the point of x-ray absorption.
 
In this study we report the epitaxial growth of BaTiO3 films on Si(0 0 1) substrate buffered by 5 nm-thick SrTiO3 layer using both MBE and PLD techniques. The BaTiO3 films demonstrate single crystalline, (0 0 1)-oriented texture and atomically flat surface on SrTiO3/Si template. The electrical characterizations of the BaTiO3 films using MFIS structures show that samples grown by MBE with limited oxygen pressure during the growth exhibit typical dielectric behavior despite post deposition annealing process employed. A ferroelectric BaTiO3 layer is obtained using PLD method, which permits much higher oxygen pressure. The C–V curve shows a memory window of 0.75 V which thus enable BaTiO3 possibly being applied to the non-volatile memory application.Graphical abstract(0 0 1)-oriented single crystalline BaTiO3 thin films were prepared on SrTiO3- buffered Si(0 0 1) substrate. The C–V curve of the MFIS structure based on BTO films shows a memory window of 0.75V which enable BTO possible being applied to non-volatile memory application.Highlights► BTO/STO/Si by MBE and PLD. ► (0 0 1)-oriented single crystalline BTO with a flat surface ► 0.75V memory window of C–V curve.
 
The aim of this work was to investigate the potentiality of molecular beam epitaxy techniques to prepare high-κ LaAlO3 (LAO) films on silicon (001). First, the homoepitaxial growth of LAO was demonstrated for growth temperatures higher than 520 °C. Then, amorphous LAO films were prepared on p-type Si(001) substrates with no interfacial SiO2 formation. LAO layers directly grown on Si(001) appear to be single crystalline at growth temperatures higher than 600 °C but show interfacial reactions. Electrical measurements demonstrate that the growth temperature has a critical impact on 1eakage current. LAO films grown under atomic oxygen have a higher permittivity and a lower charge density than films grown under molecular oxygen.
 
We have investigated the morphology and the electrical properties of epitaxial NiSi2/Si contacts formed in a Ni/Ti/Si(0 0 1) system. An atomically flat interface between an epitaxial NiSi2 layer and a Si(0 0 1) substrate without {1 1 1} facets can be formed by annealing at 750 °C. Glazing angle X-ray reflectivity measurements reveal that interface is extremely flat and uniform over areas as wide as about 1 mm2. Local and inhomogeneous formation of Ni4Ti4Si7 and C54–TiSi2 grains are observed in the NiSi2 layer and on the surface, respectively, after annealing at 850 °C. The epitaxial NiSi2 layer exhibits high thermal robustness compared to a NiSi layer formed in a conventional Ni/Si system and the sheet resistance of the epitaxial NiSi2 layer formed in Ni/Ti/Si systems keeps the low value in the annealing at the temperature ranging between 650 °C and 850 °C. Schottky barrier heights of this epitaxial NiSi2/Si contacts for n- and p-type are estimated to be 0.30 and 0.37 eV, respectively.
 
TEM and RBS studies of the solid phase reaction of Co/Ti- and Co/Hf/Si(001) layer systems are reported. In addition to conventional annealing procedures a special thermal treatment was applied to investigate the intermediate stages of the reaction during heating up. With rising temperature a complex Co–Si-phase sequence was observed which finally results in the growth of epitaxial CoSi2. The emerging silicide phases were proved to grow with preferred orientation relations to the substrate. The observed growth behaviour is compared for both the systems and discussed considering aspects of energy minimization and material supply under the conditions of a thin film reaction.
 
Structural investigations were performed to analyse the influence of ultrathin silicide layers (templates) on the quality of epitaxial CrSi2 films (thickness of about 40 nm), which were subsequently grown by reactive codeposition on top of these templates. X-ray diffraction and reflectometry, Rutherford backscattering spectrometry (RBS), transmission and scanning electron microscopy were used to characterize orientation, crystalline quality and morphology of the CrSi2 films on Si(0 0 1). The templates were formed at a Cr thickness tCr ranging from 0.20 to 1.00 nm. It was shown that reactive codeposition onto templates, grown at 0.35 nm ⩽ tCr ⩽ 0.52 nm, leads to the formation of smooth, homogeneous in thickness epitaxial layers. An RBS minimum yield of about 18% was observed for these samples. The investigation of a thin silicide template (tCr = 0.4 nm) has shown that it consists of separated crystallites with two epitaxial orientations: CrSi2(0 0 1)[1 0 0]∥Si(0 0 1)[1 1 0] and . The thicker CrSi2 film, grown on top of this template, reproduces its morphology and orientation.
 
Si(113) may be a competitive substrate material for Si integrated circuits. High-quality SiO2/Si(113) films can be produced by standard oxidation techniques. Based on investigations of the initial stages of oxidation by Scanning Tunneling Microscopy and ab initio calculations, we interpret this result as an effect of tensile stress and reduced diffusivity of oxidation by-products on Si(113). Breakdown behavior (field and charge-to-breakdown) of 5 nm thick oxide layers on Si(113) is better than on Si(001), at least by a factor 2 for charge to breakdown. To evaluate the technological potential of Si(113), gate-controlled diodes were prepared on Si(113) and Si(001) under conditions optimized for Si(001). Electrical measurements demonstrate no significant differences in the density of rechargeable interface states, threshold voltages, and charge carrier generation and recombination. We believe that optimization of the preparation conditions may lead to extremely reliable thin gate oxides on Si(113).
 
The application of copper diffusion barrier films deposited by atomic layer deposition (ALD, ALCVD™) on functional multilevel, dual damascene structures is in its infancy. In this study, two different ALD barrier films (TiN and WNC) were evaluated to determine how they affected the electrical properties of two-metal layer, dual damascene copper structures built in SiO2. In addition, bulk properties of each film were evaluated. It was found that ALD films show feasibility of functioning electrically in fully integrated interconnect structures as well as acting as a copper diffusion barrier and copper adhesion layer.
 
A novel nanofabrication technique for the realization of nanometer resonant tunnelling diodes with independent control of the electrodes and quantum well dimensionalities is presented. Liquid helium temperature current-voltage (I-V) characteristics exhibit a set of resonance lines due to the tunnelling of the 3D electrode electrons through the 0D states of the quantum box. Preliminary results on the line shape and on the relative intensity dependence of the lines with the radius of the box and the principal quantum number are also discussed.
 
We show that overgrowth of self-organized InAs islands formed on GaAs substrate by InGa(Al)As alloy results in the activated alloy decomposition. Both increase in the island size during overgrowth and formation of In-rich areas above them occur. The PL emission of such structures is significantly red shifted (up to 1.3 μm at 300 K) as compared to that for initial InAs islands. Adding Al into the alloy enhances the effect of decomposition and correspondingly increases the red shift for a given In concentration. Lasers based on QDs formed by the alloy decomposition show single transverse mode CW operation up to 110 mW near 1.3 μm.
 
Thin high-quality calcium fluorite films are grown on (1 1 1) silicon in the low- and middle- temperature molecular-beam epitaxy processes followed by annealing. Metal-insulator-semiconductor structures with such films exhibit much smaller leakage currents than the casual structures with silicon dioxide. They demonstrate also satisfactory wear-out characteristics. Low leakage is achieved not due to high permittivity, but due to restricted tunnel transparency of the fluorite owing to a large effective mass of carriers. Therefore, CaF2 is a promising candidate for gate material in advanced field-effect transistors.
 
Through the sequential use of classical molecular dynamics and first-principles relaxation methods, we generate an abrupt model interface for the 4H(0001)SiC-SiO2 interface showing regular structural parameters without any coordination defect. The bond density reduction at the interface is achieved through the use of two interfacial structural units which connect the disordered oxide to the abrupt crystalline substrate. The present model demonstrates that the sole topological constraints at SiC substrates do not preclude the occurrence of oxides of similar quality as compared to those found on Si substrates.
 
A wide range energy (25, 50, 100keV) electron beam lithography system with Schottky electron source and UHV chamber has been developed. The electron probe stability of 2.5%/hour is measured, and a beam diameter of 3nm is confirmed at 100keV beam energy. The ultimate pressure of bakeable work chamber is confirmed to reach 4×10−10Torr. With the UHV chamber and a gas jet nozzle, this system allows to perform in-situ electron beam nanolithography by combining with UHV multichamber systems.
 
We reported the replication of sub-100 nm nanostructures by an ultraviolet (UV) nanoimprint lithography (NIL) technique. We used a novel UV curable epoxy siloxane polymer as the NIL resist to achieve features as small as 50 nm. The polymeric soft molds for the NIL were fabricated by casting toluene diluted poly(dimethyl-siloxane) (PDMS) on the hydrogensilsesquioxane (HSQ) hard mold. The NIL results were characterized by using a scanning electron microscope and an atomic force microscope. Our results illustrate that, with the epoxy siloxane resist, the 50 nm HSQ features on the hard mold can be successfully replicated using PDMS soft molds.
 
In this work we report on microactuators and microgrippers fabricated from SOI (silicon-on-insulator) wafers by a surface and bulk micromachining fabrication technology. The main advantages of this technology are: (a) large thickness of the devices (10–40 μm) resulting in devices which are stable against disturbing forces perpendicular (z-direction) to the ground plate; (b) the small number of fabrication steps required. Only three steps are required: lithography, trench etching of silicon, and release of movable parts (selective wet etching of the buried oxide layer). The linear motion (‘pull action’) of the microactuator is converted into a rotational gripping motion by a system of elastic spring beams. At a voltage of 90 V, the gripper tweezers are closed.
 
The first results of experiments on direct photo-etching of organic polymers using a 10 Hz X-ray source based on a laser-irradiated gas puff target are presented. X-ray radiation in the wavelength range from 2 to 15 nm was produced as a result of irradiation of a double-stream gas puff target with Nd:YAG laser pulses of energy 0.8 J and time duration 3 ns. The resulting X-ray pulses with energy of about 100–200 mJ were used to irradiate samples of organic polymers to create microstructures by direct photo-etching. The obtained results show that direct photo-etching using the laser-plasma X-ray source could be useful for micromachining of organic polymers.
 
Top-cited authors
Christian David
  • Paul Scherrer Institut
Jens Gobrecht
  • Paul Scherrer Institut
Helmut Schift
  • Paul Scherrer Institut (PSI)
Enzo Mario Di Fabrizio
  • King Abdullah University of Science and Technology
Juergen Brugger
  • École Polytechnique Fédérale de Lausanne