Journal of Circuits, Systems and Computers

Published by World Scientific Publishing
Online ISSN: 0218-1266
Publications
An example illustrating the effects of memory layout on the number of page accesses.
A sequence of variable accesses and (a) its access graph representation; (b) the optimal graph partitioning ;(c) (b)'s implied memory layout. We define a problem of graph partitioning, Π m G(V,E) , of multigraph G(V, E), as partitioning V into t disjoint subsets V 1 ,V 2 , ···V t , each containing at most m vertices with the objective of maximizing the quantity of
Conference Paper
It has been reported and verified in many design experiences that a judicious utilization of the page/burst access modes supported by DRAMs contributes a great reduction in not only the DRAM access latency but also DRAM's energy consumption. Recently, researchers showed that a careful arrangement of data variables in memory directly leads to a maximum utilization of the page/burst access modes for the variable accesses, but unfortunately, found that the problems are not tractable, consequently, resorting to simple (e.g., greedy) heuristic solutions to the problems. To improve the quality of existing solutions, we propose a new storage assignment technique, called zone_alignment, for variables, which effectively exploits an efficient 0-1 ILP formulation and the temporal locality of variables' accesses in code.
 
Conference Paper
Timing and area of circuits are two of the most important design criteria to be optimized in data path synthesis. Further, carry-save adder (CSA) cell has been proven to be one of the most effective hardware units in optimizing timing and area of the circuits. However, the prior approaches have only been concerned with the optimization of a single operation tree using CSAs, and have not been able to optimize multiple operation trees properly. This paper proposes a practical solution to the problem of an accurate exploration of trade-offs between timing and area in optimizing arithmetic circuit using CSAs. The application of the approach leads to finding a best CSA implementation of circuit in terms of both timing and area
 
Conference Paper
This paper presents a driver for an HID lamp based on the application of a high frequency current square waveform through the lamp with the goal of avoiding acoustic resonances. The proposed ballast is fed from a 12 V DC input voltage and is intended to be used in systems supplied from nonconventional sources, such as back-up batteries, photovoltaic generators and automotive applications. In order to initiate the discharge in the lamp, a specially designed igniter supplied from the 12 V DC voltage is used to apply high voltage ignition peaks to the lamp. Experimental results obtained from a laboratory prototype for a 70 W metal halide lamp supplied at 30 kHz are also shown to evaluate the possibilities of the proposed topology
 
Conference Paper
In this paper we proposed an approach for obtaining optimal stable modulator coefficients which satisfy both SNR and stable input limit requirements. It is a revised version of [1]. The empirical (3rd to 5th order) stable input limit formula is presented. Modulator examples are presented to demonstrate the usage of proposed method. The simulation results show that nearly 1-bit(6dB) resolution is improved with the proposed method. The opamp de-offset influence on modulator performance is also discussed.
 
Conference Paper
The increasing demand for Internet and World Wide Web access from the home has stimulated research into finding methods of providing access at rates greater than the 28.8 kb/s offered by current computer modems. Most copper telephone pairs have bandwidth capacities much greater than the 3.4 kHz voice-band. Using this excess bandwidth it is possible to substantially exceed current modem rates. This paper describes an inexpensive and readily deployable network access technology capable of providing bit rates ranging from hundreds of kb/s to potentially greater than 1 Mb/s on existing copper telephone lines. The usable bit rate, which varies depending on the length and gauge of the wire, is adaptively determined at system start up. The results of rate adaption testing are presented, as well as the results of throughput testing when TCP is used to provide flow control across the adaptive rate transmission line. It is also shown that current IBM compatible computers are only capable of supporting data rates of slightly more than 1 Mb/s through Ethernet adaptor cards; providing access rates beyond a few Mb/s is currently unnecessary
 
Conference Paper
A new motion estimation scheme for an MPEG like video coder is suggested. The proposed `adaptive motion estimation' scheme consists of five functional blocks: temporal subband analysis (TSBA), extraction of temporal activity distribution (TAD), scene change detection (SCD), picture type replacement (PTR), and a temporally adapted block matching algorithm (TABMA). All five functional blocks are developed primarily based on temporal subband analysis. According to the significance of the TAD, the TABMA adjusts its nonuniform motion vector search area. Also, a newly proposed SCD and PTR integrated method can prevent poor motion prediction for a video sequence containing abruptly changing scenes. Computer simulation results show that the proposed motion estimation scheme is superior to that of typical MPEG like video coders: it requires far less computations, and it shows much better performance
 
Conference Paper
The paper deals with electric models applied to investigating sophisticated systems, such as transport, economics and neuron ones. Interest in these systems can be explained by the fact that they are characterized by parallel (collective) means of calculating sophisticated processes, which are carried out without any calculation program, but under the influence of sophisticated inner information processes. Electric models can also be looked upon as original structures for neuron-like systems. The paper emphasizes comparison between suggested electric models, on one hand, and mechanical and thermal models, on the other. It has been shown that entropy phenomena, typical for the latter, can be closely compared to those in electric models, which are distinguished by pure electrical values. Also, it has been shown that irreversible processes of energy dissipation. e.g. entropy processes in mechanical models, correspond to processes of energy concentration, energy transfer and/or energy exchange in electric models. This enables new light to be shed on processes in electric circuits, especially those concerned with structural improvements of electric circuitry, their self-organization meaning a neg-entropic information character for these processes. Models of two economic tasks are considered, wherein the calculation process is characterized under the influence of those processes. Assumption of the importance of reactive elements, such as carriers of neg-entropy in an electric circuit, is made.
 
Conference Paper
For the sake of reducing the hard cost of multiple RF chains and the complexity for spatial multiplexing systems, in this paper a novel low-complexity transmit antenna selection criterion is proposed based on MMSE V-BLAST system utilizing ordered successive interference cancellation (OSIC) detection. Unlike others transmit antenna selection schemes for V-BLAST systems, the proposed algorithm synthetically considers the impacts of detection order, interference cancellation and noise amplification due to that applying sub-optimal sorting and QR decomposition by introducing an extended channel matrix based on MMSE V-BLAST system. Theoretical analysis and simulation results show that the proposed algorithm achieves both higher outage capacity and better symbol error rate (SER) performance even with low computational complexity.
 
Conference Paper
In this paper, we present a systematic theory of the optimum subband interpolation of a family of n-dimensional signals which are not necessarily band-limited. We assume that the Fourier spectrums of these signals have weighted L ² norms smaller than a given positive number. The proposed method minimizes the measure of error which is equal to the envelope of the approximation errors with respect to the signals. In the following discussion, we assume initially that the infinite number of interpolation functions with different functional forms are used in the corresponding approximation formula. However, the resultant optimum interpolation functions are expressed as the parallel shifts of the finite number of the n-dimensional functions. It should be noted that the optimum interpolation functions presented in this paper satisfy the generalized discrete orthogonality and, as a result, minimize the wide variety of measures of error at the same time. In the literature, ⁶ a similar discussion is presented. However, it is assumed that the signal is band-limited and the interpolation functions are compulsorily time-limited. Hence, these interpolation functions cannot minimize other measures of error except the proposed one. Interesting reciprocal relation in the approximation, is also discussed. An equivalent expression of the approximation formula in the frequency domain is derived.
 
Conference Paper
In today's sub-100nm CMOS technologies, leakage current has become an important part of the total power consumption, affecting both yields and lifetime of digital circuits. Dual Vth assignment, which is proven to be an effective method of reducing leakage power in the past, is also effective in today's technologies with certain modifications. In the paper, based on a statistical timing analysis (SSTA) framework we presented a dual V<sub>th</sub> assignment method which can effectively reduce the leakage power even in the presence of large Vth variation. Besides, we use a statistical DAG pruning method which takes correlation between gates into account to speed up the dual V<sub>th</sub> assignment algorithm. Experimental results show that statistical dual V<sub>th</sub> assignment can reduce on average 40% more leakage current compared with conventional static method without affecting the performance constraints. Our DAG pruning method can reduce on average 30% gates in the circuit and save up to 50% of the total run time.
 
Conference Paper
In this paper, a fingerprint recognition algorithm is suggested. The algorithm is developed based on the wavelet transform, and the dominant local orientation which is derived from the coherence and the gradient of Gaussian. By using the wavelet transform, the algorithm does not require conventional preprocessing procedures such as smoothing, binarization, thinning and restoration. Computer simulation results show that when the rate of Type II error-incorrect recognition of two different fingerprints as identical fingerprints-is held at 0.0%, the rate of Type I error-incorrect recognition of two identical fingerprints as different ones-turns out as 2.5% in real time
 
Conference Paper
Some considerations on initial partitioning the circuit within harmonic balance analysis are presented. Instead of linear and nonlinear, it is divided into resistive and reactive parts. Following the procedure presented, frequency as a parameter appears no more than once inside each equation, and most of the unknowns are expressed explicitly. The former is advantageous when examining an autonomous system, and the latter enables a simple numerical process. The method proposed is illustrated by an example
 
Conference Paper
A method of low bit-rate facial image coding specifically designed for the use in video telephone is presented. The basic principle for this facial image coding is to exploit the capabilities of 2D image warping techniques to generate the replica of the sender's facial expression merely by deforming a master face image, which is sent once at the beginning of the telephone call. Several parameters that describe facial expressions are monitored at the transmitter at the video frame rate of 30 frames/s, and then transmitted to the receiver using the in-band data channel. Since transmission of actual image data happens once or when another image is required, the bit-rate is much lower than that required by ordinary video image transmission. A fast bilinear mapping method for warped images, a grid mesh set over the facial image, various warping algorithms to realize head movement and facial motions with respect to eyes and mouth are discussed. This paper also compares the presented low bit-rate facial image coding to its competing methods such as MPEG and the method using a 3D facial model.
 
Conference Paper
This paper proposes a circuit partitioning algorithm in which the delay of each critical signal path is within a specified upper bound. Its core is recursive bipartitioning of a circuit which consists of three stages: (0) detection of critical paths; (1) bipartitioning of a set of primary inputs and outputs; and (2) bipartitioning of a set of logic-blocks. In (0), the algorithm detects the critical paths based on their lower bounds of delays. The delays of the critical paths are reduced with higher priority. In (1), the algorithm attempts to assign the primary input and output on each critical path to one chip. In (2), the algorithm not only decreases the number of crossings between chips but also assigns the logic blocks on each critical path to one chip by exploiting a network flow technique with logic-block replication. The experimental results demonstrate that it resolves almost all path delay constraints with the maximum number of required I/O blocks per chip small compared with conventional algorithms
 
Conference Paper
The authors show that, in the solution of the double matching problem given by H.J. Carlin and B.S. Yarman (1983), a one-to-one correspondence does not exist between the output impedance Z <sub>q</sub>( S ). Also, D.C. Youla's (1961) conditions imposed on the chain parameters are extended and applied to the passive, lumped, lossless, and nonreciprocal two-port networks. Based on the analysis, a CAD method using the chain parameters is proposed to solve the double matching problem, where the equalizer may have complex transmission zeros
 
Conference Paper
This paper presents a few techniques based on an efficient use of memory resources to speed up the transient analysis of piecewise linear circuits, such as power electronic circuits. These techniques use the fact that the matrix in the linear equation solving routines can only have a finite number of different values. Hence, by adding a cache memory management technique to store the LU factor of these matrices for future reuse, the linear equation solver can be performed much faster than that of a general purpose simulation program in which these LU factors have to be recomputed every time. Since most of the CPU analysis time is spent in solving linear equations, these techniques can actually speed up the transient analysis of piecewise linear circuits significantly (100-600%)
 
Conference Paper
Recently discrete-time cellular neural network (DT-CNN) is applied to many image processing such as compression and reconstruction, recognition, and so on. Not a few models work as a simple filter and doesn't make good use of CNN dynamics by feedback A template, which is one of the significant characteristics of CNN. If CNN is applied to a filter only by feed forward B template, you should propose a model consists of digital filters using high speed signal processing modules such as high speed DSP IC. This paper describes nonlinear interpolative effect of feedback template, that is, A template by using the evaluation of image compression and reconstruction
 
Conference Paper
A simplified variant of the classical Shannon Hagelbarger theorem on the concavity of the resistance function is used to derive separate necessary and sufficient conditions characterizing always well posed, sometimes ill posed and always ill posed classes of linear resistive circuit structures introduced and characterized by Haster, new both in formulation and proof. This reveals that the form of the second partial derivative of the resistance function is responsible for various kinds of the structural solvability of linear circuits. Next, alternative “if and only if” criteria for these classes are established. They involve replacements of reciprocal circuit elements by combinations of contractions and removals leading to pairs of complementary directed nullator and directed norator trees with appropriately defined signs, and resemble therefore earlier famous Willson Nielsen feedback structure and Chua-Nishi cactus graph criteria for circuits containing traditional controlled sources
 
Conference Paper
To analyze an electric power system with a lumped constant circuit model, it is necessary to simulate, in detail, the system conditions such as the states of connections of the generators. The analysis thus requires enormous time and labor. The authors noticed that the propagation characteristics of power disturbance in load cut off tests on generators of a power system are similar to the propagation characteristics of power disturbance in distributed constant circuits, and have been examining methods for simulating a power system with a distributed constant circuit. We applied the active sink method to the distributed constant circuit model of a power system to examine stabilization of power disturbance by controlling the power flow of a DC system parallel-connected to an AC system
 
Conference Paper
One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many such switching activities are due to spurious pulses, called glitches. Recently, a new model of glitch analysis, called G-vector has been proposed. The power of the model is that, unlike the existing ones which model only the propagation of glitches to count the number of glitches in the circuits, it allows one to model the generation, propagation and elimination of glitches to be able to not only count the number of glitches but also locate the glitches. In this paper, we complete the concept of G-vector by providing a set of efficient solutions to the two important practical issues: (1) extending to signals over multiple clock cycles, and (2) extending to a logic decomposition utilizing the model. Integrating the solutions all together enables G-vector to be very efficient. A set of experimental results is provided to show the effectiveness of the proposed solutions
 
Conference Paper
This paper presents a new design of half-static clock-gating D flip-flop (DFF). The proposed DFF consists of a dynamic master and a half-static slave built with a pass-transistor clock- gating circuitry. The new circuit greatly reduces the total power dissipation, especially in the low data activity cases, and saves a lot of silicon area. The performance of the proposed DFF is verified with SPICE simulation using the 0.18 mum mixed-signal CMOS technology. The overall performance of the present design is much better than numerous DFFs reported in the literatures.
 
Conference Paper
In this paper, the periodically time-varying (PTV) structure, previously proposed for realizing FIR filters, is extended to IIR filter realization. The realization consists of ternary ({0, ±1}) or quinary ({0, ±1, ±2}) PTV coefficients with simple input and output units. Coefficient multiplications as well as the input and output units require no hardware multiplier, which helps increase the processing speed or reduce the chip area. Bit-level architectures are presented. The regularity and local interconnection of the architectures help simplify VLSI design and layout.
 
Conference Paper
By splitting the output capacitor of a basic boost converter, and combining the resulting capacitors with the main switch in the form of a switched-capacitor circuit, a new step-up structure is realized. Without using a transformer, a high line-to-load DC voltage ratio is obtained. An output filter is added as usual in boost converters for getting a free-ripple output. The circuit compares favorably with a quadratic boost converter as regarding the count of devices and efficiency, even if it presents a lower DC gain. A DC analysis of the novel converter is presented. Experimental and simulation results confirm the theoretical expectations. By increasing the number of capacitors in the switched-capacitor circuit, higher gains are obtained. Versatility, high voltage gain and a good transient response are the features of the proposed converter.
 
S-box flow chart 
Rearrange the result to notice the repetition and the parallelism in the operation 
RC-Instruction Utilization in every step (Lookup Table mapping only) 
Conference Paper
Recently, the area of reconfigurable computing has received considerable interest. Reconfigurable system is a specific name that is used for any machine that can be reconfigured during runtime to execute an algorithm as a hardware circuit. As a middle solution, reconfigurable systems stand halfway between traditional computing systems and specific hardware. This paper presents the mapping and performance analysis of two encryption algorithms, namely Rijndad and Twofish, on a coarse grain reconfigurable platform, namely MorphoSys. MorphoSys is a reconfigurable architecture targeted for multimedia applications. Since many cryptographic algorithms involve bitwise operations, bitwise instruction set extension was proposed to enhance the performance. The authors present the details of the mapping of the bitwise operations involved in the algorithms with thorough analysis. The methodology used can be utilized in other systems
 
Conference Paper
The use of star graphs as a viable interconnection scheme for parallel computers has been examined by a number of authors. An attractive feature of this class of graphs is that it has sublogarithmic diameter and has a great deal of symmetry akin to the binary hypercube. The authors describe a new class of algorithms for embedding Hamiltonian cycle, the set of all even cycles and a variety of two and multi-dimensional grids in a star graph. They derive an algorithm for the ranking and the unranking problem with respect to the Hamiltonian cycle
 
Conference Paper
The authors present a novel decomposition technique called the optimal decomposition (OD) for decomposing 2-D magnitude specifications into 1-D ones. By using the OD, 2-D magnitude specifications can be decomposed into 1-D ones which are always nonnegative, and the root mean square (RMS) decomposition error is minimum. As a result, the problem of designing a 2-D digital filter can be reduced to one of designing a pair of 1-D digital filters. Thus, the original 2-D design problem can be significantly simplified. A numerical example is given to illustrate the OD-based design technique
 
Conference Paper
In this paper, we present a basis matrix representation of grayscale morphological filters in N-dimensions. A procedure is proposed to derive the basis matrix and the block basis matrix (BBM) from an N-dimensional grayscale structuring element (GSE). It is shown that both opening and closing with arbitrary N-dimensional GSE can be accomplished by a local matrix operation using the basis matrix. Furthermore, these basis matrix representations are extended to the efficient implementation of open-closing (OC) and close-opening (CO) using the BBM
 
The tuning center frequency of the ¯lter.
Conference Paper
In this paper, a new current-mode second-order square-root-domain notch filter is proposed. The design is based on the state-space synthesis method with two subcircuit; square-root and squarer/divider circuits. In the circuit, the input and the output values, and dominant variables are all currents. Only MOS transistors and grounded capacitors are required to realize the filter circuit. Three cases of the second-order notch filter were obtained. The regular notch was obtained when omega<sub>n</sub> = 3D omega<sub>p</sub>, the lowpass notch was obtained when omega<sub>n</sub> > omega<sub>p</sub>, and the highpass notch was obtained when omega<sub>n</sub> < omega<sub>p</sub>. The center frequency, and the notch frequency of the filter can be electronically tuned by changing external currents. Time and frequency domain simulations are performed using PSPICE program for the filter to verify the theory and to show the performance of it. For this purpose, the filter is simulated by using TSMC 0.35 mum Level 3 CMOS process parameters.
 
Conference Paper
We address the problem of state encoding for synchronous finite state machines (FSM's), targeted for low power design. Most previous work in FSM state encoding has been focused on minimizing chip area and does not consider switching activity of the circuit. As a result, this does not always lead to a power efficient implementation. Especially in CMOS circuits, the switching activity is a very important factor in power dissipation. In this work, we define a function λ for automatic tradeoff between switching activity and area that contribute to power dissipation. λ is used in determining the encoding affinity between states and is observed to be related to the number of states of a FSM in our experiments. A state encoding algorithm, based on hypercube embedding, is proposed to find encodings of states such that the sum of bit toggles between each pair of states times the encoding affinity between them is minimized. Results over a wide range of MCNC benchmark examples which show the efficacy of our technique are presented
 
The artificial SV time series used for this study.
Monte Carlo histories of h 100 generated by HMC (left) and Metropolis (right) with T = 2000 data set. The Monte Carlo histories in the window from 50000 to 60000 are shown.
Autocorrelation functions of three volatility variables h 10 , h 20 and h 100 sampled by the HMC algorithm for T = 2000 data set. These autocorrelation functions show the similar behavior.
Article
The hybrid Monte Carlo (HMC) algorithm is applied for the Bayesian inference of the stochastic volatility (SV) model. We use the HMC algorithm for the Markov chain Monte Carlo updates of volatility variables of the SV model. First we compute parameters of the SV model by using the artificial financial data and compare the results from the HMC algorithm with those from the Metropolis algorithm. We find that the HMC algorithm decorrelates the volatility variables faster than the Metropolis algorithm. Second we make an empirical study for the time series of the Nikkei 225 stock index by the HMC algorithm. We find the similar correlation behavior for the sampled data to the results from the artificial financial data and obtain a $\phi$ value close to one ($\phi \approx 0.977$), which means that the time series has the strong persistency of the volatility shock. Comment: 15 pages
 
Article
The reversible circuit synthesis problem can be reduced to permutation group. This allows Schreier-Sims Algorithm for the strong generating set-finding problem to be used to find tight bounds on the synthesis of 3-bit reversible circuits using the NFT library. The tight bounds include the maximum and minimum length of 3-bit reversible circuits, the maximum and minimum cost of 3-bit reversible circuits. The analysis shows better results than that found in the literature for the lower bound of the cost. The analysis also shows that there are 1960 universal reversible sub-libraries from the main NFT library.
 
Chapter
In this paper we study the problem of diagnosing t/s-diagnosable systems. We present a t/t+k-diagnosis algorithm which runs in polynomial time for each fixed integer k. The t/t-diagnosis algorithm of [10], the t/t+1-diagnosis algorithm of [11] and the t/t+k-diagnosis algorithm of this paper complement the corresponding t/t+k-diagnosability algorithms of Sullivan [12]. It is shown in [17] that the basic approach of the t/t+k-diagnosis algorithm of this paper can be used to design a diagnosis algorithm for a sequentially t-diagnosable system which has complexity O(n 3.5 +mnt t ) where m and n are the number of edges and vertices, respectively, of the test interconnection graph.
 
The platform hourglass.
Three platforms and mappings between them.  
Platforms and mappings between them.
Illustration of an actor-oriented model (above) and its hierarchical abstraction (below).  
Article
In this paper, we argue that model-based design and platform-based design are two views of the same thing. A platform is an abstraction layer in the design flow. For example, a core-based architecture and an instruction set architecture are platforms. We focus on the set of designs induced by this abstraction layer. For example, the set of all ASICs based on a particular core-based architecture and the set of all x86 programs are induced sets. Hence, a platform is equivalently a set of designs. Model-based design is about using platforms with useful modeling properties to specify designs, and then synthesizing implementations from these specifications. Hence model-based design is the view from above (more abstract, closer to the problem domain) and platform-based design is the view from below (less abstract, closer to the implementation technology). One way to define a platform is to provide a design language. Any valid expression in the language is an element of the set. A platform provides a set of constraints together with known tradeoffs that flow from those constraints. Actor-oriented platforms, such as Simulink, abstract aspects of program-level platforms, such as Java, C++, and VHDL. Actor-oriented platforms orthogonalize the actor definition language and the actor composition language, enabling highly polymorphic actor definitions and design using multiple models of computation. In particular, we concentrate on the use of constrained models of computation in design. The modeling properties implied by well chosen constraints allow more easily understood designs and are preserved during synthesis into program-level descriptions. We illustrate these concepts by describing a design framework built on Ptolemy II.
 
Article
In this paper, we present multipliers using a modified binary tree of the modulo m signed-digit (SD) number residue adders where m=2^n-1, 2^n, 2^n+1. New additions rules are used for generating the intermediate sum and carry with a binary number representation. The sums and carries are directly inputted into the next stage of adders, so that the modulo m multiplier using binary modulo m adder tree proposed in [13] can be improved. Moreover residue multipliers using the SD residue adders are also designed with inputs/outputs in binary number representation. The design and simulation results of the proposed residue arithmetic circuits show that high speed arithmetic circuits can be obtained.
 
Article
Many problems in computer-aided design of highly integrated circuits (CAD for VLSI) can be transformed to the task of manipulating objects over finite domains. The efficiency of these operations depends substantially on the chosen data structures. In the last years, ordered binary decision diagrams (OBDDs) have proven to be a very efficient data structure in this context. Here, we give a survey on these developments and stress the deep interactions between basic research and practically relevant applied research with its immediate impact on the performance improvement of modern CAD design and verification tools. 1 Introduction The development of digital circuits by means of CAD (Computer-Aided Design) systems has a strong influence on many areas of computer science. Applications in information processing, telecommunication or in industrial control systems permanently require the construction of more and more powerful high-speed circuits. On the one hand, this imposes bigger an...
 
Article
Petri nets 46,37,45,48 are a powerful formalism for modeling concurrent systems. They are capable of implicitly describing a vast state space by a succinct representation which gracefully captures the notions of causality, concurrency and conflict between events. Petri nets have also been chosen by many authors as a formalism to describe the behavior of asynchronous circuits by interpreting the events as signal transitions, thus coining the term Signal Transition Graph (STG). 50,4 A design framework for asynchronous systems involves three main aspects: formal specification, verification and synthesis. In this paper we review the main techniques we have used to cover these aspects in recent years, with a special focus on asynchronous circuits.
 
Article
Our purpose in the present paper is to investigate the structural properties of the newly proposed Cayley networks of constant node degree 4. We show that the graph contains rings of maximal length in presence of multiple faults. Our results provide further evidence to the usefulness and robustness of these network graphs. 1 Introduction Cayley graphs have drawn considerable interest in the recent past for designing interconnection networks because of many desirable properties like low diameter, low degree, high fault tolerance etc. Cayley graphs are based on permutation groups and include a large number of families of graphs, like star graphs [AK89, AK87], hypercubes [BA84], pancake graphs [AK89, QAM94] and others [Sch91, DT92]. All Cayley graphs are regular, but almost none of the Cayley graphs studied so far offer constant node degree (where node degree does not change with size or dimension of the network). There are a number of applications where we need such constant degree netwo...
 
Article
Inductance extraction has become an important issue in the design of high speed CMOS circuits. Two characteristics of on-chip inductance are discussed in this paper that can significantly simplify the extraction of on-chip inductance. The first characteristic is that the sensitivity of a signal waveform to errors in the inductance values is low, particularly the propagation delay and the rise time. It is quantitatively shown in this paper that the error in the propagation delay and rise time is below 9.4% and 5.9%, respectively, assuming a 30% relative error in the extracted inductance values. If an RC model is used for the same example, the corresponding errors are 51% and 71%, respectively. The second characteristic is that the magnitude of the on-chip inductance is a slow varying function of the width of a wire and the geometry of the surrounding wires. These two characteristics can be exploited by using simplified techniques that permit approximate and sufficiently accurate values ...
 
Article
this paper and must be solved when designing interrupt or speculation hardware. For the basic scheduling mechanism with in-order issue, lemma simplifies condition (6.1). However, for hardware scheduling mechanisms, the deadlock aspect is usually ignored. Thus, is there something truly special about instruction level parallelism that deadlocks cannot occur? The answer is no, because in Ref. 7 it is shown that, in spite of data consistency, the Scoreboard mechanism of Refs. 10 and 3 can run into a deadlock; but the mechanism can easily be fixed. Consequently,
 
Article
This paper introduces a discrete time model for time-variant delays and investigates the very nature of such a delay. It is shown that a linear system-delay interface is a system theoretic necessity for the construction of composite linear systems with time-variant delays. Based on this analysis, two interfaces of particular importance are presented and used to obtain new, simple to check stability results for queue control systems. The relevance of the presented modeling and stability results on queue control systems to QoS control in modern communication networks is illustrated via several examples.
 
Article
A number of matrix flows, based on isospectral and isodirectional flows, is studied and modified for the purpose of local implementability on a network structure. The flows converge to matrices with a predefined spectrum and eigenvectors which are determined by an external signal. The flows can be useful for adaptive signal processing applications and are applied to neural network learning.
 
Article
A new genetic algorithm for switchbox routing in the physical design process of integrated circuits is presented. Our algorithm, called GASBOR (Genetic Algorithm for SwitchBOx Routing), is based on a three-dimensional representation of the switchbox and problem-specific genetic operators. The performance of the algorithm is tested on different benchmarks and it is shown that the results obtained using the proposed algorithm are either qualitatively similar to or better than the best published results.
 
Article
This paper proposes a method to improve robustness of the robot programs generated by genetic programming. The main idea is to inject perturbation into the simulation during the evolution of the solutions. The resulting robot programs are more robust because they have evolved to tolerate the changes in their environment. We set out to test this idea using the problem of navigating a mobile robot from a starting point to a target in an unknown cluttered environment. The result of the experiments shows the effectiveness of this scheme. The analysis of the result shows that the robustness depends on the "experience" that a robot program acquired during evolution. To improve robustness, the size of the set of "experience" should be increased and/or the amount of reusing the "experience" should be increased.
 
Article
System design based on the so-called "synchronous hypothesis" consists of abstracting non-functional implementation details of a system and lets one benefit from a focused reasoning on the logics behind the instants at which system functionalities should be secured, providing ease to generating synchronous circuits and verifying their functionalities using compilers and tools that implement this approach. In the relational model of the design language Signal, this affinity goes beyond the domain of purely synchronous circuits and embraces the context of complex architectures consisting of synchronous circuits and desynchronization protocols: Gals architectures. The unique features of Signal are to provide the notion of polychrony: the capability to describe circuits and systems with several clocks; to support refinement: the ability to assist and support system design from the early stages of requirement specification, to the later stages of synthesis and deployment. The Signal model provides a design methodology that forms a continuum from synchrony to asynchrony, from specification to implementation, from abstraction to concretization, from interfaces to implementations. Signal gives the opportunity to seamlessly model circuits and devices at multiple levels of abstractions, by implementing mechanisms found in many hardware simulators, while reasoning within a simple and formally defined mathematical model. In the same manner, the flexibility inherent to the abstract notion of signal handled in the polychronous design model of Signal invites and favors the design of correct by construction systems by means of well-defined transformations of system specifications that preserve the intended semantics and stated properties of the architecture under design. The aim of the presen...
 
Article
This paper describes and analyzes a low-noise and high-bandwidth transimpedance amplifier featuring a large dynamic range. The designed amplifier is configured on three identical stages that use an active load compensated by an active resistor to improve the stability performance of the amplifier. This topology displays a transimpedance gain of 150 kΩ, which is necessary to obtain a high sensitivity. This structure operates at 5 V power supply voltage, exhibits a gain bandwidth product of 18 THzΩ and a low-noise level of about . This transimpedance amplifier can reach a transmission speed of 240 Mb/s for a photocurrent of 0.5 μA. For a photocurrent of 9.5 μA, a transmission speed of 622 Mb/s can be achieved by using an optical fiber connection containing four channels. The predicted performance is verified by simulations using PSPICE and MAGIC tools with 0.8 μm CMOS AMS parameters.
 
Article
A simple 1.5 V rail-to-rail CMOS current conveyor is presented. The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and HSPICE is used to verify the circuit performance. The current conveyor exhibits low impedance at terminal X (7.2 Ω) and can drive ± 0.6 V to the 300 Ω with the total harmonic distortion of 0.55% at the operating frequency of 3 MHz. The voltage transfer error (between the Y and X terminals) and current transfer error (between the X and Y terminals) are small (-0.2 dB). The power dissipation and bandwidth are 532 μW and over 300 MHz, respectively.
 
Article
The design of a 1.7-ns access time prototype CMOS SRAM is presented. The threshold voltages of the wordline-controlled transistors (WCT) of the proposed memory cells are dynamically variable to achieve high-speed and low-power operations. When the cell is in the read or write (R/W) mode, the VTH of the wordline-controlled transistors is pulled low by increasing the bulk bias such that the drain current will be increased. By contrast, if it is idle in a standby mode, the bulk bias will be reduced by short-circuiting to a ground voltage to subside the leakage current. The highest operating clock rate of the proposed SRAM is measured to be 667 MHz. Moreover, the proposed memory cell possess high stability, the static noise margin is close to 635 mV given the worst case (75°C, FF model, VDD = 1.6 V).
 
Article
This paper presents a scalable low voltage CMOS folded-cascode quadrature voltage controlled oscillator (QVCO) design for radio-frequency (RF) applications using the TSMC 0.18 μm 6M1P CMOS process technology. The simulated startup behavior of this proposed QVCO topology indicates that, the QVCO is free from bi-modal oscillation (frequency ambiguity). The QVCO provided extended voltage swing with the supply voltage scalable in the range of 1.8 V to 0.75 V. The QVCO operates in the frequency range of 4 GHz to 3 GHz (corresponding to supply voltage scaling in the range of 1.8 V to 0.75 V) with around 11.7% tuning range and low quadrature error. The QVCO had a power consumption under 10 mW within the specified supply voltage scaling range. Phase noise simulations using the Monte Carlo analysis provide an approximate phase noise estimate of ≈ -150 dBc/Hz at an offset of 600 KHz from the center frequency (@3.7 GHz) for operation using the 1.8 V supply voltage, using moderate inductor-Q values. Monte Carlo simulations were also carried out to determine the effects of the process, voltage and temperature variations.
 
Article
This paper presents circuit-based approaches to SIMPL Systems (SIMulation Possible, but Laborious Systems), which could be regarded as a "public-key" version of Physical Unclonable Functions. The use of these systems can help us to avoid some of the potential vulnerabilities of conventional cryptography, such as its dependency on secret binary keys. Two specially designed circuits for SIMPL systems are discussed: "skew" memories and massively parallel analog processor arrays known as Cellular Nonlinear Networks. We argue that these circuits are able to serve as SIMPL systems in practice, and discuss their security against numerical and physical attacks.
 
Article
We present a new low-noise, low-power SiGe transimpedance amplifier (TIA) by combining an automatic DC photo-current cancellation, an on-chip DC offset compensation circuit and a single-ended to differential conversion scheme. The conversion method is based of the replica biasing technique in order to provide balanced output signals to the subsequent stages. The chip was fabricated in a 0.18 μm SiGe BiCMOS technology. Experimental results show excellent performances such as 11 GHz bandwidth, 75-dBΩ transimpedance, -19.2 dBm sensitivity measured at 10 Gb/s at a Bit Error Rate (BER) of 10-12, input referred noise, and 9.5 ps peak-to-peak jitter which are the best overall performances reported in its category. The photoreceiver chip is expected to dissipate only 120 mW from a single 3.3 V power supply.
 
Top-cited authors
Wil Van der Aalst
  • RWTH Aachen University
A.M. Soliman
  • Cairo University
Leon O. Chua
  • University of California, Berkeley
Ahmed G Radwan
  • Nile University
Shahram Minaei
  • Dogus Universitesi