In this paper, we investigated the capacity and bit error rate (BER)
performance of Multiple Input Multiple Output (MIMO) satellite systems with
single and multiple dual polarized satellites in geostationary orbit and a
mobile ground receiving station with multiple antennas. We evaluated the
effects of both system parameters such as number of satellites, number of
receive antennas, and SNR and environmental factors including atmospheric
signal attenuations and signal phase disturbances on the overall system
performance using both analytical and spatial models for MIMO satellite
systems.
The proposed digital parity generator circuit is an integrated circuit functions to detect data errors at the transmitter end, and check it at the receiving end. In digital communications, the digital messages are transmitted in the form of 1’s and 0’s between two points. It is an error free if both are the same. The purpose of this research is to implement a design method of digital parity generator layout with 0.7 micron process technology ECPD07 from Tanner Tools. Layout design starts from making schematic circuit, test function and make a layout. Next, check the layout results in terms of design rules and verify the desired functionality gradually. The results show that the circuit has functioned well as an odd parity generator. The simulation results obtained with loads CL = 25 fF, tpLH = 2nS and tpHL = 1.46 nS indicate that tp = 1.73nS or operating frequency of 578 MHz. The integrated digital parity generator circuit using transmission gate has a size of 14758 um2 (78.5 um x188 um), consisting of 74 gates.
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A novel interesting type of variable phase angle voltage mode oscillator using modern building block has been presented in this paper. The new proposed oscillator configuration which uses four voltage differencing gain amplifier (VDGA) and two grounded capacitors can generate two sinusoidal signals that change out of phase by 0 to 90 degree. It has four floating and explicit voltage mode outputs where every two outputs have the same phase. The circuit is characterized by (i) the condition of phase angle of the oscillation (PO) (this concept is introduced for the first time in this paper) can be tuned electronically (ii) the gain of the floating outputs can be controlled independently (iii) it provides electronic control of condition of oscillation (CO) and independent control of frequency of oscillation (FO). The Total Harmonic Distortion (THD) of the output waveforms was obtained and the results were reasonability values (less than 4.5%). The non-ideal analysis and simulation results are investigated and confirmed the theoretical analysis based upon VDGAs implementable in 0.35μm CMOS technology. Simulation results include time response and frequency response outputs generated by using the PSPICE program.
Digital learning through computer software and applications is rarely applied by pesantren (Islamic boarding schools) in Indonesia. So far, the application commonly used by traditional ( salaf ) pesantren, modern ( khalaf ) pesantren, and integrated pesantren is the Maktabah Syamila application. However, in Maktabah Syamila, religious radicalism, false hadiths, and texts allow the killing of innovators. Responding to this, pesantren activists developed digital learning through the application and computer program Maktabah Syumilah NU 1.0 as a comparison to Maktabah Syamila and an alternative to learning in pesantren as a counterradicalism. The research explores digital learning through Maktabah Syumilah NU 1.0 software and computer application to cultivate religious moderation in Temanggung Regency, Central Java, Indonesia. The qualitative research method with case studies on ten traditional pesantren using Maktabah Syumilah NU 1.0. The results show that digital learning through Maktabah Syumilah NU 1.0 is carried out in various activities in and outside the pesantren. The application of Maktabah Syumilah NU 1.0 is used to cultivate Islamic moderation for santri (students of pesantren). The use of Maktabah Syumilah NU 1.0 has an impact on strengthening Islamic moderation in pesantren. This research recommends that the Ministry of Religious Affairs implement Maktabah Syumilah NU 1.0 in all pesantren. Future researchers must explore digital learning more deeply through the latest applications for strengthening Islamic moderation in pesantren.
p>The research of a single stage broadband solid state power amplifier based on
ATF13876 transistor, which operates in the frequency ranging from 1.25 GHz
- 3.3 GHz is presented in this paper. To achieve the broadband performance of
the operating bandwidth, a multi-section quarter wave impedance transformer
and an approximate transformation of previously synthesized lumped elements
into transmission lines are adopted. With neatly design of broadband matching
networks and biasing circuit, excellent matching performances and
unconditionally stability are achieved over the whole operating bandwidth
with a maximum gain of 17.2 dB. The large signal simulation shows that the
proposed circuit reaches a saturated output power of 18.12 dBm with a
maximum PAE of 27.55% and a 1-dB compression point at 5 dBm input power
level. Considering the wide frequency coverage, the features of the proposed
design compares favorably with the contemporary state-of-the-art.
</p
A single-phase binary/quadrature phase-shift keying (BPSK/QPSK) demodulator basing on a phase-locked loop (PLL) is described. The demodulator relies on a linear characteristic a rising-edge RESET/SET flip-flop (RSFF) employed as a phase detector. The phase controller takes the average output from the RSFF and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for a multiple-PSK (m-PSK) signal. Symbol-error rate analysis has also been extensively carried out. The proposed BPSK and QPSK demodulators have been fabricated in a 0.18 - mm digital complementary metal–oxide–semiconductor (CMOS) process where they operate from a single supply of 1.8 V. At a carrier frequency of 60 MHz, the BPSK and QPSK demodulators achieved maximum symbol rates of 25 and 12.5 Msymb/s while consuming 0.68 and 0.79 mW, respectively. At these maximum symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 7.9×10<sup>-10</sup> and 9.8×10<sup>-10</sup>, respectively where their corresponding energy per bit figures were at 27.2 and 31.7 pJ.
This work recommends the performance of coupled inductor based novel 11-level inverter with reduced number of switches. The inverter which engender the sinusoidal output voltage by the use of split inductor with minimised total harmonic distortion (THD). The voltage stress on each controlled switching devices, capacitor balancing and switching losses can be reduced. The proposed system which gives better controlled output current and improved output voltage with moderate THD value. The switching devices of the system are controlled by using multicarrier sinusoidal pulse width modulation algorithm by comparing the carrier signals with sinusoidal signal. The simulation and experimental results of the proposed 11-level inverter system outputs are established using matlab/Simulink and dsPIC microcontroller respectively.
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span>The electronic properties of semiconductor surfaces change readily upon changing the carrier densities by controlling the dopant concentration. Additionally, excess dopant atoms can exert electric field which would affect the molecular adsorption process and could be used to manipulate the dynamic movement of confined molecules. A mechanism can be developed to control the molecular dynamic movement on modified semiconductor surface by dopants thus changing the effect of the electric field on the active molecules. In this study, the Si(111) surface was doped with phosphorus excessively using thermal diffusion process. The surface was then reconstructed to the 7 × 7 configuration via heating under UHV conditions and then studied through STM and STS techniques. The protrusions due to surface and subsurface P atoms appear brighter due to the lone electron pair. The 7 × 7 reconstruction would be destabilized after a critical P substitution of Si-adatom concentration due to high surface strain result in P-terminated (6√3 × 6√3) R 30º reconstruction.</span
Actuators in a robot system may become faulty during their life cycle. Locked joints, free-moving joints, and the loss of actuator torque are common faulty types of robot joints where the actuators fail. Locked and free-moving joint issues are addressed by many published articles, whereas the actuator torque loss still opens attractive investigation challenges. The objectives of this study are to classify the loss of robot actuator torque, named actuator torque degradation, into three different cases: Boundary degradation of torque, boundary degradation of torque rate, and proportional degradation of torque, and to analyze their impact on the performance of a typical 6-DOF robot (i.e., the IRB 120 robot). Typically, controllers of robots are not pre-designed specifically for anticipating these faults. To isolate and focus on the impact of only actuator torque degradation faults, all robot parameters are assumed to be known precisely, and a popular closed-loop controller is used to investigate the robot’s responses under these faults. By exploiting MATLAB-the reliable simulation environment, a simscape-based quasi-physical model of the robot is built and utilized instead of an actual expensive prototype. The simulation results indicate that the robot responses cannot follow the desired path properly in most fault cases.
The cryptographic hash functions are the most fundamental cryptographic concept. These functions are used as basic building blocks for digital signatures and message authentication. Boolean functions are the core of hash functions. These functions are expected to provide pseudo-randomness as well as input sensitivity. Cellular automata are a form of Boolean function that exhibits strong cryptography properties as well as chaotic behavior. This paper proposes a hash function, designed on the principle of cellular automata. The proposed algorithm is secure and meets the requirements for a successful hashing scheme. The hash function has strong statistical and cryptographic characteristics, according to the findings of the avalanche test and the National Institute of Standards and Technology (NIST) Statistical Test Suite. The modularity of different operations of this algorithm makes it suitable for a high-capacity processing environment to produce efficient performance.
Demand robust counterpart-open capacitated vehicle routing problem with time windows and deadline (DRC-OCVRPtw,d) model formed and explained in this paper, is the model used to find the minimum distance and the time needed for vehicles to transport garbage in Sukarami Sub-District, Palembang that consists of the time it takes for the vehicle to pass through the route. Time needed to transport garbage to the vehicle is called time windows. Combination of the thoses times is called deadline. The farther the distance passed by vehicle and the more garbage transported, the longer the deadline is needed. This DRC-OCVRPtw,d model is completed by LINGO 13.0 to obtain the optimal route and time deadline for Sukarami Sub-District. The model shows that the improved model of open vehicle routing problem involving the robustness, time windows and deadline can achieve the optimal routes that enable driver to save operational time in picking up the garbage compared to similar problem not involving no-time windows and deadline stated in previous research.
A gain modified CMOS Operational Transconductance Amplifier (OTA) for a 16 bit pipeline Analog-to-Digital Converter (ADC) is presented. The circuit is designed to be used for a high resolution and low sampling rate ADC. Gain boosting technique is implemented in the design to achieve high DC gain and settling time as required. Post layout simulations for a 5 pF load capacitance shows that OTA achieves a gain bandwidth of 161 MHz at a phase margin 93.14 o with 93.27 dB DC gain. The settling time for an OTA is 163 ns for 0.1 % accuracy to achieve final value and consume power about 4.88 mW from 5 V power supply.
p>With the intrusion of internet into the lives of every household and terabytes of data being transmitted over the internet on daily basis, the protection of content being transmitted over the internet has become an extremely serious concern. Various measures and methods are being researched and devised everyday to ensure content protection of digital media. To address this issue of content protection, this paper proposes an RGB image steganography based on sixteen-pixel differencing with n-bit Least Significant Bit (LSB) substitution. The proposed technique provides higher embedding capacity without sacrificing the imperceptibility of the host data. The image is divided into 4×4 non overlapping blocks and in each block the average difference value is calculated. Based on this value the block is classified to fall into one of four levels such as, lower, lower-middle, higher-middle and higher. If block belongs to lower level then 2-bit LSB substitution is used in it. Similarly, for lower-middle, higher-middle and higher level blocks 3, 4, and 5 bit LSB substitution is used. In our proposed method there is no need of pixel value readjustment for minimizing distortion. The experimental results show that stego-images are imperceptible and have huge hiding capacity.</p
In any integrated chip compulsory adders are required because first they are fast and second are the less power consumption and delay. And at the same time multiplication process is also used in various applications. So as the speed of multiplier increases then the speed of processor also increases. And hence we are proposing the Vedic multiplier using these adders. Vedic multiplier is an ancient mathematics which uses mainly 16 sutras for its operation. In this project we are using “urdhva triyagbhyam” sutra to do our process. This paper proposes the Vedic multiplier using the adders ripple carry adder(RCA) and carry look ahead adder(CLA) and puts forward that CLA is better than RCA.The major parameters we are simulating here are number of slices and delay. The code is written by using Verilog and is implemented using Xilinx ISE Design Suite.
p>In any integrated chip compulsory adders are required because first they are fast and second are the less power consumption and delay. And at the same time multiplication process is also used in various applications. So as the speed of multiplier increases then the speed of processor also increases. And hence we are proposing the Vedic multiplier using these adders. Vedic multiplier is an ancient mathematics which uses mainly 16 sutras for its operation. In this project we are using “urdhva triyagbhyam” sutra to do our process. This paper proposes the Vedic multiplier using the adders ripple carry adder(RCA) and carry look ahead adder(CLA) and puts forward that CLA is better than RCA.The major parameters we are simulating here are number of slices and delay. The code is written by using Verilog and is implemented using Xilinx ISE Design Suite.</p
span>The design of intelligent systems for analyzing information and predicting the epidemiological trends of the disease is rapidly expanding because of the coronavirus disease (COVID-19) pandemic. The COVID-19 datasets provided by Johns Hopkins University were included in the analysis. This dataset contains some missing data that is imputed using the multi-objective particle swarm optimization method. A time series model based on nonlinear autoregressive exogenou (NARX) neural network is proposed to predict the recovered and death COVID-19 cases. This model is trained and evaluated for two modes: predicting the situation of the affected areas for the next day and the next month. After training the model based on the data from January 22 to February 27, 2020, the performance of the proposed model was evaluated in predicting the situation of the areas in the coming two weeks. The error rate was less than 5%. The prediction of the proposed model for April 9, 2020, was compared with the actual data for that day. The absolute percentage error (AE) worldwide was 12%. The lowest mean absolute error (MAE) of the model was for South America and Australia with 3 and 3.3, respectively. In this paper, we have shown that geographical areas with mortality and recovery of COVID-19 cases can be predicted using a neural network-based model.</span
span>Susceptible exposed infectious recovered (SEIR) is a fitting model for coronavirus disease (COVID-19) spread prediction. Hence, to examine the effect of different levels of social distancing on the spreading of the disease, a variable was introduced in the SEIR equations system used in this work. We also used an artificial intelligence approach using a machine learning (ML) method known as deep neural network. This modified SEIR model was applied on the available initial spread data until June 25<sup>th</sup>, 2021 for the Hashemite Kingdom of Jordan. Without lockdown in Jordan, the analysis demonstrates potential infection to roughly 3.1 million people during the peak of spread approximately 3 months, starting from the date of lockdown (March 21<sup>st</sup>). Conversely, the present partial lockdowns strategy by the Kingdom was expected to reduce the predicted number of infections to 0.5 million in 9 months period. The analysis also demonstrates the ability of stricter lockdowns to effectively flatten the graph curve of COVID-19 in Jordan. Our modified SEIR and deep neural network (DNN) model were efficient in the prediction of COVID-19 epidemic sizes and peaks. The measures taken to control the epidemic by the government decreased the size of the COVID-19 epidemic.</span
span lang="EN-US">COVID-19 is a pandemic that has occurred in the world since 2019. Researchers have carried out various ways in dealing with this disease, starting from the screening stage to the stage of treatment and therapy for COVID-19 patients. As the gateway to the COVID-19 problem, screening has an essential role in a diagnosis that leads to appropriate treatment. In this paper, we will focus on the screening stage using digital image processing techniques, namely in calculating the area of white spots in the lungs of COVID-19 patients. The white patches are an early indication of how badly COVID-19 is attacking the patient. We use X-Ray Thorax image objects as research data in this paper. Although the current experimental results show that this method has a successful performance of 71.11%, it is pretty promising for further development due to its simplicity.</span
Social media platforms enable people exchange their thoughts, reactions, emotions regarding all aspects of their lives. Therefore, sentiment analysis using textual data is widely practiced field. Due to large textual content available on social media, sentiment analysis is usually considered a text classification task. The high feature dimension is an important issue that needs to be resolved by examining text meaningfully. The proposed study considers a case study of coronavirus (COVID) vaccination to conclude public opinions about prospects for vaccination. Text corpus of tweets is collected, published between December 12, 2020, and July 13, 2021 is considered. The proposed model is developed considering phase-by-phase data analysis process, followed by an assessment of important information about the collected tweets on coronavirus disease (COVID-19) vaccine using two sentiment analyzer methods and probabilistic models for validation and knowledge analysis. The result indicated that public sentiment is more positive than negative. The study also presented statistics of trends in vaccination progress in the top countries from early 2021 to July 2021. The scope of study is enormous regarding sentiment analysis based on keyword and document modeling. The proposed work offers an effective mechanism for a decision-making system to understand public opinion and accordingly assists policymakers in health measures and vaccination campaigns.
![Figure 2. CMOS realization of the VDGA [34, 35]](https://www.researchgate.net/publication/343366935/figure/fig2/AS:919774909440000@1596302835838/CMOS-realization-of-the-VDGA-34-35_Q320.jpg)
![Figure 1. Block diagram of a microwave amplifier [2]](https://www.researchgate.net/publication/328019909/figure/fig1/AS:834330628743170@1575931331664/Block-diagram-of-a-microwave-amplifier-2_Q320.jpg)
