Ibm Journal of Research and Development

Online ISSN: 0018-8646
Publications
Article
Since the announcement of the IBM System/3 in 1969, IBM has been incorporating leading-edge technology in products referred to as small general-purpose systems. With the many models of the System/3, System/32, System/34, and System/38, IBM has introduced many technological advances addressing the needs of diverse customers, from the novice, first-time user to the experienced user in the distributed data processing account. By identifying the goals, objectives, design themes, major salient features, and development constraints, this paper reviews and highlights the technical evolution of these products in terms of their systems layout, processor architecture, machine structure, and programming support.
 
Article
This paper describes the design, fabrication, and characterization of 0.1-µm-channel CMOS devices with dual n+/p+ polysilicon gates on 35-A gate oxide. A 2× performance gain over 2.5-V, 0.25-µm CMOS technology is achieved at a power supply voltage of 1.5 V. In addition, a 20× reduction in active power/circuit is obtained at a supply voltage of < 1 V with the same delay as the 0.25-micron CMOS. These results demonstrate the feasibility of high-performance and low-power room-temperature 0.1-µm CMOS technology. Beyond 0.1 µm, a number of fundamental device and technology issues must be examined: oxide and silicon tunneling, random dopant distribution, threshold voltage nonscaling, and interconnect delays. Several alternative device structures (in particular, low-temperature CMOS and double-gate MOSFET) for exploring the outermost limit of silicon scaling are discussed.
 
Article
Deep-submicron CMOS is the primary technology for ULSI systems. Currently, the state-of-the-art CMOS device has a 0.25-µm effective channel length and operates at 2.5 V. As the CMOS technology is extended into the deep submicron range, it is estimated that the next generation will have a nominal channel length of 0.15 µm with a supply voltage of ≤2 V. In this paper, two potential technologies with application to 1.X-V CMOS are presented. First, a bulk CMOS technology with the nominal channel length of 0.15 µm is described. It is next argued that because of issues related to power dissipation, such a device may face problems when operated at its maximum speed-density potential in high-performance logic chips. CMOS on a silicon-on-insulator (SOI) substrate offers circuits with lower power at the same performance. Such a CMOS technology, with channel lengths down to less than 0.1 µm, is described next. This technology is particularly useful for applications near a 1.0-V supply. We describe, for example, a 512Kb SRAM with an access time of less than 3.5 ns at 1.X V. The clear power-performance advantage of CMOS on SOI over that of CMOS on bulk silicon in the 1.X-V regime makes it the technology of choice for sub-0.25-µm CMOS generations.
 
Article
An overview is presented of our work to explore the extendibility of the silicon FET technology to the 0.1-µm-gate-length level. Self-aligned, n-channel, polysilicon-gated FETs were designed for operation at 77K, with reduced power-supply voltage. Direct-write electron-beam lithography was used to pattern all levels, while other processing followed established lines. Noteworthy results of the work included the observation of a clear manifestation of velocity overshoot, which contributed to achieving extrinsic transconductances above 940 µS/µm at 0.07-µm gate length. The measured switching delay of ring oscillators which contained 0.1-µm-gate-length devices was as low as 13.1 ps, with simulations showing potential for reduction to below 5 ps. Both the transconductance and the switching times are the best values observed for FETs to date-indicating continuing value in the scaling of FETs to dimensions well beyond those currently used.
 
Article
This paper presents an overview of the macro design, architecture, and built-in self-test (BIST) implementation as part of the IBM third-generation embedded dynamic random-access memory (DRAM) for the IBM Blue Logic® 0.11-µm application-specific integrated circuit (ASIC) design system (CU-11). Issues associated with embedding DRAM in an ASIC design are identified and addressed, including fundamental DRAM core function, user interface, test, and diagnosis. Macro operation and organization are detailed and contrasted with traditional DRAM designs. The use of BIST, a key enabler for embedded DRAM, is discussed while highlighting innovations required by the embedded DRAM.
 
Article
Systems-on-chips (SoCs) that combine digital and high-speed communication circuits present new opportunities for power-saving designs. This results from both the large number of system specifications that can be traded off to minimize overall power and the inherent low capacitance of densely integrated devices. As shown in this paper, aggressively scaled silicon-on-insulator (SOI) CMOS is a promising technology for SoCs for several reasons: Transistor scaling leads to active power reduction in the sub-50-nm-channel-length regime, standard interconnect supports the high-quality passive devices essential to communications circuitry, and high-speed analog circuits on SOI are state of the art in terms of both performance and power dissipation. We discuss the migration of a complete digital circuit library from bulk to SOI to prove that SOI CMOS supports ASIC-style as well as fully custom circuit design.
 
Article
High-resolution lithographic capability is required for the fabrication of fully scaled semiconductor devices at minimum dimensions of 0.5 µm to 0.25 µm—the prototype for the semiconductor logic and memory CMOS devices of the 1990s. Electron-beam exposure tools provide this capability. Fully scaled 0.5-µm test devices were fabricated using a modified EL-3 variable shaped-electron-beam system, while 0.25-µm ground-rule lithography was accomplished with a Gaussian round-electron-beam Vector Scan system. An important part of this technology is the selection of lithographic resist system and the process used for pattern definition and transfer. Twelve or more lithographic steps are often needed for circuit devices with the above minimum dimensions. For fully scaled applications, each one of these pattern levels must be defined by electron-beam lithography, and each level may require a specific lithographic resist. Thus, the electron-beam system and the resist process must be mutually compatible if the required resolution, feature size control, and pattern-level-to-pattern-level overlay accuracy are to be achieved. This paper discusses the successful integration of e-beam lithography and resist technologies and their application to CMOS device fabrication.
 
Article
Highly uniform step and termination structures on 4H- and 6H-SiC(0001) surfaces have been prepared via moderate annealing in disilane. Atomic force microscopy and dark-field low-energy electron microscopy imaging indicate single-phase terminations separated solely by half-unit-cell-height steps, driven by stacking fault energy. The atomic structure of 4H-SiC(0001)- $surd$ 3 $times$ $surd$ 3R30 $^{circ}$ -Si has been determined quantitatively by nanospot low-energy electron diffraction. The topmost stacking fault at the 4H surface has been found to be between the second and third bilayers.
 
Article
Semiconductor spintronics is a promising technology in which the spin states of electrons are utilized as an additional degree of freedom for device operation. One of its prerequisites is the ability to inject spin-polarized electrons into semiconductors. An overview is presented of recent progress in spin injection using an injector based on a crystalline CoFe/MgO(001) tunnel structure. The spin polarization of the electrons that were injected into a GaAs quantum-well light-emitting diode was inferred from electroluminescence polarization from the quantum well. Spin polarizations of 57% at 100 K and 47% at room temperature were obtained. The spin polarization was found to exhibit a strong dependence on bias and temperature, which can be explained on the basis of spin relaxation within the GaAs.
 
Article
Color filters with a wide color reproduction gamut and high transmittance were developed for 10.4-in.-diagonal 4096-color thin-film-transistor liquid crystal displays using pigment-dispersed photosensitive polymers. The transmission spectrum of each color pixel was designed in conjunction with other components such as backlight and polarizers in order to meet front-of-screen quality requirements. To improve screen quality, a low-resistivity common electrode was used, eliminating the top coating. A repair technique utilizing back-exposure was also developed to improve production yield. This pigment-dispersed-type color filter has the merits of a simple process, low fabrication cost, good uniformity, high reliability, and applicability to high-resolution displays. There is a problem involving deterioration of contrast ratio caused by the depolarization effect of the color filter. We measured depolarization factors for several pigments and showed that the yellow pigment was the major contributor. This depolarization effect has been minimized.
 
Article
A 157-dot-per-inch, 262K-color, 10.5-in.-diagonal, 1280 × 1024 (SXGA) display has been fabricated using a six-mask process with Cu or Al-alloy thin-film gates. The combination of high resolution and gray-scale accuracy has been shown to render color images and text with paperlike legibility. The low-resistivity gate metallization and trilayer-type TFTs with a channel length of 6-8 µm were fabricated with a six-mask process which is extendible to larger, higher-resolution displays. A combination of double-sided driving and active line repair was used so that open gate lines or data lines did not result in visible line defects. A flexible drive-electronics system was developed to address the display and characterize its performance under different drive conditions.
 
Article
Experimental transistors designed to operate above 1000 Mc are described and measurements of their electrical parameters discussed. The design is a diffused-base drift transistor structure with minimized bulk resistances and junction capacitances. Measurements of the short-circuit current gain (−h 21p ) with both emitter and collector reverse-biased, indicated that the passive circuit comprising extrinsic parameters only could produce a gain greater than unity. Interpretation of measurements using a simplified equivalent circuit shows that reduction of bulk resistances leads to an appreciable passive or feed-through current. An oscillator is described in which the transistors operated up to 1550 Mc.
 
Article
This paper presents the design of a 1K-byte random access memory using a cross-coupled complementary transistor switch (CTS) cell. The memory operates with a 4.25-V power supply and achieves a 15-ns access time with a power dissipation of 1.8 W. This paper also demonstrates the advantages of using the CTS cell to achieve high circuit density and good performance of memory arrays. Array attributes, cell selection criteria, and cell operation (both ideal and in situ) as well as design considerations are covered. Hardware performance is also briefly summarized.
 
Article
This paper describes a byte-oriented binary transmission code and its implementation. This code is particularly well suited for high-speed local area networks and similar data links, where the information format consists of packets, variable in length, from about a dozen up to several hundred 8-bit bytes. The proposed transmission code translates each source byte into a constrained 10-bit binary sequence which has excellent performance parameters near the theoretical limits for 8B/10B codes. The maximum run length is 5 and the maximum digital sum variation is 6. A single error in the encoded bits can, at most, generate an error burst of length 5 in the decoded domain. A very simple implementation of the code has been accomplished by partitioning the coder into 5B/6B and 3B/4B subordinate coders.
 
Article
The design of a large, very-high-speed ferrite memory is described. The memory has a capacity of 8192 words, 72 bits per word, and has a cycle time of 110 nanoseconds and an access time of 67 nanoseconds. The storage devices are miniature ferrite cores, 0.0075 by 0.0123 by 0.0029 inches, and are operated in a two-core-per-bit destructive read-out mode. A planar array geometry with cores resting on a single ground plane is used to control drive line parameters. Device switching speed and bit line recovery are treated as special problems. The design criteria and operational characteristics of the core, and the approach taken on the bit line recovery problem, are also presented.
 
Article
Photoemission electron microscopy and spot profile analyzing low-energy electron diffraction have been used to study the temperature-dependent growth of Ag islands on a Si(111) surface. Depending on growth temperature, various island shapes can be formed. At low temperatures, polygonic islands are formed, consisting of both Ag(001) and Ag(111) crystal orientations. At higher temperatures, islands consist mostly of Ag(111) orientation and are predominantly of triangular shape. As the islands grow, it is possible that the crystalline composition of an island changes. We observed that Ag(001)-oriented areas convert into areas of Ag(111) orientation. The rotational orientation of the Ag islands with respect to the substrate is explained by a modified coincidence-site lattice approach.
 
Article
By using a realistic tight-binding or LCAO (linear combination of atomic orbitals) model, detailed calculations of surface states, local densities of states, and theoretically simulated photoemission spectra have been carried out for two qualitatively distinct structural models for chemisorption of atomic hydrogen on Si(111)1×1 surfaces. In the low-coverage model, called the monohydride phase or Si(111):H, it is assumed that a single hydrogen atom sits on top of each surface Si atom, thus saturating all dangling bonds. In the high-coverage model, designated as the trihydride phase or Si(111):SiH 3 , SiH 3 radicals are bonded to the surface Si atoms. Due to the radically different atomic structures, the theoretical spectra of the two phases show striking differences. A comparison of the theoretical spectra with the ultraviolet photoemission spectra taken during hydrogen chemisorption on the quenched Si(111)1×1 surface clearly shows that at low coverages the monohydride is formed, while at high coverages the trihydride phase is formed. Formation of the monohydride phase is expected on simple chemical and structural considerations, and it has been observed on other Si surfaces. However, formation of the trihydride phase is unique to Si(111)1×1 and as such, it has important implications regarding the structure and stability of clean Si(111)1×1.
 
Article
Ethane is chemisorbed on W(111) with a sticking probability of ≈0.003. The carbon Auger spectrum at saturation co verage exhibits a two-peak structure similar to that for graphite, while the LEED (low energy electron diffraction) pattern is almost identical to that obtained for an atomically clean surface. Heating the surface to ≈773 K causes desorption of hydrogen and changes th e carbon Auger spectrum to a three-peak structure similar to that for tungsten carbide. After annealing, the LEED pattern is affected in different ways depending on the precise conditions, but it may in certain circumstances almost disappear. Exposure to ethylene produces a similar sequence of events. A large kinetic isotope effect is observed with the ratio of the sticking probabilities [S(C 2 H 6 )/S(C 2 D 6 ), W(111), T = 300 K] being ≈3. A similar ratio is measured for tungsten at T = 2500 K. These data suggest that chemisorption is dissociative in nature, probably involving the reaction C 2 H 6 → C 2 H 5 * + H → subsequent steps. Heating of the surface completely dissociates the adsorbed gas, leaving adsorbed carbon and gas phase hydrogen. In analogy with previous work on methane, we believe the large isotope effect suggests that the initial dissociation reaction is dominated by the tunneling of a hydrogen atom through a potential barrier. The implications of this conclusion for other saturated molecules will be discussed.
 
Article
This paper describes an all-CMOS 128Kb static random-access memory (SRAM) with emitter-coupled-logic (ECL) I/O compatibility which was designed for the air-cooled Enterprise System/9000™ processors. Access time of 6.5 ns is achieved using 0.5-µm channel length and 1.0-µm minimum geometry. Pipelining and self-resetting circuit techniques permit the chip to operate with cycle time less than access time. To achieve the high-reliability requirement in the TCM environment, a novel technique utilizing a sacrificial substrate is used to “burn in” chips prior to their attachment to the TCM.
 
Article
This paper reviews the salient features of the methods used for resolution and sensitivity enhancement in <sup>13</sup>C NMR spectra of solids. Performance characteristics of the unique variable-temperature cross-polarization magic angle spinning (VT-CPMAS) apparatus developed in our laboratory are given. We present results of structural studies on fluoropolymers using this technique, and discuss the issue of intensities in cross-polarized spectra. In addition, results of an ongoing VT-CPMAS study of polypropylene dynamics are given.
 
Article
Monolithic System Technology (MST) is a microelectronic circuit family consisting of high-density monolithic circuit chips on ceramic substrates. Using current-switch emitter follower (CSEF) logic, the technology is designed to provide a balanced reflection of cost and performance requirements. One version, MST-2, has been developed for use primarily in the middle range of System/370—the Models 145 and 155. The typical package usually consists of a single multi-circuit chip on a 16-pin module substrate, and the design embodies a number of recent interconnection and packaging developments that make it well suited to large-scale automated production.
 
Article
Excerpts of technical papers and magazine articles that serve the purposes of conventional abstracts have been created entirely by automatic means. In the exploratory research described, the complete text of an article in machine-readable form is scanned by an IBM 704 data-processing machine and analyzed in accordance with a standard program. Statistical information derived from word frequency and distribution is used by the machine to compute a relative measure of significance, first for individual words and then for sentences. Sentences scoring highest in significance are extracted and printed out to become the “auto-abstract."
 
Article
The physical chip design aspects of a 16-bit, single-chip, custom-macro-designed microprocessor are described. This microprocessor represents the IBM System Products Division's highest-density VLSI FET processor design to date. The chip is a complex arrangement of over 6500 VLSI circuits utilizing a state-of-the-art polysilicon-gate HMOS-1 (high-performance MOS) technology. The physical design of this chip required the use of a comprehensive methodology, from conception through completion. The methodology used in the design of the microprocessor was based on a hierarchical approach and is presented in this paper.
 
Article
This paper describes the boundary-scan and built-in self-test (BIST) functions of the IBM token-ring local area network (LAN) adapter chip. These functions present a number of unique features. First, less that 1% of available standard cell circuits were needed to implement these functions. Second, clocking methods used in different logical macros were merged into a comprehensive clocking sequence for self-test. Finally, asynchronous serial and parallel interfaces were provided to facilitate the communication between a test system and the chip's built-in test circuits. Although self-test and boundary-scan provide for an inexpensive higher-level package test, evaluation showed that automatically generated deterministic patterns provide a better-quality VLSI chip manufacturing test.
 
Article
This paper reviews the remarkable developments of the magnetic tunnel junction over the last decade and in particular, work aimed at demonstrating its potential for a dense, fast, and nonvolatile random access memory. The initial focus is on the technological roots of the magnetic tunnel junction, and then on the recent progress made with engineered materials for this device. Following that, we discuss the development of the magnetic random access memory (MRAM) technology, in which the magnetic tunnel junction serves as both the storage device and the storage sensing device. The emphasis is on work at IBM, including demonstrations of basic capabilities of the technology and work on a 16-Mb “product demonstrator” design in 180-nm node technology, which was targeted to be a realistic test bed for the MRAM technology. Performance and cost are compared with those of competing technologies. The paper also serves as an introduction to more specialized papers in this issue on MRAM device physics, magnetic tunnel junction materials and device characterization, MRAM processing, and MRAM design.
 
Article
Over the past twenty-five years we have witnessed the transition from germanium-based, individual transistors in their hermetically sealed enclosures to VLSI silicon devices interconnected in modular packages containing more than 50,000 logic circuits or as many as 500,000 bits of random-access memory. During this progression, manufacturing facilities producing these modern products have become more complex and technologically more sophisticated than those of any other industry. This review traces these fast-moving changes as they have occurred in IBM, emphasizing the continuous expansion of manufacturing skills and disciplines and how these, in turn, have contributed to the development of today's products and their respective manufacturing systems.
 
Article
IBM's role in the discovery of new lasers and in the development of their scientific potential is described. A brief survey is presented of laser-related projects conducted within IBM's Research Division laboratories at Yorktown Heights, NY, San Jose, CA, and Zurich, Switzerland.
 
Article
The IBM 1975 Optical Page Reader, specially built for the Social Security Administration, reads over 200 fonts from quarterly employer reports printed by electric and manual typewriters, business machines, and high-speed printers. Since the SSA has no control over the means used by employers to prepare the reports, many variations in print quality are present. This paper discusses the problems involved in planning and developing a system to read these reports and summarizes the design of the specialized video signal processing circuits and the character recognition logic that are used in the system. Two companion papers treat the latter topics in more detail. Also discussed in the paper is a management information system that permitted detailed analysis of experimental data and accelerated the development process.
 
Article
The design approaches which were used to specify feature measurement logic, recognition reference standards, and decision functions for a multifont character recognition system are discussed. The importance of an intuitive approach to design, as opposed to a fully automated approach, is emphasized. The nature of the problem required an intimate interaction between the designers, who investigated complex pattern recognition problems and proposed design alternatives, and the computer, which relieved the designer of routine testing and evaluation of the tentative design.
 
Article
This historical review covers IBM experiments in evaluating radiation-induced soft fails in LSI electronics over a fifteen-year period, concentrating on major scientific and technical advances which have not been previously published.
 
Article
The IBM X-ray lithography research and development program is outlined, from a personal perspective, covering the period from the inception of the program in 1980 through the development of IBM's own storage ring for X-ray production in 1992. The following aspects, among others, are discussed: origins of the program; acquisition of an X-ray port at Brookhaven National Laboratory; masks for X-ray lithography; development of special tooling for X-ray lithography, including a wafer stepper, a precision e-beam X-ray mask writing system, and a superconducting (dipole) electron synchrotron installed in the IBM Advanced Lithography Facility (ALF) in East Fishkill, New York. Key device programs were conducted to increase understanding of the X-ray lithography process and confirm its utility.
 
Article
Web 2.0 applications often rely on programming techniques that involve Ajax and mashups to provide rich user experiences and remixing of contents. Such techniques allow browser-based clients to communicate with the server using numerous units of information that are small compared with traditional (Web 1.0) applications for which the communication unit is typically an entire page. As a result, Web 2.0 applications tend to generate a larger number of smaller-sized requests. We describe a technique that aggregates multiple client requests of the same type and that processes them at the same time to accelerate Web 2.0 applications when the server is heavily loaded with a large number of client requests. We used a Representational State Transfer (REST) architecture style because they allow the server to detect the request type by examining a small portion in the Hypertext Transfer Protocol request. Due to this aggregation, the application server can process multiple client requests together. Request-invariant computations need to be done only once for a set of aggregated requests. Our experimental results with a simple application within a framework of WebSphere® sMash demonstrate that our technique can improve the throughput of client requests by more than a factor of 2 when we aggregate up to only four requests at a time.
 
Article
This paper describes Josephson Current Injection Logic (CIL) circuits. The design of the basic logic circuits, the two-and four-input OR and AND gates, and a timed inverter circuit, is presented in full detail and the logic delay and its sensitivity to design and fabrication parameters are investigated using detailed models of devices based on a 2.5-µm technology. The nominal logic delay of the circuits is estimated at 36 ps per gate for an average fan-in of 4.5 and fan-out of 3. The corresponding average power dissipation is 3.4 microwatts per gate. Finally, experimental delay measurements are presented for two-input and four-input OR and AND gates. The delay experiments are in excellent agreement with computer simulations.
 
Article
This paper presents an overview of the papers in this issue of the IBM Journal of Research and Development covering the design and implementation of the ®SELECTRIC System/2000 Typewriter/Printer products. The SELECTRIC System/2000 products comprise a nonimpact typewriter and printer, two impact typewriters, and an impact printer which use printwheel technology. The development approach for the SELECTRIC System/2000 products, which included design for automation, introduction of new technologies, and product development concurrent with manufacturing, was accomplished by the use of common architecture, hardware, and software.
 
Article
This paper describes the function and hardware structure of the Enterprise Systems Connection (ESCON™) Director™, an I/O switch capable of providing dynamic, nonblocking, any-to-any connectivity for up to 60 fiber optic links operating at 200 Mb/s. Optoelectronic conversion at the switch ports allows the switching of the fiber optic links to be done electronically. The establishment of paths in the switching matrix is done by means of a hard-wired, pipelined controller at a maximum rate of five million connections/disconnections per second. Routing information is provided in the header of data frames. The switch-port function, switching matrix, and matrix controller were implemented in the IBM 1-µm CMOS “standard cell” technology. The paper discusses the system interconnection philosophy, details of the data flow, the switch hardware architecture, the design methodology, and the approach to technology implementation.
 
Article
The call establishment procedure of the X.21 interface recommended by the International Telegraph and Telephone Consultative Committee (CCITT) has been validated as a test of a recently developed theory and of an implemented system for automated communications protocol validation. The test demonstrated the applicability of the validation technique and identified a number of points where the interface state diagram does not completely define the interface behavior.
 
Article
An algorithm is described that allows log(n) processors to sort n records in just over 2n write cycles, together with suitable hardware to support the algorithm. The algorithm is a parallel version of the straight merge sort. The passes of the merge sort are run overlapped, with each pass supported by a separate processor. The intermediate files of a serial merge sort are replaced by first-in first-out queues. The processors and queues may be implemented in conventional solid logic technology or in bubble technology. A hybrid technology is also appropriate.
 
Article
This paper describes the main characteristics of a new microprocessor-implemented 2400-bit/s data modem, the IBM 3863. In addition to the execution of signal processing tasks, the microprocessor provides a variety of other significant functions such as diagnostics and aids in network problem determination. The lack of hardware multiplication capability imposes certain constraints in the design of the signal processing algorithms. The analytical approach and computational techniques, based on the processing of signals in polar coordinates, which are used to circumvent these constraints, are described. It is shown in particular that timing phase control, carrier recovery, and adaptive equalization can be achieved at the receiver by processing only the phase of the sampled signal. Additionally, experimental results are presented which demonstrate the superiority of this design over conventional coherent demodulators.
 
Article
This paper describes the operational program of the IBM 2750 Voice and Data Switching System. The program runs in the supervisor unit of the two network controllers used in the 2750. This program controls: (1) the duplexing of the network controllers; (2) the switching network; (3) the data collection and transmission operations passing through the system, including interconnection with IBM System/360; (4) the on-line error handling and system testing. The IBM program uses all available core storage. It is flexible, is tailor-made to each customer's requirements, and runs continuously without customer assistance.
 
Article
This paper reviews the functions of private automatic branch exchanges (PABX's) and describes the organization of the IBM 2750 Voice and Data Switching System. This system has two main functional areas: (1) line switching, transmission and signaling, and (2) common control. The switching network uses a new integrated electronic crosspoint. The common control is performed by a built-in duplexed computer with stored programs dedicated to line switching. The IBM 2750 offers a variety of normal and advanced voice features, and some entirely new data features, and is designed for interconnection with an IBM System/360. Four companion papers describe the electronic switching network, the network control program, and the integrated crosspoint in greater detail.
 
Article
A tandem connection of terminals for a data collection system has certain desirable advantages over the more common radial configuration. To make use of these advantages, high-speed transmission links are required. This paper describes the transmission capability necessary for a high-speed digital data repeater when it is restricted to an in-house environment. The transmission techniques discussed are implemented in the IBM 2790 Data Communication System.
 
Article
The IBM 2305 Fixed Head Storage and IBM 3330 Disk Storage provide significant performance improvements over previously available disk facilities. Many of the improvements were made possible by the design of the control units, which are complex systems that integrate analog and digital interfaces. Definition of control unit requirements and characteristics permitted a large degree of commonality to be achieved between the two control units. The available design alternatives and implementations are discussed.
 
Article
The main features of the finite element semiconductor process simulator FEDSS are described, with emphasis on a recently added capability for generalized 2D oxidation with impurity redistribution in oxide and silicon. Examples are given that demonstrate the ability of the program to oxidize various structures using a model based on steady-state oxidant diffusion and incompressible viscous oxide flow. Impurity profiles and contours are also shown in both neutral and oxidizing ambients, along with several comparisons with data or with the program SUPREM II.
 
Article
A brief introduction introduction to a computer graphics characterization of cancer DNA sequences, as well as other biologically interesting sequences, is presented. The procedure described takes DNA sequences containing n bases and computes n two-dimensional real vectors. When displayed on a planar unit-cellular lattice, these characteristic patterns appear as a “DNA vectorgram,” C(n). Several demonstration plots are provided which indicate that C(n) is sensitive to certain statistical properties of the sequence of bases and allows the human observer to visually detect some important sequence structural properties and patterns not easily captured by traditional methods. The system presented has as its primary focus the fast characterization of the progression of sequence data using an interactive graphics system with several controlling parameters.
 
Article
Mathematical details of a two-dimensional semiconductor device simulation program are presented. Applicability of the carrier transport model to shallow junction bipolar transistors is discussed. Use of this program to optimize device structures in new bipolar technology is illustrated by presenting calculated device characteristics for variations in a few selected process conditions. Software links that automatically transfer data from a two-dimensional process simulation program and to a quasi-three-dimensional device equivalent circuit model generation program are also discussed.
 
Article
An experimental 2.0-volt low-power PowerPC 601™ Microprocessor built in a modified 3.6-volt, 0.6-µm IBM CMOS technology is described. By using unmodified tasks from the 3.6-volt design, a 3× power savings was realized while maintaining nearly the original performance. The use of selective scaling provides high performance at reduced power supply voltage. This technique, applicable to selected existing product designs, may allow early entry into the low-power market while minimizing new process development expense. The technique proposes hyperscaled reductions in specific electrical and physical parameters, while keeping horizontal layout rules unchanged. Static chip designs, which comprise the majority of 601 circuitry, respond well to the alterations. In addition, potential reliability detractors are deuced or eliminated. Challenges to this technique include I/O interfacing and minimizing leakages associated with low device thresholds. The 601 design and its base technology are described, a long with the experimental changes. The paper reviews the motivation behind low-power microprocessor development, alternative power-saving techniques being practiced, and opportunities for continued power reduction.
 
Article
A scanning tunneling microscope (STM) has been developed for operation over the full temperature range from 300 to 4.2 K. At room temperature, the instrument has been used to produce topographic images of grain structure in a copper-titanium alloy foil and of atomic structure on a Pt(100) surface. At low temperatures, the instrument can be used in a new spectroscopic mode, one which combines the high spatial resolution of the STM with the existing technique of electron tunneling spectroscopy. This new capability has been demonstrated by using the microscope to probe spatial variations in the superconducting character of a niobium-tin alloy film.
 
Article
The design features of a new automatic data processing machine for business applications, utilizing a random-access memory system, are described. Unlike the usual “batch” method of machine-processing business transactions, the technique used permits transfer of information between any two points in the system and allows multi-choice decisions according to the current status of the information. The “in-line” operational concept is discussed in detail and the data transfer routes and processing controls are shown. Employing punched-card input and printed-record output, the IBM 305 accounting machine is designed to handle 10,000 line-transactions per day.
 
Article
A 3072 × 32-stage TDI charge-coupled imaging device is described. It is believed to be the first reported TDI imager suitable for 300-pel-per-inch document scanning. Its large photocharge capacity gives it the noise performance and dynamic range required for high-quality gray-scale and color imaging in publishing and museum applications. Design options for high-resolution TDI imagers and the uniformity enhancement provided by the TDI mode of operation are discussed.
 
Article
A new set of printed-circuit technologies have been developed which permit construction of printed-circuit panels with several kilometers of controlled-impedance interconnections. Communications between internal layers of signal planes are achieved through small plated vias (drilled with a laser), while plated through-holes are used for the logic service terminals for cable terminations and module terminals. The panels are the largest currently known in the industry, 600 × 700 mm, and have the most layers, 20. This paper describes new LSI package designs which are achievable with the exceptional versatility that the new technologies provide. These technologies encompass vacuum lamination, electroless plating, photosensitive dielectric, laser drilling, automatic twisted-pair wire bonding, and other new approaches to printed circuits.
 
Top-cited authors
Raphael Tsu
  • University of North Carolina at Charlotte
Charles H. Bennett
Geoffrey Burr
Dana S. Scott
  • University of California, Berkeley
Cherie R Kagan
  • University of Pennsylvania