IET Circuits, Devices & Systems

The proposed research paper focuses on the study of fully depleted silicon (Si)-on-insulator negative capacitance metal oxide-semiconductor field-effect transistor (FDSOI-NC-MOSFET) performance for biosensor and digital circuit applications. The study mainly aims to use ferroelectric (FE) material to improve the performance and efficiency of FDSOI-NC-MOSFETs compared to conventional planar MOSFETs. Using TCAD software, the proposed device is simulated and analyzed under various parameter conditions (parameters like temperature, channel thickness, input supply voltages, and channel doping levels). Later, the proposed device is also designed for different biomolecular structures to analyze the selectivity and sensitivity behavior of the device. Sensitivity is the change in electrical characteristics in response to applied external stimuli or parameters like current and voltages. Variations in these parameters will affect the operating region of the device, thereby, the choice of parameters in achieving the best performance will depend on the operating conditions and device applications. NC-MOSFET with FE materials can obtain an acceptable on/off current ratio by lowering the off current and can achieve an adequate subthreshold swing (SS), thus, observed that the NC-MOSFET device has enhanced performance and transfer characteristics in comparison to planar MOSFET. For K = 4, at an input voltage of 0.25 V, the Ion/Ioff ratio was 6.21 × 10⁵ and the sensitivity was 6.20 × 10⁷ and at 0.5 V, these values rise to 8.07 × 10⁵ and 8.073 × 10⁷, respectively. Similarly for K = 6 and at an input voltage of 0.25 V, we observed an Ion/Ioff ratio is 1.5 × 10⁷ and a sensitivity of 1.52 × 10⁹. When the input voltage was increased to 0.5 V, the Ion/Ioff ratio improved to 2.07 × 10⁷ and the sensitivity increased to 2.073 × 10⁹. From these analyses, it is apparent that as the K-values increase at a given input voltage, both the Ion/Ioff ratio and the sensitivity also increase significantly. Finally, in this paper, we also demonstrated the implementation and simulation of digital logic gates using the proposed NC-MOSFET device, supporting circuit-level design applications.

The swift progression of electric vehicles (EVs) presents significant prospects for the enhanced integration of sustainable energy in the automotive industry. The installation technique and cost-effectiveness of on-board chargers (OBCs) have contributed to their increasing popularity as a feasible option for EVs. Moreover, there exists a growing demand within the automotive sector regarding bidirectional power flow solutions owing to the capacity of EVs to supply electricity to the electrical network. A crucial and integral component of the OBC is the dual active bridge (DAB) (an isolated bidirectional direct current [DC]–DC converter) satisfying the bidirectional power flow. The key aim of this work is to emphasize the essential role of the DAB within the realm of power electronic converters utilized in EVs. This paper introduces an analytical methodology for evaluating power losses and energy efficiency in a single-phase DAB. The validity of this approach is determined through a comparison between the computed energy efficiency and the empirical data obtained from a closed loop PI controlled 2.6 kW DAB model. The research article furthermore presents an analysis of leakage inductance on the efficiency and phase shift saturation in the empirical model. Subsequent comparative study evaluates the key properties of the paper, such as overall efficiency and settling time, across different loads. This inquiry offers valuable insights into the actual performance of these systems by a comparative analysis of simulation findings and real-world data obtained from hardware-based experiments.

An ultra-low power fully integrated CMOS current-mode amplitude shift keying (ASK) demodulator for radio frequency identification (RFID) transponders is presented. The proposed ASK demodulator performs signal shaping and amplification in the current domain to achieve higher power efficiency. Owing to a DC elimination technique, the employed current amplifier only amplifies the AC content of the envelope signal resulting in a significant reduction of power consumption. A feedforward correction method is also introduced to match the baseline of the amplified envelope signal with the threshold level of the output buffer, preserving the uniformity of data symbols. The proposed ASK demodulator is implemented in a standard 0.18 µm CMOS process consuming about 5.4 µW. A modulation index of 4% and a data rate of 800 Kbps is supported by the proposed demodulator which fully complies with international standards for passive RF communication.

The utilization of on-board chargers (OBCs) in electric vehicle (EV) has become increasing prevalent due to their configuration and cost-efficiency in the context of installation. Furthermore, the automobile industry is increasingly showing interest in bidirectional power flow because of the EV’s ability to provide energy back to the network. The paper presents an analytical method for designing the crucial elements of dual active bridge (DAB) with single-phase shift (SPS) modulation control. By comparing the estimated energy efficiency characteristics with measurements from a prototype 90-W single-phase DAB converter fitted with silicon carbide (SiC) MOSFETs, the robustness of this approach is exemplified and loss, and efficiency comparison analysis is carried out with conventional switching devices. Furthermore, this study presents a closed-loop voltage controller that effectively regulates the output voltage in the presence of significant variations in both the input line and load conditions. Finally, a comparison analysis is undertaken to evaluate important factors such as overall efficiency and settling time across different load circumstances. This analysis provides substantial perspectives toward the actual functionality of these systems through contrasts of simulation results with hardware-based results from the real world.

A compact harmonic tuning network (HTN) using a composite right-/left-handed (CRLH) transmission line (TL) is introduced. The CRLH TL offers purely imaginary harmonic load impedances, as it essentially functions as a one-port circuit at the harmonic frequencies, owing to a harmonics trap filter. In comparison to conventional HTNs based on microstrip line (MSL) or hybrid MSL and CRLH TL technologies, the proposed HTN features remarkable compactness while accommodating various operating classes of amplifiers. As a proof of concept, a 2-GHz 10-W gallium nitride (GaN) high electron mobility transistor (HEMT) power amplifier (PA) was fabricated, demonstrating drain efficiency of 84.6% and power added efficiency (PAE) of 78.4%. The novel HTN is expected to find applications in PAs for transmitter systems, where high efficiency and a minimal circuit footprint are of paramount importance.

Approximate computing is commonly employed in applications where accuracy is not crucial and aims to enhance circuit performance when inaccurate results are not challenging. The multipliers are power-hungry, and their approximation has been the target of research, especially by using approximate counters. In this study, a low-power and high-speed approximate 4 : 2 counter is proposed to add partial product (PP) bits. Also, a new partial product generation (PPG) is introduced by inserting errors in Karnaugh’s map to reduce the circuit complexity. The counter and PPG make a new radix-4-based 8 × 8 Booth multiplier, which is synthesized targeting a 32-nm carbon nanotube field-effect transistor (CNTFET) technology to determine the hardware characteristics. Looking at the normalized mean error distance (NMED), the multiplier has a 51.33% power–delay product (PDP) saving and acceptable accuracy. Besides, the multiplier which is configured by the counter and PPG accomplishes a 28.31% savings in the PDP × NMED in comparison with other approximate Booth multipliers. The case study of joint photographic experts group (JPEG) compression is performed, and the proposed multiplier outperforms references by higher quality results along with lower power consumption.

The localization of electromagnetic radiation leakage through cabin gaps is a critical and challenging aspect of electromagnetic compatibility (EMC) design for spacecraft with complex electromagnetic environments. This paper proposes a localization method based on synthetic aperture interferometric passive radiometry imaging. Electromagnetic radiation signals are measured at a certain distance from the spacecraft surface to form visibility samples. A Fourier transform pair between the visibility sample and the corrected brightness temperature for electromagnetic radiation leakage is established. The spacecraft surface electromagnetic leakage location image is obtained through the inverse Fourier transform. A sparse sampling method based on ant colony optimization was proposed to improve testing efficiency. The impacts of various factors, including positional parameters, positioning accuracy of the test antenna, scanning parameters, and measurement receiver amplitude/phase errors on the imaging results are analyzed. Experiments were conducted on a 1 m × 1 m × 1 m cabin with 51 holes on one surface, and the algorithm proposed in this paper was validated to effectively image and locate electromagnetic leakage points at different frequencies. The effectiveness of sparse sampling was also verified, with a localization accuracy of 90.2% and a testing time savings of 81.9%.

In the last decade, with the development of the electric vehicle industry and their acceptance in human societies, the participation plan of electric vehicles in supplying the load of the network has been taken into consideration. One of the requirements of this plan is the optimal location of the stations for these vehicles in the network so that they play an effective role in the operation of the network. In this regard, along with the construction of charging and discharging stations for electric vehicles, the construction of renewable sources in the network can play a complementary role for these stations. In this paper, the effect of using renewable resources as a supplement for smart charging stations and the placement of these stations to achieve technical and economic goals have been investigated. In order to manage the demand on the side of consumers and even out the load curve, the time of use mechanism as one of the demand response programs has been considered in this study. In this research, the improved nondominant sorting genetic algorithm is proposed to solve the problem, and the results of the proposed method are also compared with the conventional genetic and particle swarm optimization algorithms. All the simulations have been done in the MATLAB software and on the IEEE 33-bus network. Based on the obtained results, after the implementation of the proposed plan in the distribution network, the objective functions of the loss, voltage drop, and the total cost have been reduced by 13.6%, 58.7%, and 54.4%, respectively, compared to the base conditions of the network.

Wireless communication network in robotic telesurgery can be a huge advantage to smart healthcare systems that allows the surgeon to perform surgery on remote patients utilizing a surgical robot. It enables the surgical robotic manipulator to replicate the natural hand motions of the surgeon, allowing it to carry out operations with greater acuity and dexterity. This paper addresses the development of an intelligent controller to assure the safe functioning of a telesurgical robotic manipulator. The intelligent optimized, adaptive, and learning-based adaptive neuro-fuzzy fractional order sliding mode control (ANFFOSMC) controller is proposed to attain dexterity and acuity of the surgical manipulator for surgical interventions. The proposed controller for telesurgical system exhibits superior accuracy and performance compared to conventional controllers, as evidenced by reduced root mean square error (RMSE), integral squared error (ISE), and integral absolute error (IAE). The performance of the robot is evaluated using performance indices in the occurrence of uncertainties and external disturbances.

The spin transfer tunnel magnetic tunnel junction (STT-MTJ) has been widely used in computers, memory, and other fields because of its nonvolatility, low power consumption, and high capacity for integration, attracting significant attention in recent years. Building an accurate and efficient magnetic tunnel junction (MTJ) behavior model is necessary to accurately describe the physical changes caused by variations in external excitation and guide the design and optimization of magnetic random access memory (MRAM). In this paper, we construct a multiphysical field dynamic behavior model of a perpendicular STT-MTJ, introducing temperature and frequency effects based on the Landau–Lifshitiz–Gilbert–Slinbczewski (LLGS) equation and a macro model. Compared with the LLGS model, our model simplifies the calculation of the tunneling current and shortens the simulation time by ~40%. Compared with the macro model, ours model can more accurately reflect the dynamic physical changes in magnetoresistance under a small signal and transient excitation. Simulation modeling and experimental comparison verify the temperature and frequency dependencies of the model. Our model provides guiding significance for the design, application, and research of MTJ devices’ electromagnetic compatibility characteristics.

In this contribution, a chaos-based microcontroller electrocardiogram (ECG) signal acquisition-security-transmission system is proposed. It is designed based on a Novel 4Wings-4D Chaotic Oscillator (N4W4DCO) with a hyperbolic sine nonlinearity unbalanced. The classical nonlinear dynamics tools, such as 2D bifurcation and the highest Lyapunov exponent curves, basins of attraction, and power spectral density, help us see that the proposed chaotic oscillator generates periodic oscillations, intermittency + crisis routes to chaos, transient chaos, and the coexistence of 4/2 wings attractors just to name a few dynamics. The data generated using highly chaotic regime are tested using the well-known NIST TEST -800-22 Rev A and the results passed the test successfully. The N4W4DCO oscillator is embedded in an Arduino microcontroller where the discovered interesting dynamics are confirmed. A low-cost ECG acquisition circuit with an AD8232 ECG sensor is also designed and experimented. ECG signals are acquired and directly loaded into MATLAB-Simulink and are successfully encrypted with random data from the N4W4DCO in its chaos regime. The scrambled ECG signals from experiment are sent through an added white gaussian noise (AWGN) channel and thereafter received and decrypted. These results are promising and open the possibility of improving secure telemedicine transmission systems.

This study explores the impact of integrating a gallium arsenide (GaAs) pocket at the source and drain in a dual-material gate-oxide-stack double-gate tunnel field-effect transistor (DMGOSDG-TFET). The performance of this DMGOSDG-TFET, employing work-function engineering and gate-oxide-stack techniques, is compared with a GaAs pocket-doped DMGOSDG-TFET. Using the Silvaco Technology Computer-Aided Design tool, the comparison covers DC characteristics, analog/RF behavior, and circuit-level assessments. The research introduces an optimized heterostructure pocket-doped DMGOSDG-TFET to enhance DC characteristics, analog/RF performance, and DC/transient analysis. This novel architecture effectively suppresses ambipolarity, making it more suitable for current conduction. The incorporation of work-function engineering and a gate-oxide-stack approach enhances the device’s current driving capability, while the use of a highly doped GaAs pocket at the source and drain virtually eliminates ambipolar current conduction. Simulation results indicate that the proposed heterostructure device exhibits a high ON-current and switching ratio. For analog/RF applications, the optimized heterostructure device outperforms conventional DMGOSDG-TFET, offering higher cutoff frequency, transconductance, and other analog/RF parameters. Circuit-level performance is assessed using HSPICE, with a focus on the implementation of a resistive-load inverter for both proposed and conventional device topologies through DC and transient evaluations.

A staggering number of applications rely on the network architecture to carry out their tasks, which has led to a fast growth in wireless sensor networks (WSN). The possibility of harmful activity and data theft is growing as a result of the growth in devices and data. Thus, the network’s regular users have an impact on legitimate data delivery, which lowers customer happiness and worsens network standards. The data have been saved using a variety of security procedures that have been developed in past research studies. However, harmful activity continues to engage in its illegal operations despite their efforts to safeguard data transmission in the network. As a result, a number of recent research projects have concentrated on predicting innovative techniques and processes to offer security in WSN. In comparison to existing methods, this work attempted to offer an effective tighter security for WSN and suggested an ML-Based Secured Routing Protocol (MLSRP) for WSN with improved energy efficiency and overall performance. Energy efficiency is the main requirement of WSNs, hence a clustered network is proposed where the data are routed through the cluster head nodes. In this paper, a multicriteria based decision-making (MCDM) model is used by the MLSRP to perform data routing, clustering, and cluster head election while also analyzing a number of network characteristics that might affect the quality of a node, route, and data. In NS2 software, the suggested framework is put into practice and simulated. The results are then validated to gauge performance. The observed quantitative results reveal that the proposed MLSRP method attains an improved network lifetime by 5% and network throughput of 6%. It reduces energy consumption by 40%, curtails overhead to 37%, and minimizes end-to-end delay by 30% than the other conventional methods. The suggested framework performs better than others when its total performance is compared to that of older methods.

Accurate passenger flow forecasting is crucial in urban areas with growing transit demand. In this paper, we propose a method that combines advanced machine learning with rigorous time series analysis to improve prediction accuracy by integrating different datasets, providing a prescriptive example for passenger flow prediction in urban rail transit systems. The study employs advanced machine learning algorithms and proposes a novel prediction model that combines two-stage decomposition (seasonal and trend decomposition using LOESS–ensemble empirical mode decomposition (STL-EEMD)) and gated recurrent units. First, the STL decomposition algorithm is applied to break down the preprocessed data into trend terms, periodic terms, and irregular fluctuation terms. Then, the EEMD decomposition algorithm is employed to further decompose the irregular fluctuation terms, yielding multiple IMF components and residual residuals. Subsequently, the decomposed data from STL and EEMD are partitioned into training and test sets and normalized. The training set is utilized to train the model for optimal performance in predicting subway short-time passenger flow. The synthesis of these sophisticated methodologies serves to substantially enhance both the predictive precision and the broad applicability of the forecasting models. The efficacy of the proposed approach is rigorously evaluated through its application to empirical metro passenger flow datasets from diverse urban centers, demonstrating marked superiority in predictive performance over traditional forecasting methods. The insights gleaned from this study bear significant ramifications for the strategic planning and administration of public transportation infrastructures, potentially leading to more strategic resource allocation and an enhanced commuter experience.

Neuron circuits are the fundamental building blocks in the modern neuromorphic system. Designing compact and low-power neuron circuits can significantly improve the overall area and energy efficiencies of a neuromorphic chip architecture. Here, practical neuron circuits must overcome the variations arising from nonideal behaviors of synaptic devices, such as stuck-at-fault and conductance deviation. In this study, a compact leaky integrate-and-fire neuron circuit has been designed, with resilience to synaptic device state variations, for hardware implementation of spiking neural networks (SNNs). The proposed neuron circuit is simulated on the 0.35-μm Si complementary metal-oxide-semiconductor technology node by a series of circuit simulations based on HSPICE. The proposed circuit occupies a reduced area and exhibits low power consumption (14.7 µW per spike). Furthermore, the optimized circuit design results in a high degree of tolerance toward input-current variations arising from conductance-state variations in the synapse array. Hence, the proposed neuron circuit would be capable of substantially improving the area efficiency and reliability in the realization of the hardware-oriented SNN architectures.

Diabetic retinopathy (DR) is an ocular ailment that may lead to loss of vision and eventual blindness among individuals diagnosed with diabetes. The blood vessels of the retina, a layer of light-sensitive tissue located at the posterior aspect of the ocular globe, are adversely impacted. The identification of DR entails the utilization of retinal fundus images. The detection of any form of abnormality in the eye through raw fundus images poses a significant challenge for medical practitioners. Hence, it is imperative to engage in the processing of fundus images. This paper delineates several image processing techniques for DR images, including but not limited to, manipulation of brightness levels, application of negative transformation, and utilization of threshold operations. It focuses on elucidating the enhancement techniques that pertain to DR images, which aim to optimize the visual quality of said images in order to facilitate more facile disease detection. The process of detecting edges within DR images is also executed by Sobel edge detection algorithm. In order to successfully execute the aforementioned algorithms, expedient and contemporaneous systems are favored to account for the intricacies of the image processing calculations. The exclusive utilization of software techniques in order to fulfill the prerequisites of advanced algorithms presents a significant challenge, owing to the multifarious processes that are involved in their computation, coupled with an exigent requirement for high processing speeds. The proposed model is utilized to articulate a proficient model for the design and execution of field programable gate array (FPGA)-based image enhancement processes along with the Sobel edge detection algorithm upon DR images. Finally, a Internet Protocol chip is developed that can combine multiple image enhancement operations into a single framework with less complexity.

With the growing competition between the various manufacturers of electronic products, the quality of the products developed and the consequent confidence in the brand are fundamental factors for the survival of companies. To guarantee the quality of the products in the manufacturing process, it is crucial to identify defects during the production stage of an electronic device. This study presents a system based on traditional visual computing and new deep learning methods to detect defects in electronic devices during the manufacturing process. A prototype of the proposed system was developed and manufactured for direct use in the production line of electronic devices. Tests were performed using a particular smartphone model that had 22 critical components to inspect and the results showed that the proposed system achieved an average accuracy of more than 90% in defect detection when it was directly used in the operational production line. Other studies in this field perform measurements in controlled laboratory environments and identify fewer critical components. Therefore, the proposed method is a real-time high-performance system. Furthermore, the proposed system conforms with the Industry 4.0 goal that process system digitization is essential to improve indicators and optimize production.

Register file (Regfile), as the bottleneck circuit for processor data interaction, directly determines the computing performance of the system. To address the read/write conflict and timing error problems of register heap, this paper proposes a 5R4W high-timing reliability Regfile circuit design scheme. First, the scheme analyzed the principles of timing errors such as read/write conflicts, write errors, and read errors in the Regfile circuit; then adopted the timing separation method of independent control of the read/write process by clock double edges to solve multiport read/write conflicts, designed a mirror memory check circuit to avoid write errors caused by the word line delays, and used a phase-locked clock feedback structure to eliminate read errors caused by the data timing fluctuations; in the TSMC 7 nm FinFET process, a 64 × 74-bit 5R4W Regfile circuit was implemented using a fully customized layout. Experimental results show that the Regfile circuit has an area of 0.13 mm2 and consumes 5.541 mW. The circuit operates at a maximum frequency of 3.8 GHz at −40 to −125°C and 0.75 V, and is capable of detecting write errors caused by a clock jitter exceeding 30 ps or a frequency above 5 GHz.

A power amplifier design operating at 28 GHz for communication applications is presented in this paper. Analog predistorted technique is used to improve the linearity using a cold mode MOSFET linearizer. The paper reports +19.8 dBm of peak power at the output and power-added efficiency (PAE) of 17% is attained by the designed circuit. The 1-dB compression point linearity was +18.6 dBm. The adjacent channel power ratio (ACPR) simulations were performed for the different communication standards like 802_11n_40M, CDMA, IS-95, and 802_11n_20M. Design specification variations of the amplifier have been analyzed over five process corners and simulations were performed to validate compliance with standards and robustness of the designed circuit. Monte Carlo simulation were performed to assess the performance over statistical variability of PAE and power gain. It is believed that this linearization design and the verifications used are done for the first time on a 65-nm RFCMOS process.

In this work, the effects of the mini-local oxidation of silicon (LOCOS) field plate’s bottom physical profile on the devices’ breakdown performance are analyzed through technology computer-aided design simulations. It is indicated that the “abrupt” bottom profile could certainly do with an optimization. This paper introduces an effective process improvement method by etching bias power adjustment and time reduction. The upgradation of the field plate physical profile has been proved by transmission electron microscope cross-section analysis. The angle for the bottom surface of mini-LOCOS field plate θ2 is improved from 11.9° to 12.6°, and the thickness ratio of Hup/Hbottom (field plate oxide thickness for the upper and bottom, respectively) is increased from 71.8% to 76.6%. Finally, the optimized laterally diffused metal oxide semiconductor devices have been fabricated, and both figure of merit curves and safe operation area curves are measured. The specific on-resistance Ron,sp could achieve as low as 11.3 mΩ mm2, while breakdown voltage BVds,max arrives at 37.4 V, which is nearly 19.3% improved.

Multitarget tracking is prone to target loss, identity exchange, and jumping problems in the context of complex background, target occlusion, target scale, and pose transformation. In this paper, we proposed a target tracking algorithm based on the conditional adversarial generative twin networks, using the improved you only look once multitarget association algorithm to classify and detect the position of the target to be detected in the current frame, constructing a feature extraction model using generative adversarial networks (GANs) to learn the main features and subtle features of the target, and then using GANs to generate the motion trajectories of multiple targets, finally fuzing the motion and appearance information of the target to obtain the optimal match. The optimal matching of the tracked targets is obtained. The experimental results under OTB2015 and IVOT2018 datasets demonstrate that the proposed multitarget tracking algorithm has high accuracy and robustness, with 65% less jumps and 0.25% more accuracy than the current algorithms with minimal identity exchange and jumps.

A feedback field effect transistor (FBFET) with p-n-p-n structure benefits from a positive feedback mechanism. In this structure, the accumulated charges in its potential well and limitation of carrier flow by its internal potential barrier lead to superior electrical properties such as lower subthreshold swing (SS) and higher I ON / I OFF ratio in comparison with FinFET. Thus, FBFET is a promising alternative for digital applications such as logic inverters. In this paper, binary and ternary logic inverters are designed by using FBFETs with 40 nm channel length. The doping profile in the device plays an essential role and specifies the binary or ternary operation of the inverter. The inverter is analyzed by using a TCAD mixed-mode simulator. The results indicate the high value of 1010 for I ON / I OFF ratio with an extremely low SS (1 mV/decade). The voltage transfer characteristics of the inverter and its dependence on doping levels have been investigated. Also, the electrical properties of this inverter are compared with previous inverter counterparts.

A new approach to increasing the power-added efficiency (PAE) of a class E power amplifier (PA) is proposed in this paper. The PA operates at a 5 GHz frequency and a reactance compensation technique is utilized to maximize the bandwidth at the operating frequency. The driver stage creates either a half-wave rectified sine wave or a half-wave rectified sawtooth wave. By applying each one of the waves, the performance of the PA is examined and PAE = 70% and PAE = 50% is achieved. Plus, the output power of the PA is about 26 dBm when the DC voltage supply is 1.8 V. Advanced design system and TSMC 0.18 µm CMOS process are utilized to carry on the simulation.

High-order harmonic mixer is popular for frequency extension of spectrum analyzer (SA) from microwave to millimeter-wave or even terahertz band. The manufactures of SA usually offer expensive harmonic mixers where frequency extension is needed. In this work, low-cost designs of 2-port and 3-port W-band 8th harmonic mixers covering 75–110 GHz are proposed, and design method of two port mixer without frequency diplexer to separate local oscillator (LO) and intermediate frequency (IF) signals are first presented. These two kinds of mixers are compatible with almost all the current SAs with frequency extension options, which provides LO for the external harmonic mixer. The mixers are designed with planar microstrip lines and antiparallel Schottky diodes. The circuit of 2-port mixer includes the input broadband bandpass filter, diodes, output lowpass filter, and matching circuits. As for 3-port mixer, only an extra diplexer is needed to separate the IF signal and LO signal. The diplexer is composed of a planar semi-lumped lowpass and a highpass filter. The planar circuits are easily fabricated with low-cost print circuit board process on polytetrafluoroethylene substrate. The measured conversion loss of 2-port 8th harmonic mixer is from 20 to 26 dB, and 23 to 28 dB for 3-port mixer at full W-band. The good measured results indicate the proposed mixers are simple and effective.

This paper presents simulation and measurement results of a 2–4 GHz octave bandwidth interference suppression circuit. The circuit accomplishes the function of a tunable frequency notch through an interferometer architecture. The relative delay in the interferometer paths is varied with GaN monolithic microwave integrated circuit tunable delay lines. The delay is adjusted by varying the drain voltage of cold‐FET connected high electron mobility transistors acting as varactors. Two types of periodically‐loaded delay lines are compared: a uniform and a tapered design. A simple theoretical study, relating the delays and amplitudes in the interferometer circuit branches, is developed to inform the design. Two interference suppression hybrid circuits are implemented, and measurements demonstrate a 25–40 dB notch across the 2.24–4 GHz range for the uniform delay line, and 2.32–4.13 GHz for the tapered design. The return loss for both designs remains below 10 dB. Measurements with two tones spaced 0.5 and 1 GHz for varying tone power are performed to quantify suppression. The circuit can handle an input power of 37 dBm and maintains performance with two simultaneous 25 dBm tones spaced 0.5 GHz apart. Linearity is characterised with 10 MHz two‐tone measurements, and the circuit demonstrates a 3rd‐order intercept input power larger than 30 dBm for control biases above −12 V.