A 250-GHz corrugated transmission line with a directional coupler for forward and backward power monitoring has been constructed and tested for use with a 25-W continuous-wave gyrotron for dynamic nuclear polarization (DNP) experiments. The main corrugated line (22-mm internal diameter, 2.4-m long) connects the gyrotron output to the DNP probe input. The directional coupler, inserted approximately midway, is a four-port crossed waveguide beamsplitter design. Two beamsplitters, a quartz plate and ten-wire array, were tested with output coupling of 2.5% (-16 dB) at 250.6 GHz and 1.6% (-18 dB), respectively. A pair of mirrors in the DNP probe transferred the gyrotron beam from the 22-mm waveguide to an 8-mm helically corrugated waveguide for transmission through the final 0.58-m distance inside the NMR magnet to the sample. The transmission-line components were all cold tested with a 248 ± 4-GHz radiometer. A total insertion loss of 0.8 dB was achieved for HE(11) -mode propagation from the gyrotron to the sample with only 1% insertion loss for the 22-mm-diameter waveguide. A clean Gaussian gyrotron beam at the waveguide output and reliable forward power monitoring were achieved for many hours of continuous operation.
We apply a new triaxial antenna for microwave ablation procedures to an ex vivo bovine liver. The antenna consists of a coaxial monopole inserted through a biopsy needle positioned one quarter-wavelength from the antenna base. The insertion needle creates a triaxial structure, which enhances return loss more than 10 dB, maximizing energy transfer to the tissue while minimizing feed cable heating and invasiveness. Numerical electromagnetic and thermal simulations are used to optimize the antenna design and predict heating patterns. Numerical and ex vivo experimental results show that the lesion size depends strongly on ablation time and average input power, but not on peak power. Pulsing algorithms are also explored. We were able to measure a 3.8-cm lesion using 50 W for 7 min, which we believe to be the largest lesion reported thus far using a 17-gauge insertion needle.
A modified Cartesian feedback method called "frequency-offset Cartesian feedback" and based on polyphase difference amplifiers is described that significantly reduces the problems associated with quadrature errors and DC-offsets in classic Cartesian feedback power amplifier control systems.In this method, the reference input and feedback signals are down-converted and compared at a low intermediate frequency (IF) instead of at DC. The polyphase difference amplifiers create a complex control bandwidth centered at this low IF, which is typically offset from DC by 200-1500 kHz. Consequently, the loop gain peak does not overlap DC where voltage offsets, drift, and local oscillator leakage create errors. Moreover, quadrature mismatch errors are significantly attenuated in the control bandwidth. Since the polyphase amplifiers selectively amplify the complex signals characterized by a +90° phase relationship representing positive frequency signals, the control system operates somewhat like single sideband (SSB) modulation. However, the approach still allows the same modulation bandwidth control as classic Cartesian feedback.In this paper, the behavior of the polyphase difference amplifier is described through both the results of simulations, based on a theoretical analysis of their architecture, and experiments. We then describe our first printed circuit board prototype of a frequency-offset Cartesian feedback transmitter and its performance in open and closed loop configuration. This approach should be especially useful in magnetic resonance imaging transmit array systems.
High-performance and high-reliability low-noise GaAs MESFET's are studied from a practical point of view. By optimizing the structure and the configuration of GaAs FET's and by developing techniques to form a reproducible thick submicrometer gate, GaAs FET's having improved characteristics have been made. A mean minimum noise figure NF<sub>min</sub> of 0.89 dB, a standard deviation of 0.07 dB at 4-GHz CW and a pulse input power capability of more than 0.4 and 2 W, respectively, and a failure rate, supported by field data of less than 200 FIT have become practical.
Low-loss dichroic filters, a subgroup of frequency-selective
components, have been characterized by terahertz time-domain
spectroscopy in the region from 0.1 to 3 THz and with Fourier transform
spectroscopy. The two data sets are fully consistent. The time-domain
spectrometer is used to investigate the phase velocity behavior of
dichroic filters. The dichroic filters have various applications in
frequency mixing, multiplying, and diplexing experiments. In a novel
application, cascaded filters were used to limit the terahertz pulse
bandwidth and to monitor molecular transitions of atmospheric water
vapor in a selected frequency band
A 33-dBm P 0.1-dB single-pole double-throw antenna switch is designed and implemented using a standard 0.18-mum CMOS process at 1.8 GHz. An analysis shows a relation between parasitic junction capacitors and substrate resistance for low insertion loss (IL). The power-handling capability of the switch was also investigated through the voltage dividing mechanism through the substrate in the case of an ON-insertion loss-state NMOS switch implemented in a triple-well structure. A multistacked field-effect transistor (FET) structure with feed-forward capacitors in an Rx switch was chosen as the method of designing an antenna switch with high power-handling capability. Low IL of the switch in the multistacked FET structure is achieved by the optimization of layout and minimization of junction capacitors through the deep N -well bias. Allowance of a negative voltage swing at either the source or drain port is ensured by a floated well structure with a negatively biased P -well for each switch device of the multistacked FET structure. Intentional unequal division of the voltage swing level at each NMOS device by feed-forward capacitors with negative biases of the off-state switches helps to prevent channel formation in the off-state device. Experimental data shows that the proposed design achieves a 0.1-dB compression point at 33-dBm input power at 1.8 GHz with a negative bias supply to control the voltage at the off-state switches and the P -well of each device. The IL of the Tx switch is 0.5 and 0.73 dB at 900 MHz and 1.8 GHz, respectively. The Rx switch has 0.7- and 1.1-dB IL at 900 MHz and 1.8 GHz, respectively. In addition, a reliability issue related to antenna load mismatch was tested using a load-pull measurement setup.
We investigate the effects of a multigate-feeding structure on the gate resistance (R<sub>g</sub>) and RF characteristics of the high electron-mobility transistors (HEMTs). In this structure, the increase of R<sub>g</sub> with the gatewidth (W) is minimized; therefore, high maximum frequency of oscillation (f<sub>max</sub>) is achieved. Various numbers of gate feedings (N<sub>gf</sub>) using the air-bridge interconnections are adopted for fabricating the 0.1-mum depletion-mode metamorphic HEMTs. From these structures, we observe great reduction in R<sub>g</sub> with the increase of N<sub>gf</sub>, and their relationship is given by R<sub>g</sub>prop 1/[2middot(N<sub>gf</sub>-1)]<sup>2</sup>, where N<sub>gf</sub>=2,3,4,...; on the other hand, the effects of N<sub>gf</sub> on other small-signal parameters are negligible. Calculated cutoff frequency (f<sub>T</sub>) and f<sub>max</sub> from the extracted small-signal parameters all show good agreement with the measurement results. f<sub>T</sub> is slightly decreased with the increase of N<sub>gf</sub> due to the increase of gate-to-source capacitance. f<sub>max</sub> is, however, greatly increased with N<sub>gf</sub>, and this effect becomes greater at longer total gatewidth (W times number of gate fingers) . This is due to the smaller R<sub>g</sub> at greater N<sub>gf</sub> in the multigate-feeding structure. We propose that this gate-feeding structure provides a very effective way to suppress R<sub>g</sub> and maximize f<sub>max</sub> for the applications of the HEMTs with long W.
0.1-μm-gate-length GaAs MESFET distributed baseband integrated
circuits (ICs) that utilize an artificial-line-division technique and
three-dimensional transmission lines are described. The technique
reduces return loss of the distributed circuits at high frequencies, and
four-layer transmission-line structure reduces parasitic impedance
caused by the IC pattern shape and is suitable for the flip-chip bonding
module format. A gate-line-division distributed baseband amplifier IC
achieved input return loss of less than -13 dB and gain of 11.7 dB in
the 0-56 GHz band. A source-line-division distributed level-shift IC
achieved output return loss of less than -9.6 dB at high frequencies and
insertion loss of 2.7 dB in the 0-79 GHz band. Both results better the
performance of all reported GaAs MESFET distributed ICs
In this paper, we study the microwave properties of strongly
anisotropic materials made of orientated conducting wires. We have
developed a broad band method to determine their permeability μ||
parallel to the direction of the wires. We investigate the magnetic
properties of strongly anisotropic composites made of different types of
paramagnetic and ferromagnetic wires. A simple model is proposed to
account for the skin effect, and agrees with our observations. This
leads to a unique broad band method for measuring the permeability of
thin conducting wires
A compact ultra-wideband low-noise amplifier (LNA) with a 12.4-dB maximum gain, a 2.7-dB minimum noise figure (NF), and a bandwidth over 0.1-14 GHz is realized in a 0.13-μm CMOS technology. The circuit is basically an inductorless configuration using the resistive-feedback and current-reuse techniques for wideband and high-gain characteristics. It was found that a small inductor of only 0.4 nH can greatly improve the circuit performance, which enhances the bandwidth by 23%, and reduces the NF by 0.94 dB (at 10.6 GHz), while only consuming an additional area of 80 × 80 μm<sup>2</sup>. The LNA only occupies a core area of 0.031 mm , and consumes 14.4 mW from a 1.8-V supply.
The design of a traveling-wave amplifier (TWA) in 0.13-mum standard CMOS technology is presented. It is designed to maximize the gain-bandwidth product (GBP). An asymmetric cascode, coplanar waveguide (CPW), and loss compensation technique enables maximization of the TWA GBP. Design and modeling of 90-Omega CPW used to synthesize inductors of the TWA lines is presented. Simulations with a design kit and developed models for CPW show a 52-GHz bandwidth with a maximum power gain of 8.5 dB at 10 GHz for a 135-mW power consumption. Measurements up to 40 GHz confirm these results.
A novel ultra-wideband impulse radar architecture for 24-GHz-band short-range radar was developed using 0.13-mum InP high electron-mobility technology. The transmitter part generates an extremely wideband impulse from a pulse generator and then filters it through a bandpass filter. The obtained impulse had a full width at half maximum of 9 ps. Its frequency spectrum spread from dc to over 40 GHz and achieved sufficient flatness in the target band. The power amplifier (PA) for the transmitter had a gain of 15 plusmn0.1 dB, and the low-noise amplifier (LNA) for the receiver had a gain of 40 plusmn1 dB and a minimum noise figure of 1.9 dB. The achieved flatness of integration gain including the PA, LNA, and RF switch was less than plusmn1.2 dB. These RF circuits with gain flatness make a simple matched filter configuration possible without the use of a conventional correlator composed of a local oscillator. An ultra high-speed sample and hold circuit having an ultra-long hold time of more than 3 ns was also developed to detect the output pulses from the matched filter
A low conversion-loss monolithic frequency doubler has been developed for D-band signal generation in 0.13-μm SiGe BiCMOS technology. The circuit uses a single-transistor topology with a novel grounded-shielding structure, which can efficiently reduce the parasitic feedback effect between collector and base of a HBT to achieve frequency multiplication. The measurement results show that the doubler exhibits minimum ~3.2-dB conversion loss at the output frequency of 134 GHz with the efficiency of ~5.8% and maximum -1.4-dBm second-harmonic output power at the output frequency of 132 GHz with the efficiency of ~7%, respectively. Moreover, both input and output return loss are better than 10 dB for the input frequency from 64 to 69 GHz and the corresponding doubled output frequency range. In addition, the estimated rejection of the fundamental signal is better than 20 dB.
This paper presents designs and measurements of Ka-band single-pole single-throw (SPST) and single-pole double-throw (SPDT) 0.13-CMOS switches. Designs based on series and shunt switches on low and high substrate resistance networks are presented. It is found that the shunt switch and the series switch with a high substrate resistance network have a lower insertion loss than a standard designs. The shunt SPST switch shows an insertion loss of 1.0 dB and an isolation of 26 dB at >35 GHz. The series SPDT switch with a high substrate resistance network shows excellent performance with 2.2-dB insertion loss and isolation at 35 GHz, and this is achieved using two parallel resonant networks. The series-shunt SPDT switch using deep n-well nMOS transistors for a high substrate resistance network results in an insertion loss and isolation of 2.6 and 27 dB, respectively, at 35 GHz. For series switches, the input 1-dB compression point (1P<sub>1</sub>) can be significantly increased to with the use of a high substrate resistance design. In contrast, of shunt switches is limited by the self-biasing effect to 12 dBm independent of the substrate resistance network. The paper shows that, with good design, several 0.13- CMOS designs can be used for state-of-the-art switches at 26-40 GHz.
In this paper, a multiband wideband code-division multiple access/high-speed downlink packet access direct-conversion receiver to cover all six Third-Generation Partnership Project bands is implemented in a 0.13-μm CMOS process. To reduce the increase of chip size due to implementation of the multimode multiband RF transceiver integrated circuit, a new integrated inductor structure sharing an inner diameter, a proposed mixed-type dc offset correction circuit, and a stacked structure of metal-insulator-metal and MOS capacitors is proposed. These silicon area reducing techniques can decrease the chip size by up to 30%. The measured full-path receiver performance is a noise figure of >3 dB, third-order intermodulation intercept point of > -17 dBm, and second-order intermodulation intercept point of > +30 dBm for all six bands. Its current consumption, including a frequency synthesizer, is 45 mA at 2.8-V supply voltage.
On-chip transformers are best suited to lower the supply voltage in RF integrated circuits. A design method to achieve a high current gain with an on-chip transformer operating in resonance is presented. The proposed method will be proven analytically and has been applied to a downconversion mixer. Thereby part of the overall gain of the mixer has been shifted from the RF input stage to the transformer. Thus, the power consumption has been reduced and, in spite of the low supply voltage, moderate linearity has been achieved. Although the transformer has a bandpass behavior, a 3-dB bandwidth of 900 MHz at a center frequency of 2.5 GHz has been achieved. The downconversion mixer has been realized in 0.13-mum CMOS. It consumes 1.6 mW from a 0.6-V supply. A gain of +5.4 dB, a third-order intercept point of -2.8 dBm, an input 1-dB compression point of -9.2 dBm, and a single-sideband noise figure of 14.8 dB have been achieved
This paper presents the design and analysis of a 60-GHz 0.13-mum CMOS divide-by-three frequency divider (FD). The regenerative injection-locked technique is proposed to achieve divide-by-three function at millimeter-wave frequency. The novel level shifter is used to increase the overdrive voltage of the input switch of the loop divider such that the divider locking range and input sensitivity can be enhanced. The CMOS divide-by-three FD including the testing pads occupies the silicon area of 0.99 mm × 0.69 mm. Operated at 1.3 V, the CMOS divider consumes 13 mW of power. The measured locking range is 1.8 GHz around the input frequency of 59 GHz, and the phase noise of the output signal at 1-MHz offset is -131.36 dBc/Hz.
In this paper, analyses on sensitivity and link budget have been presented to guide the design of high-sensitivity noncontact vital sign detector. Important design issues such as flicker noise, baseband bandwidth, and gain budget have been discussed with practical considerations of analog-to-digital interface and signal processing methods in noncontact vital sign detection. Based on the analyses, a direct-conversion 5.8-GHz radar sensor chip with 1-GHz bandwidth was designed and fabricated. This radar sensor chip is software configurable to set the operation point and detection range for optimal performance. It integrates all the analog functions on-chip so that the output can be directly sampled for digital signal processing. Measurement results show that the fabricated chip has a sensitivity of better than -101 dBm for ideal detection in the absence of random body movement. Experiments have been performed successfully in laboratory environment to detect the vital signs of human subjects.
A beam-forming antenna module is demonstrated using an integrated CMOS beam-former chip and a simple two-metal layer printed circuit board at V-band. The beam-former circuit integrates an absorptive single-pole four-throw switch together with a 4 × 4 Butler matrix using a 0.13-μm CMOS process. The entire insertion loss of the integrated beam former integrated circuit (IC) is around 7.5 dB at 60 GHz, among which 3 dB is attributed to the Butler matrix. The overall phase error is within ±12%. The antenna module employs backside radiation structure using series-fed patch antenna arrays to suppress parasitic radiation. The measured radiation pattern shows good agreement with the simulation. To the best of our knowledge, this is the first demonstration of the beam-forming antenna module using a single-chip CMOS switched beam-former IC at V-band.
A 70-GHz broadband amplifier is realized in a 0.13- mum CMOS technology. By using five cascaded common- source stages with the proposed asymmetric transformer peaking technique, the measured bandwidth and gain can reach 70.6 GHz and 10.3 dB under a power consumption (P<sub>DC</sub>) of 79.5 mW. Within the circuit bandwidth, the maximum input and output reflection coefficients are -6.1 and -10.8 dB, respectively. The group delay variation is plusmn 12.0 ps, and the output 1-dB compression point is 0.2 dBm at 5 GHz. With the miniaturized transformer design, the occupied core area of the circuit is only ~ 0.05 mm<sup>2</sup> . This amplifier demonstrates a gain-bandwidth product of 231 GHz and a GBW/P<sub>DC</sub> up to 2.9 GHz/mW.
This paper presents the temperature effect on a Ku -band NMOS common-gate low-noise amplifier (CG-LNA). The temperature characteristics of an NMOS transistor and spiral inductors are obtained over the temperature range from 253 to 393 K. These results show that the optimal bias condition minimizes the transconductance and drain current temperature variations. Based on these results, a current-reused CG-LNA with good temperature performance is designed. At ambient temperatures, the CG-LNA has a measured power gain of 10.3 dB and a noise figure (NF) of 4.3 dB at 15.2 GHz, while consuming 4.5 mA from a 1.3-V power supply. When the temperature varies from 253 to 393 K, the CG-LNA has a power gain variation of 3 dB, NF variation of 2 dB , and dc power consumption variation of 11.9%. This paper is the first to report the temperature effect on Ku -band CG-LNAs.
This paper presents symmetric offset stack Marchand single and dual baluns that are designed, analyzed, and implemented in a 0.18-μm CMOS process to verify the feasibility. Both single and dual baluns achieve measured bandwidths (BWs) of over 110% and 90%, and insertion losses of less than 4.4 and 7.4 dB at 38 GHz. The amplitude imbalance and phase imbalance of single and dual baluns are less than 1 dB and 5° from 10 to 67 and 11 to 50 GHz, respectively. The baluns were used in three broadband balanced passive mixers, i.e., a single-balanced resistive mixer (SBRM), a star mixer, and a subharmonic gate pumped resistive mixer (SHPRM) design in a 0.13-μm CMOS technology. These mixers exhibit wide BWs over 14-45 GHz (105%), 18-54 GHz (100%), and 28-50 GHz (56%). The 14-45-GHz SBRM achieves a conversion loss of better than 12 dB at 7 dBm of local oscillator (LO) power. The LO to RF and LO to IF isolations are better than 30 dB. The chip area is 0.53 mm<sup>2</sup>. The star mixer achieves a conversion loss of better than 12 dB from 18 to 54 GHz, and LO to RF, LO to IF, and RF to IF isolations better than 35 dB at LO frequencies spanning 10-60 GHz. The chip area is 0.6 mm<sup>2</sup>. The SHPRM has a conversion loss of better than 11 dB from 28 to 50 GHz. The isolations are better than 31 dB and occupy a chip area of 0.61 mm<sup>2</sup>.
The insensitivity to gain and phase mismatches is investigated in a multiband double image rejection transmitter (DIRT). Although a direct in-phase/quadrature (I/Q) modulator architecture is simple, the I/Q gain and phase mismatches directly affect the image rejection ratio (IRR) over the operating frequencies. However, the DIRT has low sensitivity to a small I/Q phase mismatch, while the IRR is predominantly dependent on the IF gain mismatch. Furthermore, there is a region of insensitivity to both gain and phase mismatches in the DIRT. To characterize the mismatch effects of the DIRT, the IRR is theoretically analyzed and simulated at the system level. The proposed DIRT with sliding-IF is implemented on a 0.13-μm CMOS process to prove the insensitivity to the I/Q mismatch effects over 11-15-GHz multiband frequency ranges. For supporting the multiband functionality, frequency dividers-by-4/8/16 are utilized to generate 0.675-, 1.35-, and 2.7-GHz quadrature IF LO signals using 10.8-GHz RF local oscillator (LO) signal. The measurement results show that the in-band image rejection and LO leakage suppression are greater than 48.8 and 43.5 dBc, respectively, over the wideband frequency range. The output referred 1-dB compression point is obtained as high as - 4 dBm with a 1.5-V power supply. A multiband CMOS DIRT operating over Ku -band has not been previously reported.
Using ST 0.13-mum CMOS technology, a class A power amplifier has been developed for the global system for mobile communication in Europe. To solve the problem of low breakdown voltage in deep-submicrometer CMOS technology, the high-voltage/high-power (HiVP) device configuration is used. With the HiVP configuration, a large voltage can be divided by several devices so that the voltage drop on each device can be limited under the breakdown voltage. The measurement results show that the output power of 29.5 dBm has been achieved at the frequency of 900 MHz. The linear power gain reaches 11.5 dB and the maximum power-added efficiency is as high as 34.5%.
A discrete-time (DT) fast Fourier transform (FFT) processor is presented as an architectural approach to Fourier transform processing multigigahertz of spectral bandwidth. The processor is considered with the specific application of demodulating orthogonal frequency-division multiplexing (OFDM) modulation. The processor enables increased receiver linearity beyond that which is typically limited by the signal-to-noise-and-distortion ratio of high sample rate ADCs by performing OFDM demodulation in the DT domain. The circuit design of the prototype DT-FFT processor is presented and measurement results from the CMOS 0.13-μm test chip are shown. Results show that the processor demodulates OFDM at 1 GS/s with an accuracy better than 2.8% error vector magnitude while drawing 25 mW from a 1.2-V power supply. The processor demonstrates a measured dynamic range of 49 dB, a 13-dB improvement over that of a 6-bit quantization limited all-digital FFT processor and ADC pair. The DT-FFT is also shown to better tolerate large blocking signals with an 8-dB dynamic range improvement. The DT-FFT core area is 450 μm × 450 μm.
This paper presents an inductorless low-noise amplifier (LNA) design for an ultra-wideband (UWB) receiver front-end. A current-reuse gain-enhanced noise canceling architecture is proposed, and the properties and limitations of the gain-enhancement stage are discussed. Capacitive peaking is employed to improve the gain flatness and -3-dB bandwidth, at the cost of absolute gain value. The LNA circuit is fabricated in a 0.13-mum triple-well CMOS technology. Measurement result shows that a small-signal gain of 11 dB and a -3-dB bandwidth of 2-9.6 GHz are obtained. Over the -3-dB bandwidth, the input return loss is less than -8.3 dB, and the noise figure is 3.6-4.8 dB. The LNA consumes 19 mW from a low supply voltage of 1.5 V. It is shown that the LNA designed without on-chip inductors achieves comparable performances with inductor-based designs. The silicon area is reduced significantly in the inductorless design, the LNA core occupies only 0.05 mm<sup>2</sup>, which is among the smallest reported designs.
A compact and broadband 0.8-77.5-GHz passive distributed drain mixer using standard 0.13-mum CMOS technology is presented in this paper. To extend the operation bandwidth, a uniform distributed topology is utilized for wideband matching. This paper also analyzes the device size and number of stages for the bandwidth of the CMOS distributed drain mixer. To optimize the conversion gain performance of the CMOS drain mixer, a gate bias optimization method is proposed and successfully implemented in the mixer design. This mixer consumes zero dc power and exhibits a measured conversion loss of 5.5 plusmn1 dB from 0.8 to 77.5 GHz with a compact size of 0.67 0.58 mm<sup>2</sup> . The output 1-dB compression point is -8.5 dBm at 20 GHz. To best of our knowledge, this monolithic microwave integrated circuit has the widest operation bandwidth among CMOS wideband mixers to date with good conversion efficiency and zero dc power consumption.
This paper proposes a high-efficiency dual-band on-chip rectifying antenna (rectenna) at 35 and 94 GHz for wireless power transmission. The rectenna is designed in slotline (SL) and finite-width ground coplanar waveguide (FGCPW) transmission lines in a CMOS 0.13-μm process. The rectenna comprises a high gain linear tapered slot antenna (LTSA), an FGCPW to SL transition, a bandpass filter, and a full-wave rectifier. The LTSA achieves a VSWR=2 fractional bandwidth of 82% and 41%, and a gain of 7.4 and 6.5 dBi at the frequencies of 35 and 94 GHz. The measured power conversion efficiencies are 53% and 37% in free space at 35 and 94 GHz, while the incident radiation power density is 30 mW/cm<sup>2</sup> . The fabricated rectenna occupies a compact size of 2.9 mm<sup>2</sup>.
This paper presents a miniature 5-6-GHz 8 × 8 Butler matrix in a 0.13-μm CMOS implementation. The 8 × 8 design results in an insertion loss of 3.5 dB at 5.5 GHz with a bandwidth of 5-6 GHz and no power consumption. The chip area is 2.5 × 1.9 mm<sup>2</sup> including all pads. The 8 × 8 matrix is mounted on a Teflon board with eight antennas, and the measured patterns agree well with theory and show an isolation of >; 12 dB at 5-6 GHz. CMOS Butler matrices offer a simple and low-power alternative to replace eight-element phased-array systems for high gain transceivers. The applications areas are in high data-rate communications at 5-6 and at 57-66 GHz. They can also be excellent candidates for multiple-input-multiple-output systems.
We present a two-stage digitally controlled ring oscillator designed mainly for impulse-radio ultra-wideband (UWB) applications. Each basic stage utilizes a local positive feedback, allowing to achieve steady oscillation at low current consumption levels, and to extend the frequency tuning over an ultra-wide range. The frequency tuning is achieved via the control of the tail resistor in each stage. The circuit is fabricated in a 0.13-mum CMOS technology. It features full UWB coverage at slightly higher than 1.3-V supply voltage, -121.7-dBc/Hz phase noise at a 5.6-GHz carrier, and 10-MHz offset, and less than 5-mW power consumption for the digitally controlled oscillator core alone at 10.18-GHz maximum frequency under 1.3-V supply voltage.
This paper presents the design of a low-power single-full-band (3.1-10.6 GHz) noncarrier impulse-radio ultra-wideband (UWB) transmitter (TX) implemented in a commercial 0.18-μm CMOS technology. This UWB TX features fifth-order Gaussian derivative pulse shaping, integrated binary phase-shift keying modulation and 2.5-kV whole-chip electrostatic discharge (ESD) protection. Measurement shows full function with a very small die size of 0.25 mm<sup>2</sup>, extremely low power consumption of 0.14 pJ/p-mV, and an ultrashort pulsewidth of 394 ps. This ESD-protected UWB TX has the potential to support wireless streaming for gigabit/second applications.
This paper describes recent results obtained from the
monolithic-microwave integrated-circuit design activity at Chalmers
University, Goteborg, Sweden. The goal is to design all circuits needed
for the front end of a 60-GHz wireless local area network and to build
various system demonstrators. Some recent experimental results from this
activity like different 60-GHz amplifiers, a general-purpose IF
amplifier, a 60-GHz resistive mixer, and frequency multipliers are
reported in this paper. Parameters such as the gain, conversion loss,
noise figure, dc-power dissipation, as well as the model used in the
simulations are reported and discussed
We have developed a novel current-reuse configuration of a
front-end integrated circuit (IC), where the current can be reused in
the whole circuit blocks that are a low-noise amplifier, local
amplifier, and mixer. The power dissipation of the front-end IC is
reduced by the factor of three as compared to conventional front-end
ICs. Excellent RF performance such as conversion gain of 30 dB and noise
figure of 1.6 dB at 1.5 GHz is attained under the conditions of the
supply voltage and current of 3.6 V and 3 mA, respectively
Carrierless impulse radio ultra-wideband (IR-UWB) radios have attracted significant research interest due to their low system complexity and power consumption. Unfortunately, IR-UWB systems suffer from the difficulty in controlling the transmitted spectral mask because of process, voltage, and temperature variations. In this paper, a monolithic 3-5-GHz IR-UWB transceiver is presented that integrates both amplitude and spectrum tunability, thereby providing adaptable spectral characteristics for different data rate transmission. The noncoherent receiver employs a simplified low-power merged correlator, eliminating the need for a conventional sample-and-hold circuit. After self-correlation, the demodulated data is digitally synchronized with the baseband clock. The 4 mm<sup>2</sup> 0.13 μm CMOS transmitter and receiver consume 2.2 and 13.2 mW, respectively at the data rate of 100 Mb/s. The measured peak-to-peak transmitted pulse amplitudes are 240, 170, and 115 mV, with a tunable frequency range of 3.2-4.1 GHz. The receiver exhibits a maximum gain of 70 dB, noise figure of 8.6 dB, and the input 1-dB compression point of -28 dBm . With off-chip antennas, the transceiver achieves a bit error rate of 10<sup>-3</sup> at a sensitivity of -50 dBm.
A fully integrated ultra-broadband transmit/receive (T/R) switch has been developed using nMOS transistors with a deep n-well in a standard 0.18-mum CMOS process, and demonstrates unprecedented insertion loss, isolation, power handling, and linearity. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET's parasitic capacitances to synthesize artificial transmission lines, which result in low insertion loss over an extremely wide bandwidth. Negative bias to the bulk or positive bias to the drain of the MOSFET devices with floating bulk is used to reduce effects of the parasitic diodes, leading to enhanced linearity and power handling for the switch. Within dc-10, 10-18, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0, and 2.5 dB and isolation between 32-60, 25-32, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. The new CMOS T/R switch has a die area of only 230 mumtimes250 mum. The achieved ultra-broadband performance and high power-handling capability, approaching those achieved in GaAs-based T/R switches, along with the full-integration ability confirm the usefulness of switches in CMOS technology, and demonstrate their great potential for many broadband CMOS radar and communication applications
In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the V -band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-mum CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are -85.2 and -90.9 dBc/Hz, respectively. The reference spur level of -40.16 dBc is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance V -band applications.
A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18-mum SiGe BiCMOS technology for Q -band (30-50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an IIP<sub>3</sub> of -13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8-44 GHz. The rms gain and phase errors are les1.2 dB and les8.7deg for all 4-bit phase states at 30-50 GHz. The beamformer also results in les0.4 dB of rms gain mismatch and les2deg of rms phase mismatch between the four channels. The channel-to-channel isolation is better than -35 dB at 30-50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is 1.4times1.7 mm<sup>2</sup> including all pads and CMOS control electronics.
This chapter presents the detailed design and analysis of a CMOS short-range automotive pulse–radar receiver (RX) front-end operating in the UWB band from 22 to 29 GHz. Various design techniques are introduced in order to boost circuit performance at frequencies around only half of the transit (or unity current-gain) frequency, fT, of the transistor (f
T ≈ 55 GHz for 0.18 µm CMOS). An interference-reduction scheme is also presented that allows efficient use of the allocated power-constrained spectrum, while minimizing the interference with other systems operating in the same frequency range. Circuit techniques used in the UWB RX front-end design enable the radar sensor to potentially achieve a high range resolution and detect objects at a close range, thereby demonstrating suitability for integration in short-range radar systems.
This paper presents a 20-32-GHz wideband BiCMOS mixer with an IF bandwidth of 12 GHz. The mixer utilizes an inductive peaking technique to extend the bandwidth of the downconverted IF signal. To our knowledge, the proposed mixer achieves the widest IF bandwidth using silicon-based technologies in K-band. Analytical expressions for the conversion gain and output noise of the proposed mixer are presented. The wideband mixer is implemented using 0.18-μm BiCMOS technology and occupies an area of 0.19 mm<sup>2</sup>. It achieves a conversion gain of 3 dB, a noise figure between 10.5 and 13.0 dB, and an IIP3 higher than 0.5 dBm with a power consumption of 18 mW from a 1.8-V supply.
A downconversion double-balanced oscillator mixer using 0.18-mum CMOS technology is proposed in this paper. This oscillator mixer consists of an individual mixer stacked on a voltage-controlled oscillator (VCO). The stacked structure allows entire mixer current to be reused by the VCO cross-coupled pair to reduce the total current consumption of the individual VCO and mixer. Using individual supply voltages and eliminating the tail current source, the stacked topology requires 1.0-V low supply voltage. The oscillator mixer achieves a voltage conversion gain of 10.9 dB at 4.2-GHz RF frequency. The oscillator mixer exhibits a tuning range of 11.5% and a single-sideband noise figure of 14.5 dB. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO. This oscillator mixer requires a lower supply voltage and achieves a higher operating frequency among recently reported Si-based self-oscillating mixers and mixer oscillators. The mixer in this oscillator mixer also achieves a low power consumption compared with recently reported low-power mixers
An experimental demodulator suitable for ultra-low-voltage and low-power wireless applications is presented in this paper. To alleviate the stringent design constraints, discrete-time frequency-shift keying (FSK) is employed in this design. The proposed demodulator is composed of limiting amplifiers (LAs), low-pass filters (LPFs), and discrete-time quadricorrelators. For circuit implementations, negative-feedback source-degeneration gain cells are adopted in the LAs for low-voltage operations, while the LPFs are realized by a Sallen-Key structure with differential difference amplifiers for reduced power consumption and chip area. As for the quadricorrelators, delay cells are utilized in the discrete-time differentiator and the baseband signals are finally detected for logic recognition. Using a standard 0.18-mum CMOS process, the proposed demodulator is implemented for demonstration. Operated at a 0.6-V supply voltage, the fabricated circuit consumes a dc power of 2.4 mW. With a data rate of 1 Mb/s and a modulation index of 0.32, the measured bit error rates for FSK and Gaussian FSK schemes are 0.333% and 1.036%, respectively, at an IF frequency of 2 MHz.
This paper presents the structure of a high-selectivity bandpass filter that is fabricated on low-resistivity silicon substrate with a commercial CMOS technology. The filter is constructed using crossed coplanar waveguide (CPW) lines and metal-insulator-metal capacitors to ensure that it has the desired passband characteristics. An adjustable capacitor between the input and output ports is employed to form a capacitive cross-coupled path, yielding two transmission zeros in the lower and upper stopbands, respectively. Additionally, the coupling mechanism can be modified by turning on or off the gate of an nMOS transistor to adjust the positions of the transmission zeros by applying an externally controlled voltage. To obtain a low passband loss and to minimize the chip size, high-impedance CPW transmission lines are adopted. Our analysis indicates that the CPW line possesses more advantages than the preferred stacked-ground CPW line for constructing the proposed filter. A very compact X -band experimental prototype with a size of 0.88 ?? 0.54 mm<sup>2</sup> was designed and fabricated. The measurements reveal an insertion loss of less than 3.2 dB in the passband, which is from 10.6 to 12.7 GHz, and rejection levels greater than 35 dB at the designed frequencies of transmission zeros. Moreover, the lower and upper transmission zeros can be shifted from 5 to 6.5 GHz and from 18 to 21.4 GHz, respectively, by changing the controlled voltage.
A triple-modulus phase-switching prescaler for high- speed operations is presented in this paper. By reversing the switching orders between the eight 45deg-spaced signals generated by the 8 : 1 frequency divider, the maximum operating frequency of the prescaler is effectively enhanced. With the triple-modulus switching scheme, a wide frequency covering range is achieved. The proposed prescaler is implemented in a 0.18-mum CMOS process, demonstrating a maximum operating frequency of 16 GHz without additional peaking inductors for a compact chip size. Based on the high-speed prescaler, a fully integrated integer-N frequency synthesizer is realized. The synthesizer operates at an output frequency from 13.9 to 15.6 GHz, making it very attractive for wideband applications in Ku-band. At an output frequency of 14.4 GHz, the measured sideband power and phase noise at 1-MHz offset are -60 dBc and -103.8 dBc/Hz, respectively. The fabricated circuit occupies a chip area of 1 mm<sup>2</sup> and consumes a dc power of 70 mW from a 1.8-V supply voltage
Utilizing a standard 0.18-mum CMOS process, a receiver frontend and a local oscillator (LO) module are implemented for RF applications at the 24-GHz industrial, scientific, medical band. The proposed frontend is composed of a three-stage low-noise amplifier, a down-conversion mixer, and IF amplifiers. With an IF frequency of 4.82 GHz, the fabricated circuit demonstrates a conversion gain of 28.4 dB and a noise figure of 6.0 dB while maintaining an input return loss better than 14 dB. The measured P <sub>in</sub> <sub>-</sub> <sub>1dB</sub> and IIP<sub>3</sub> of the receiver frontend are -23.2 and -13.0 dBm, respectively. In addition, a circuit module, which generates the required dual down-conversion LO signals, is also included in this study. The proposed LO generator consists of a 19-GHz low-phase-noise voltage-controlled oscillator (VCO), a 4 : 1 frequency divider, and a quadrature phase-tuning circuit. From the measurement results, the VCO exhibits a tuning range of 850 MHz and a phase noise of -110 dBc/Hz at 1-MHz offset frequency. Operated at a supply voltage of 1.8 V, the current consumptions for the receiver frontend and the LO generator are both 30 mA.
We demonstrated Ku-band (12-20 GHz) Si MOSFET monolithic
amplifiers with on-chip matching networks. In these amplifiers, we used
3-μm-thick Al-metal transmission lines on 8-μm-thick
polyimide-SiON-SiO<sub>2</sub> isolation layers for the matching
networks. The amplifier showed a gain of 6-10 dB and a noise figure (NF)
of 3.5-4 dB up to about 20 GHz, the highest gain and lowest NF yet
reported for MOSFET amplifiers at this frequency. We also clarified the
lossy on-chip inductor effect on the gain and noise performance of the
An RF front-end transceiver is implemented in standard 0.18-μm CMOS for V2.1 Bluetooth applications. All signal detection and gain calibrations are realized without the need of baseband control, but using an incoming Gaussian frequency-shift keying signal detection mechanism, auto low-noise amplifier gain mode selection, and autogain calibration with a combined programmable gain amplifier/received-signal-strength indicator function. Moreover, a simple control interface between transceiver and baseband is designed. The differential error vector magnitude performance of the transmitter is less than 6%, and a less than 7.5-dB system noise figure is achieved in the receiver. Continuous current consumptions in receiver and transmitter are 32 and 42 mA, respectively, with a 1.8-V internal regulator voltage.
A novel design and performance of a power MOS transistor for RF system-on-chip applications are reported. The power MOS transistor with high breakdown voltage is integrated into 0.18-μm CMOS technology with only one additional mask. By an optimized design considering all aspects of DC and RF performances, a power MOS transistor with 16-GHz cutoff frequency and 24-GHz maximum oscillation frequency has been demonstrated. In addition, the power gain is 12 dB at 2.4 GHz with power-added efficiency of 50%. In this study, the device architectures that include drain engineering, substrate engineering, and gate scaling are investigated comprehensively.
A merged-diffusion dual-gate CMOS device model is presented in this paper. The proposed large-signal model consists of two intrinsic BSIM3v3 nonlinear models and parasitic components. The parasitic elements, including the substrate networks, the distributed resistances, and the inductances, are extracted from the measured S-parameters. In order to verify the model accuracy, a cascode configuration with the proposed dual-gate device is employed in a low-noise amplifier. The dual-gate model is also evaluated with power sweep and load-pull measurements. In addition, a doubly balanced dual-gate mixer is successfully demonstrated using the proposed model. The measured results agree with the simulated results using the proposed device model for both linear and nonlinear applications. The advanced large-signal dual-gate CMOS model can be further used as an RF sub-circuit cell for simplifying the design procedure.
In this paper, a transimpedance amplifier (TIA) with a tunable 3-dB bandwidth is presented for optical communications. The proposed TIA is composed of two cascaded stages in which an input network with inductive peaking elements is employed in the first stage for broadband operations while a modified distributed amplifier is utilized as the second stage for enhanced transimpedance gain. In addition, a feedback loop is incorporated as the bandwidth-tuning mechanism. By tuning the bandwidth of the TIA, optimum circuit operation with lowest bit error rate (BER) can be achieved in the receiver frontend for high-speed data transmission. The proposed circuit is implemented in a 0.18-μm CMOS process. Consuming a dc power of 33.3 mW forms a 1.8-V supply, the fabricated TIA exhibits a transimpedance gain of 47.8 dB??Ω and a variable 3-dB bandwidth from 6.2 to 10.5 GHz. Provided a 2<sup>11</sup> -1 pseudorandom bit sequence at 9-15 Gb/s, a BER less than 10<sup>-12</sup> is demonstrated experimentally by the TIA with the bandwidth tuning mechanism.
A dual-band switchable harmonic receiver for downconverting the industrial-scientific-medical and local-multipoint-distribution-service bands at 24 and 31 GHz is proposed in this paper. The front end utilizes a new technique for band selection. Mathematical formulation, including the effect of mismatches, for the new switchable harmonic receiver is provided in this paper. In addition, new circuit techniques for the low-noise amplifier and millimeter-wave mixer implementations are presented. The receiver is implemented using 0.18-μm BiCMOS technology with a total power consumption of 60 mW. Measurements show a band rejection higher than 43 dB, gain of 21 and 18 dB, NF lower than 8 and 9.5 dB, and third-order intercept point of -18 and -17 dBm for the 24- and 31-GHz frequency bands, respectively.