IEEE Transactions on Electron Devices

Published by Institute of Electrical and Electronics Engineers
Online ISSN: 0018-9383
Publications
Article
The theory, design, and experimental results of a wideband 140-GHz 1-kW pulsed gyro-traveling-wave amplifier (gyro-TWA) are presented. The gyro-TWA operates in the HE(06) mode of an overmoded quasi-optical waveguide using a gyrating electron beam. The electromagnetic theory, interaction theory, design processes, and experimental procedures are described in detail. At 37.7 kV and a 2.7-A beam current, the experiment has produced over 820 W of peak power with a -3-dB bandwidth of 0.8 GHz and a linear gain of 34 dB at 34.7 kV. In addition, the amplifier produced a -3-dB bandwidth of over 1.5 GHz (1.1%) with a peak power of 570 W from a 38.5-kV 2.5-A electron beam. The electron beam is estimated to have a pitch factor of 0.55-0.6, a radius of 1.9 mm, and a calculated perpendicular momentum spread of approximately 9%. The gyro-amplifier was nominally operated at a pulselength of 2 μs but was tested to amplify pulses as short as 4 ns with no noticeable pulse broadening. Internal reflections in the amplifier were identified using these short pulses by time-domain reflectometry. The demonstrated performance of this amplifier shows that it can be applied to dynamic nuclear polarization and electron paramagnetic resonance spectroscopy.
 
Article
We present a novel structure for the back-side readout silicon photomultipler (SiPM). Current SiPMs are front-illuminated structures with front-side readout, which have relatively small geometric fill factor leading to degradation in their photon detection efficiency (PDE). Back-side readout devices will provide an advantageous solution to achieve high PDE. We designed and investigated a novel structure that would allow back-side readout while creating a region of high electric field optimized for avalanche breakdown. In addition, this structure has relatively high fill factor and also allow direct coupling of individual micro-cell of the SiPM to application-specific integrated circuits. We will discuss the performance that can be attained with this structure through device simulation and the process flow that can be used to fabricate this structure through process simulation.
 
Article
We report a novel Si/Si<sub>1-x</sub>Ge<sub>x</sub> channel with improved noise, current drivability, and reliability using a buried Si<sub>0.99</sub>C<sub>0.01</sub> which can induce higher channel strain for the same Ge concentration. High-k dielectrics on Si/Si<sub>1-x</sub>Ge<sub>x</sub>. with buried Si<sub>0.99</sub>C<sub>0.01</sub> show lower charge trapping, better leakage current distribution and less ftathand voltage shift. Si/Si<sub>1-x</sub>Ge<sub>x</sub>. channel p-MOSFET with the buried Si<sub>0.99</sub>C<sub>0.01</sub> shows drive current improvement of up to 20% and better noise immunity.
 
Article
Highly thermally stable Ni germanide technology for high performance germanium metal-oxide-semiconductor field-effect transistors (Ge MOSFETs) is proposed, utilizing Pd incorporation into Ni germanide. The proposed Ni germanide shows not only the improvement of thermal stability but also the reduction of hole barrier height, which can improve the device on-current by reducing the Ni germanide to p+ source/drain contact resistance. The proposed Ni germanide showed a stable sheet resistance of up to 500<sup>deg</sup>C 30-min postgermanidation annealing due to the suppression of agglomeration and oxidation of Ni germanide and the diffusion of Ni and Ge atoms by the incorporated Pd. Therefore, the proposed Ni<sub>0.95</sub>Pd<sub>0.05</sub> alloy could be promising for the high mobility Ge MOSFET applications.
 
Article
This paper describes potential design and transport property of a 0.1-μm n-MOSFET with asymmetric channel profile, which is formed by the tilt-angle ion-implantation after gate electrode formation. The relation between device performance and transport property of the asymmetric 0.1-μm device is explored by Monte Carlo simulations, and measured electrical characteristics. The self-consistent Monte Carlo device simulation coupled with a process simulator reveals higher electron velocity at the source end of the channel and velocity overshoot at the source side of the channel, and the smaller high-energy tail of the distribution in the drain. This transport property creates high drain current, large transconductance, and low substrate current of the 0.1-μm n-MOSFET with asymmetric channel profile
 
Article
Novel approach for making high-performance enhancement-mode InAlAs/InGaAs HEMT's (E-HEMT's) is described for the first time. Most important issue for the fabrication of E-HEMT's is the suppression of the parasitic resistance due to side-etching around the gate periphery during gate recess etching. Two-step recessed gate technology is utilized for this purpose. The first step of the gate recess etching removes cap layers wet-chemically down to an InP recess-stopping layer and the second step removes only the recess-stopping layer by Ar plasma etching. The parasitic component for source resistance is successfully reduced to less than 0.35 Ω·mm. Etching selectivities for both steps are sufficient not to degrade uniformity of devices on the wafer. The resulting structure achieves a positive threshold voltage of 49.0 mV with high transconductance. Due to the etching selectivity, the standard deviation of the threshold voltage is as small as 13.3 mV on a 3-in wafer. A cutoff frequency of 208 GHz is obtained for the 0.1-μm gate E-HEMT's. This is therefore one of the promising devices for ultra-high-speed applications
 
Article
Sub-0.1-μm planar and gate recessed MOSFET's are investigated using both drift-diffusion and Monte Carlo simulations. In nonplanar devices, the influence of the gate corner explains that the threshold voltage roll-off can be almost suppressed. A steeper subthreshold slope (low swing) is also obtained for a channel length shorter than 50 nm when the recessed channel MOSFET is compared to its planar counterpart. The influence of the corner effect on high-current performances is also considered in relation with the electric field profile along the Si/SiO <sub>2</sub> interface
 
Article
A bandgap engineering technique is proposed for the suppression of the short-channel effect (SCE) and its effectiveness is quantitatively calculated in the case of the SiGe source/drain structure with a device simulation. The drain-induced barrier lowering (DIBL) and the charge sharing are suppressed by the presence of the valence band discontinuity between the SiGe source/drain and Si channel. In order to obtain the full advantage of this structure, it is necessary to locate the SiGe layers both at the source/drain regions and the SiSe/Si interface at the pn junction or inside the channel region. The effectiveness increases with the increase of the valence band discontinuity (Ge concentration). As a result of the suppression of the SCE and the reduction of the minimum gate length, the drain current increases, and thus high-speed operation can be realized with this technique
 
Article
This paper describes a new ultra-thin SOI-CMOS structure offering reduced parasitic diffusion-layer resistance. It addresses ways to deal with the ultra-shallow junctions required by sub-0.1 μm MOSFET's. Based on a CVD tungsten process we experimentally investigate the characteristics of selectively grown tungsten used in the source and drain region made in SOI layers of various thicknesses ranging from 10 to 100 nm. We also investigate certain CMOS device characteristics. The SOI-CMOS structure, with low parasitic diffusion-layer resistance and good contact characteristics for ultra-shallow junction devices exhibits superior device performance and high scalability
 
Article
This paper describes the high performance of T-shaped-gate CMOS devices with effective channel lengths in the sub-0.1-μm region. These devices were fabricated by using selective W growth, which allows low-resistance gates smaller than 0.1 μm to be made without requiring fine lithography alignment. We used counter-doping to scale down the threshold voltage while still maintaining acceptable short-channel effects. This approach allowed us to make ring oscillators with a gate-delay time as short as 21 ps at 2 V with a gate length of 0.15 μm. Furthermore, we experimentally show that the high circuit speed of a sub-0.1-μm gate length CMOS device is mainly due to the PMOS device performance, especially in terms of its drivability
 
Article
This paper investigates the channel design for buried p-channel MOSFETs with an effective channel length of 0.1 μm via simulations using the two-dimensional device simulator PISCES IIB. A new three-layer design is considered with the objective of obtaining low junction capacitance while maintaining high current drive and suppressing punchthrough. The channel design consists of a p-type layer under the gate oxide, an n-type anti-punchthrough layer below the p-type layer followed the substrate with a doping concentration of 1e17/cm<sup>3</sup>. By optimizing the doping structure, an attempt is made to investigate fundamental limits of the buried channel design. In concurrence with published results, it is shown that there is a maximum allowable thickness for the first layer, while the thickness of the anti-punchthrough layer has a minimum value in order to effectively suppress punchthrough. The above constraints enable devices with good subthreshold characteristics (subthreshold swing <90 mV/Dec) as well as high transconductance which is a matter of concern for ultra-thin buried layers. While simulation results show that it is possible to fabricate buried p-channel MOSFETs with n-type polysilicon gate electrodes in the 0.1 μm regime, it is also evident that advanced doping and low temperature fabrication technologies are needed that provide control over doped layers of ultra-thin dimensions
 
Influence of alloy potential in Si C on normalized transition frequency f =f of simulated MODFETs for different gate lengths (closed symbols), and on normalized drift mobility = in strained Si C (dashed line, open squares from Fig. 1). Subscript 0 refers to quantities obtained for U = 0:
Article
We study the electron transport in tensile strained Si<sub>1-y </sub>C<sub>y</sub> pseudomorphically grown on Si(100) substrate, and in n-channel short gate Si<sub>1-y</sub>C<sub>y</sub>/Si MODFETs using an ensemble Monte Carlo simulation. The alloy potential in Si<sub>1-y</sub>C<sub>y</sub> is used as a parameter, ranging from 0 to 2 eV. When the alloy scattering reduces drastically the intrinsic transport properties in Si<sub>1-y</sub>C<sub>y</sub> alloys, the nonstationary transport occurring in ultrashort gate MODFETs decreases the influence of scattering processes. The device performance can then fully benefit from the strain-induced reduction of effective mass
 
Article
We present a model for subthreshold current in deep-submicrometer pocket n-MOSFETs based on the diffusion current transport equation, the quasi-two-dimensional (2-D) Poisson equation and a doping-density-dependent mobility model, and a model for above-threshold current in deep-submicrometer pocket n-MOSFETs based on the drift-diffusion current transport equation for nonuniformly doped MOSFETs, the charge-sheet approximation, a solution of the one-dimensional (1-D) Poisson equation, a quasi-2-D model for the velocity saturation region, longitudinal- and transverse-field-dependent mobility models. The analytic models for subthreshold and above-threshold currents are used to efficiently construct viable design spaces locating well-designed 0.1-μm pocket n-MOSFETs that meet all the device design specifications of off-state (leakage) current, on-state (drive) current, and power-supply voltage. The model for subthreshold current correctly predicts an increase in off-state current in sub-100 nm pocket n-MOSFETs. The model for above-threshold current generates I<sub>D</sub>-V<sub>DS</sub> characteristics of a variety of deep-submicrometer pocket n-MOSFETs
 
Article
The effect of post-thermal annealing after indium-halo implantation on the reliability of sub-0.1-μm nMOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot carrier-induced device degradation. The best results of device performance were obtained with post-annealing treatment performed at medium temperatures (e.g., 900°C) for a longer time.
 
Article
A new 0.1-μm MOSFET structure called asymmetric halo by large-angle-tilt implant (AHLATI) is proposed for substantial reduction of short-channel and hot-carrier effects while enhancing the current driving capability. This structure differs from the conventional devices in that it has an asymmetric channel profile with a localized pileup region next to the source junction
 
Article
Simulation of a 0.1-µm MOSFET's characteristics using the Monte Carlo method is introduced in this paper. The studied device is a 0.1-µm MOSFET on an ultrathin nearly intrinsic SOI structure that is thought to be useful to suppress short-channel effects. To carry out the calculation, intravalley scattering with acoustic phonon and intervalley inelastic scattering have been taken into account in our model. Surface roughness scattering has also been considered in a particle manner using a classical model, which is a combination of both specular reflection and diffused scattering. In order to take the avalanche breakdown phenomena into account, a two-carrier many-particle Monte Carlo method has been used here. We proposed a new model for the impact ionization probability, and also for the velocity distribution of both the primary electron and the generated electron-hole pairs in this paper.
 
Article
W/TiN gate CMOS technologies with improved performance were investigated using a damascene metal gate process. 0.1-μm W/TiN stacked gate CMOS devices with high performance and good driving ability were fabricated successfully by optimizing the W/TiN stacked gate structure, improving the W/TiN gate electrode sputtering technology, and reducing W/TiN stacked gate MOSFET surface states and threshold voltages. A super steep retrograde (SSR) channel doping with heavy ion implantation, <sup>115</sup>In<sup>+</sup> for NMOS and <sup>121</sup>Sb<sup>+</sup> for PMOS, was applied here to obtain a reasonably lower threshold voltage and to suppress short-channel effects (SCEs). Non-CMP technology, used to replace CMP during the damascene metal gate process, was also explored. The propagation delay time of 57 stage W/TiN gate CMOS ring oscillators was 13 ps/stage at 3 V and 25 ps/stage at 1.5 V, respectively. Better performance would be achieved by using Co/Ti salicide source/drain (S/D) and thinner gate dielectrics.
 
Article
Hot-carrier-induced degradation of partially depleted SOI CMOSFETs was investigated with respect to body-contact (BC-SOI) and floating-body (FB-SOI) for channel lengths ranging from 0.25 down to 0.1 μm with 2 nm gate oxide. It is found that the valence-band electron tunneling is the main factor of device degradation for the SOI CMOSFET. In the FB-SOI nMOSFET, both the floating body effect (FBE) and the parasitic bipolar transistor effect (PBT) affect the hot-carrier-induced degradation of device characteristics. Without apparent FBE on pMOSFET, the worst hot-carrier stress condition of the 0.1 μm FB-SOI pMOSFET is similar to that of the 0.1 μm BC-SOI pMOSFET.
 
Article
We have experimentally studied the high-lateral-field carrier velocity near the source edge in sub-0.1 μm MOSFETs. It is demonstrated that the high-field electron velocity and hole velocity have universal low-field mobility dependence. This shows that the hole velocity is lower than the electron velocity due to the hole's lower mobility. Moreover, we have investigated the low-power CMOS operation using the velocity overshoot. It is verified that there is a most suitable supply voltage for improving the CMOS operation using velocity overshoot. The most suitable supply voltage is shown to be about 1 V. Therefore, the velocity overshoot will be very useful for low voltage CMOS operation in the future
 
Article
Al<sub>0.5</sub>In<sub>0.5</sub>As/Ga<sub>0.5</sub>In<sub>0.5 </sub>As MODFET structures have been successfully grown on lattice-mismatched GaAs substrates with a 3.8% difference of lattice constants. MODFETs fabricated with a 0.12-μm T-shaped gate demonstrate DC and microwave characteristics comparable to those of Al <sub>0.5</sub>In<sub>0.5</sub>As/Ga<sub>0.5</sub>In<sub>0.5</sub>As MODFETs on lattice-matched InP substrates. A peak extrinsic DC transconductance of 585 mS/mm and a full-channel current of 370 mA/mm are achieved at room temperature. Parasitic substrate conduction, which may be the result of the threading dislocations under the FET bonding pads and the active FET channel, affects the device performance. The MODFET shows a high current-gain cutoff frequency of 117 GHz and a maximum available gain cutoff frequency of 125 GHz. The effects of substrate conduction on microwave performance are also investigated
 
Article
This paper describes a novel double-deck-shaped (DDS) gate technology for 0.1-μm heterojunction FETs (HJFETs) which have about half the external gate fringing capacitance (C<sub>f</sub><sup>ext</sup>) of conventional T-shaped gate HJFET's. By introducing a T-shaped SiO<sub>2</sub>-opening technique based on two-step dry-etching with W-film masks, we fabricated 0.1-μm gate-openings which were suitable for reducing the C<sub>f</sub><sup>ext </sup> and filling gate-metals with voidless. The fine gate-openings are completely filled with refractory WSi/Ti/Pt/Au gate-metal by using WSi-collimated sputtering and electroless Au-plating, resulting in high performance 0.1-μm DDS gate HJFETs are fabricated. The 0.1-μm n-Al <sub>0.2</sub>Ga<sub>0.8</sub>As/i-In<sub>0.15</sub>Ga<sub>0.85</sub>As pseudomorphic DDS gate HJFETs exhibited an excellent V<sub>th</sub> standard-deviation (σV<sub>th</sub>) of 39 mV because dry-etching techniques were used in all etching-processes. Also, an HJFET covered with SiO<sub>2</sub> passivation film had very high performance with an f<sub>T</sub> of 120 GHz and an f<sub>max</sub> of 165 GHz, due to the low C<sub>f</sub><sup>ext</sup> with the DDS gate structure. In addition, a high f<sub>T</sub> of 151 GHz and an f<sub>max</sub> of 186 GHz were obtained without a SiO<sub>2</sub> passivation film. This fabrication technology shows great promise for high-speed IC applications
 
Article
Summary form only given. The LDD-type structure has begun to encounter difficulties in satisfying transistor requirements in manufacturing due to a basic conflict between the need to have a graded drain profile for hot carrier suppression and the requirements for manufacturability and performance which place emphasis on a shallow, steeply profiled drain. One approach for overcoming this conflict and limitation is a MOS transistor structure called the hot-carrier suppressed (HCS) MOSFET. In this approach, a lower doped drain region is placed behind, or above, the shallow, heavier doped drain region rather than being placed adjacent to the channel region. This structure is described in detail, and its simulated performance compared with that of the LDD and conventional MOSFET structures
 
Article
A detailed three-dimensional (3-D) statistical “atomistic” simulation study of fluctuation-resistant sub 0.1-μm MOSFET architectures with epitaxial channels and delta doping is presented. The need for enhancing the fluctuation resistance of the sub-0.1-μm generation transistors is highlighted by presenting summarized results from atomistic simulations of a wide range of conventional devices with uniformly doped channels. According to our atomistic results, the doping concentration dependence of the random dopant-induced threshold voltage fluctuations in conventional devices is stronger than the analytically predicted fourth-root dependence. As a result of this, the scaling of such devices will be restricted by the “intrinsic” random dopant-induced fluctuations earlier than anticipated. Our atomistic simulations confirm that the introduction of a thin epitaxial layer in the MOSFET's channel can efficiently suppress the random dopant-induced threshold voltage fluctuations in sub-0.1-μm devices. For the first time, we observe an “anomalous” reduction in the threshold voltage fluctuations with an increase in the doping concentration behind the epitaxial channel, which we attribute to screening effects. Also, for the first time we study the effect of a delta doping, positioned behind the epitaxial layer, on the intrinsic threshold voltage fluctuations. Above a certain thickness of epitaxial layer, we observe a pronounced anomalous decrease in the threshold voltage fluctuation with the increase of the delta doping. This phenomenon, which is also associated with screening, enhances the importance of the delta doping in the design of properly scaled fluctuation-resistant sub-0.1-μm MOSFET's
 
Article
The critical parameters important to the design of an instantly operational cathode (0.1 sec heating time) for use in power tubes are discussed. Design information showing material selection, mechanical considerations, solution to lineal expansion problems, and methods of assisted heating are covered. The treatment of the cathode heating problem is presented in semi-normalized terms to make it more adaptable to a wide variety of tube applications. The work reported in this paper resulted in the design and construction of a low inductance instantly operational cathode (0.1 sec heating time) that could be interchangeably placed in a production 250-watt UHF tetrode. This design is shown.
 
Article
Modern silicon-on-insulator (SOI) technology and 0.1-μm-channel-length complementary metal oxide silicon (CMOS) devices make it possible to fabricate high-performance RF devices by using standard Si ULSI processes. Using the buried oxide layer of an SOI wafer as an etching stopper, we were able to integrate a suspended inductor, with high-inductor resonance-frequency of 19.6 GHz, and high-performance 0.1-μm CMOS devices. Moreover, we experimentally show that this suspended CMOS has acceptable short-channel immunity. Using two-dimensional (2-D) simulation, we clarify that the gate-potential spread sufficiently suppresses the potential shifts, which results in good short-channel characteristics
 
Article
The subthreshold slope in ultra-thin-film fully depleted SOI MOSFETs is investigated for channel lengths from the long channel region down to 0.1 μm. A doping effect is found which allows improvement of the S -factor by increasing the channel doping concentration. In order to explain this phenomenon and to clarify the mechanism of S -factor degradation at short gate lengths, a two-dimensional analytical model is developed. A modified boundary condition for the two-dimensional Poisson equation is introduced to account for the nonlinear potential distribution inside the buried oxide. It is found that the S -factor short-channel degradation is governed by three mechanisms: the rise of capacitances at the channel source and drain ends due to the two-dimensional potentional distribution; the subthreshold current flow at the back channel surface; and the modulation of the effective current channel thickness during the gate voltage swing in the subthreshold region. The analytical model results are compared to those of numerical device simulation, and a good agreement is found
 
Article
A new structure is proposed for bipolar transistors - FRACS (Fully Radiative Current Path Structure). A FRACS transistor has a line emitter and a cylindrical base and collector or a point emitter and a spherical base and collector. Device parameters of the FRACS transistor is obtained by extending the conventional one-dimensional transistor model to a two- or three-dimensional model. In this structure, base transit time is reduced as the emitter size is reduced by radiative collector current flow. Using this model, a general bipolar transistor with a shallow link base is found to increase the cutoff frequency as the emitter size is reduced. The Kirk effect is suppressed in this structure because of the small collector current density at the collector-base junction. The effect was experimentally examined. A cylindrical base was fabricated by thermal diffusion of boron to achieve the FRACS transistor. Cutoff frequency was observed to increase as the emitter size was reduced. Maximum cut-off frequency of 64 GHz was achieved by this transistor with a 25-nm thick base formed by rapid vapor-phase diffusion
 
Article
Short-channel effects, substrate leakage current, and average electron velocity are investigated for 0.1-μm-gate-length GaAs MESFETs fabricated using the SAINT (self-aligned implantation for n<sup>+</sup>-layer technology) process. The threshold-voltage shift was scaled by the aspect ratio of the channel thickness to the gate length ( a / L <sub>g</sub>). The substrate leakage current in a sub-quarter-micrometer MESFET is completely suppressed by the buried p layers and shallow n<sup>+</sup>-layers. The average electron velocity for 0.1- to 0.2-μm-gate-length FETs is estimated to be 3×10<sup>6</sup> cm/s from the analysis of intrinsic FET parameters. This high value indicates electron velocity overshoot. Moreover, a very high f <sub>T</sub> of 93.1 GHz has been attained by the 0.1-μm SAINT MESFET
 
Article
Hydrogen degradation of III-V field-effect transistors (FETs) is a serious reliability concern. Previous work has shown that threshold-voltage shifts induced by H<sub>2</sub> exposure in 1-μm-channel InP high-electron mobility transitors (HEMTs) can be attributed to compressive stress in the gate due to the formation of TiH<sub>x</sub> in Ti/Pt/Au gates. The compressive stress affects the device characteristics through the piezoelectric effect. This paper examined the H<sub>2</sub> sensitivity of 0.1-μm strained-channel InP HEMTs and GaAs pseudomorphic HEMTs. After exposure to H<sub>2</sub>, the threshold voltage V<sub>T</sub> of both types of devices shifted positive. This positive shift in V<sub>T</sub> is predicted by a model for hydrogen-induced piezoelectric effect. In situ V<sub>T</sub> measurements reveal distinct time dependences of the V<sub>T</sub> shifts, which are also consistent with stress-related phenomena.
 
Article
Summary form only given. The authors report a novel metal-semiconductor-metal (MSM) Schottky photodiode using a nominally lattice-matched In/sub 0.53/(Ga/sub x/Al/sub 1-x/) /sub 0.47/As (graded)/In/sub 0.53/Ga/sub 0.47/As structure grown by molecular beam epitaxy on a semi-insulating InP substrate. The approach to barrier enhancement uses a lattice-matched compositionally graded InGaAlAs capping layer. This lattice-matched layer does not suffer from the nonradiative recombination centers which can result from strained/relaxed layers or superlattice interfaces. Abrupt band-edge discontinuities, which inhibit the collection of photogenerated carriers, are also eliminated. A detector responsivity of 0.35 A/W was measured at 1.3 mu m with a 10-V applied bias; the corresponding internal quantum efficiency is in excess of 90%. The associated dark currents are very low: 35 nA at 10 V and 500 nA at 20 V. Detector capacitance was 70 fF. Preliminary high-speed measurements with a gain-switched 1.3- mu m laser diode show an instrumentation-limited impulse response of 55 ps.< >
 
Article
A multilevel resist process has been developed that is capable of producing 0.1-μm T-cross-section gates using 50-kV electron-beam lithography. A ratio of upper to lower dimensions greater than three provides a low gate resistance of 450 Ω-mm, allowing improved microwave performance over high-resistance trapezoidal gates. Careful characterization and control of gate recessing resulted in less than 300 Å of ungated channel recess for minimal parasitic channel resistance. Several material structures were compared, varying the dopant incorporation from 80-Å spike doping to 40-Å spike doping to atomic planar doping. The growth of the spike-doped structures was optimized to provide a high n <sub>s</sub>&ges;1.2 10<sup>12 </sup> cm<sup>-2</sup>. In addition, these spike-doped structures had heavily doped caps of 100 Ω/&square; sheet resistivity to provide low parasitic source resistance. Performance was evaluated by on-wafer S -parameter measurements. The peak measured unity current gain cutoff frequency ranged from 90 to 113 GHz, depending on the material structure. This performance is attributed to careful attention to the details of gate formation, layer design, and MBE (molecular-beam epitaxial) growth
 
Article
This work is a systematic investigation of the feasibility of MOSFET's with a gate length below 0.1 μm. Limits imposed on the scalability of oxide thickness and supply voltage require a new scaling methodology which allows these parameters to be maintained constant. The feasibility of achieving sub-0.1 μm MOSFETs in this way is evaluated through simulations of the electrical characteristics of several different device structures and by addressing the most important issues related to the scaling down to ultra-short gate lengths. This study forms a valuable starting point for the understanding of technological requirements for future ULSI
 
Article
The fabrication of sub-0.1-μm CMOS devices and ring oscillator circuits has been successfully explored. The key technologies include: lateral local super-steep-retrograde (SSR) channel doping with heavy ion implantation, 40-nm ultrashallow source/drain (S/D) extension, 3-nm nitrided gate oxide, dual p<sup>+</sup>/n<sup>+</sup> poly-Si gate electrode, double sidewall scheme, e-beam lithography and RIE etching for sub-0.1-μm poly-Si gate pattern, thin and low sheet resistance SALICIDE process, etc. By these innovations in the technologies, high-performance sub-0.1-μm CMOS devices with excellent short-channel effects (SCEs) and good driving ability have been fabricated successfully; the shortest channel length is 70 nm. 57 stage unloaded 0.1-μm CMOS ring oscillator circuits exhibiting delay 23.8 ps/stage at 1.5 V, and 17.5 ps/stage and 12.5 ps/stage at 2 V and 3 V, respectively, are achieved
 
Article
Grooved-gate Si MOSFET's with tungsten gates are fabricated using conventional manufacturing technologies, and their short-channel-effect-free characteristics are verified down to a source and drain separation of around 0.1 μm. Phase shift lithography followed by a side-wall oxide film formation technique achieves a spacing of less than 0.2 μm between adjacent elevated polysilicons, subsequently resulting in a sub-0.1-μm source and drain separation in the substrate. Short-channel effects, such as threshold voltage roll-off and punchthrough, are found to be completely suppressed. From device simulations, the potential barrier formed at each grooved-gate corner is considered to be responsible for the suppression of the short-channel effects
 
TiN Φm values (PECVD and CVD ) extracted from C(V) curves; poly Si is for reference.
Article
Full chemical mechanical polishing (CMP) process integration of a W/TiN damascene metal gate has been optimized and is demonstrated to be compatible with ULSI circuit fabrication. Highly uniform and reliable electrical characteristics are achieved for widely ranged MOS pattern structures (from 0.1-μm gate transistors up to 0.6-mm<sup>2</sup> capacitors). CVD TiN film as a damascene gate electrode shows excellent properties for MOS performances and gate oxide integrity even on ultrathin gate oxide (2-nm SiO<sub>2</sub>)
 
Article
We report on 0.1-μm gate-length self-aligned Au/WSiN-gate GaAs MESFET technology. The FET we produced using this technology has a planar structure with a selective ion-implanted channel layer and self-aligned n<sup>+</sup>- layers. One of the key structural parameters affecting device performance is the offset separating the gate electrode from lightly-doped source and drain n' layers. A 0.1-μm gate length is attained by i-line photolithography using an anti-reflection top coat film and SF<sub>6</sub> gas ECR plasma etching. We demonstrate FET uniformity in a 3-in wafer and excellent high-frequency performance. The standard deviation of the threshold voltages is 0.058 V with an average of about 0 V at a gate length of 0.126 μm and the current gain cutoff frequency (f<sub>T</sub>) is 168 GHz at a gate length of 0.06 μm
 
Article
An advanced 0.1 μm CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 μm) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 μm were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 Å effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C<sub>L</sub>=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained
 
Article
A low-energy, high-dosage boron ion implantation technology using a decaborane (B<sub>10</sub>H<sub>14</sub>) molecule is developed. Since B<sub>10</sub>N<sub>14</sub> consists of ten boron atoms, they are implanted with about a one-tenth lower effective acceleration energy and ten times higher effective beam current compared with those of boron. We demonstrated an ultrashallow boron profile with 0.5 keV effective acceleration energy, which does not cause transient enhanced diffusion (TED) after rapid thermal annealing (RTA). Using this technology, we succeeded in fabricating 0.1-μm PMOSFET's with good device performances and excellent suppression of short-channel effects
 
Article
A comprehensive Monte Carlo simulator is employed to investigate nonlocal carrier transport in 0.1 μm n-MOSFET's under low-voltage stress. Specifically, the role of electron-electron (e-e) interactions on hot electron injection is explored for two emerging device designs biased at a drain voltage V<sub>d</sub> considerably less than the Si/SiO<sub>2</sub> injection barrier height φ<sub>b</sub>. Simulation of both devices reveal that 1) although qV<sub>d</sub><φ<sub>b</sub>, carriers can obtain energies greater than φ<sub>b</sub>, and 2) the peak for electron injection is displaced approximately 20 nm beyond the peak in the parallel channel electric field. These phenomena constitute a spatial retardation of carrier heating that is strongly influenced by e-e interactions near the drain edge. (Virtually no injection is observed in our simulations when e-e scattering is not considered.) Simulations also show that an aggressive design based on larger dopant atoms, steeper doping gradients, and a self-aligned junction counter-doping process produces a higher peak in the channel electric field, a hotter carrier energy distribution, and a greater total electron injection rate into the oxide when compared to a more conventionally-doped design. The impact of spatially retarded carrier heating on hot-electron-induced device degradation is further examined by coupling an interface state distribution obtained from Monte Carlo simulations with a drift-diffusion simulator. Because of retarded carrier heating, the interface states are mainly generated further over the drain region where interface charge produces minimal degradation. Thus, surprisingly, both 0.1 μm n-MOSFET designs exhibit comparable drain current degradation rates
 
Article
We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-μm SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (10<sup>16</sup> cm<sup>-3</sup>) channel and 2) a heavily-doped (10<sup>18</sup> cm<sup>-3</sup>) channel. For each design, the silicon layer thicknesses (T<sub>Si</sub>) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO<sub>2</sub> barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in T<sub>Si</sub> results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead
 
Article
Analytical modeling of these very-short-channel HEMTs (high-electron-mobility transistors) using the charge-control model is given. The calculations performed using this model indicate a very high electron velocity in the device channel (3.2±0.2×10<sup>7 </sup> cm/s) and clearly demonstrate the advantages of the planar-doped devices as compared to the conventional uniformly doped HEMTs. Devices with different air-bridged geometries have been fabricated to study the effect of the gate resistance on the sub-0.1-μm HEMT performance. With reduced gate resistance in the air-bridge-drain device, noise figures as low as 0.7 and 1.9 dB were measured at 18 and 60 GHz, respectively. Maximum available gains as high as 13.0 dB at 60 GHz and 9.2 dB at 92 GHz, corresponding to an f <sub>max</sub> of 270 GHz, have also been measured in the device. Using the planar-doped pseudomorphic structure with a high gate aspect-ratio design, a noise figure of less than 2.0 dB at 94 GHz is projected based on expected further reduction in the parasitic gate and source resistances
 
Article
A three-dimensional (3-D) “atomistic” simulation study of random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFETs is presented. For the first time a systematic analysis of random dopant effects down to an individual dopant level was carried out in 3-D on a scale sufficient to provide quantitative statistical predictions. Efficient algorithms based on a single multigrid solution of the Poisson equation followed by the solution of a simplified current continuity equation are used in the simulations. The effects of various MOSFET design parameters, including the channel length and width, oxide thickness and channel doping, on the threshold voltage lowering and fluctuations are studied using typical samples of 200 atomistically different MOSFETs. The atomistic results for the threshold voltage fluctuations were compared with two analytical models based on dopant number fluctuations. Although the analytical models predict the general trends in the threshold voltage fluctuations, they fail to describe quantitatively the magnitude of the fluctuations. The distribution of the atomistically calculated threshold voltage and its correlation with the number of dopants in the channel of the MOSFETs was analyzed based on a sample of 2500 microscopically different devices. The detailed analysis shows that the threshold voltage fluctuations are determined not only by the fluctuation in the dopant number, but also in the dopant position
 
Article
A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (~1000°C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450°C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO<sub>2</sub> or Ta<sub>2</sub>O<sub>5</sub> as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance
 
Article
Optimized halo structures for sub-0.1 μm CMOSFETs are evaluated. Halo profiling using indium implantation for nMOSFETs is investigated over a wide range of implantation dosages and energies. Performance degradation due to interstitial Si resulting from In-halo implantation can be reduced using thermal annealing at medium temperatures for longer periods of time. Lower-temperature composite liner-oxide/SiN-spacer technology is proposed for pMOSFETs to suppress device performance degradation. Optimized halo structures using indium for nMOSFETs and arsenic for pMOSFETs to obtain high-performance sub-0.1 μm CMOSFETs are proposed
 
Article
We found threshold voltage sensitivity to silicon thickness variation in 0.1 μm channel length fully-depleted SOI NMOSFET's can be reduced with lightly-doped channel and back-gate bias. However, after the back-interface is accumulated, the reduction is small and threshold voltage roll-off due to high drain bias increases
 
Article
A simple fabrication technology for delta-doped MOSFETs, named post-low-energy implanting selective epitaxy (PLISE) is presented. The PLISE technology needs no additional photo-lithography mask, deposition step or etching step even for CMOS devices. The only additional step is growing undoped epitaxial channel layers by UHV-CVD after the channel implantation. With this technology, delta-doped NMOSFETs with 0.1-μm gate length were successfully fabricated. By optimizing the epi-layer thickness and the channel doping level, short-channel effects are suppressed enough to achieve 0.1-μm gate length. Moreover, the junction capacitance at zero bias is reduced by 50%
 
Article
Accurate external resistance extraction for shallow source/drain extension (SDE) MOSFET's is demonstrated using a unified mobility model for inversion and accumulation layers. The parasitic resistance in the accumulation layer (R<sub>acc</sub>) is highly dependent both on the SDE junction depth (X<sub>j</sub>) and the gate overlap length (L<sub>ou </sub>). Due to the laterally finite doping gradient, R<sub>acc</sub> becomes dominant among other external resistance components in sub-0.1 μm MOSFETs. Hence, device optimization to minimize R<sub>acc</sub> is necessary in order to improve on-current and SDE to the gate coupling. A NMOS transistor with L<sub>eff</sub> of 0.08 μm shows a maximum on-current while maintaining a lower off-leakage current for a L<sub>ou </sub> of 20 nm and X<sub>j</sub> of 40 nm
 
Top-cited authors
Chenming hu
  • University of California, Berkeley
Guido Groeseneken
Michael S. Shur
  • Rensselaer Polytechnic Institute
H.-S. Philip Wong
  • Stanford University
D. Ielmini
  • Politecnico di Milano