IEEE Transactions on Consumer Electronics

Published by Institute of Electrical and Electronics Engineers
Online ISSN: 0098-3063
Publications
Article
A phase-locked loop (PLL) large-scale integration (LSI) chip operating in the broadcast frequency band from MF to UHF has been developed using an N-channel enhanced double diffusion (ED) MOS process technology with 0.8- mu m effective channel length. The operation of the PLL has been verified for frequencies from 0.2 MHz to 1200 MHz for a power-supply voltage of 5 V and an input signal amplitude of 100 mV RMS. The authors describe the N-channel ED MOS process technology that enables direct division of high-frequency signals up to the UHF band, and the high-speed circuit technology, functions, and special features of the circuit.
 
Article
A 10-bit D/A converter with differential current outputs is presented. Special care was taken to minimize the output glitch energy and the linearity errors, considering the 1.5 V output range under a 3.3 V voltage supply. A current cell with biased switches, thermometer decoding and a shuffle in the physical layout of the cells enabled to achieve the following performances. The integral and differential linearity errors INL and DNL are within +/-1.5 LSB and +/-0.5 LSB respectively. The maximal glitch energy is 60 pV.S. The device dissipates 46 mW at 70 MHz clock rate and full-scale output swing. The D/A converter has been developed in a CMOS 0.5 μm technology. The active chip area is 0.4 mm<sup>2</sup>
 
Article
The discrete cosine transform (DCT) has been commonly adopted in many transformation applications such as image, video, and facsimile. A VLSI architecture and implementation of a high speed 2-dimensional DCT core processor with 0.8 μ technology is presented. This architecture applies a fast DCT algorithm and multiplier-accumulator based on the distributed algorithm, which has contributed to reduce the hardware requirement and to achieve high speed operation. The transpose memory inserted between each dimension of DCT is partitioned in order to reduce further hardware overhead. Furthermore, this 2-dimensional DCT scheme satisfies the accuracy specification of CCITT recommendation MPEG
 
Article
A CMOS analog front-end processor for a 4× speed CD-ROM is designed and fabricated in a 0.8-μm process. The IC consists of RF amplifiers, pulse reshaping circuits, an automatic power control circuit for laser diode, and a servo control signal generator which includes track and focus error detecting circuits. Experimental result shows that its RF performance is enough for 8× speed CD-ROM. The circuit enables to design a true one chip 4× speed and 8× speed CD-ROM or DVD player in digital CMOS process technology
 
Article
CMOS technologies are widely exploited now in the area of a few-GHz-range radio frequency (RF) circuits as well as in the area of baseband circuits. Accordingly, the CMOS low-noise amplifier (LNA) is gaining its popularity, tailored to the applications such as GSM, PCS, IMT-2000, and wireless LAN. In this paper, compact and comprehensive design strategies for CMOS LNA are presented. Basic topologies are compared and analyzed using key equations newly derived. Using these strategies, an LNA based upon LC resonance using on-chip spiral inductors is designed and investigated. This LNA, targeted for 1.8 GHz PCS, exhibits power gain of about 18 dB and noise figure (NF) of about 2.1 dB by both theory and post-layout simulation under a 0.8-μm CMOS process and 3-V supply
 
Article
A 1 GHz image-rejection down-converter implemented in a 0.8 /spl mu/m CMOS process is presented. The down-converter consists of a quadrature generator and mixers. The proposed architecture has an image-rejection characteristic that are insensitive to the phase error of the higher frequency first local oscillator (LO). The down-converter has an image-rejection characteristic of 29.3 dB under 2/spl deg/ phase error of the lower frequency second LO. The down-converter dissipates 108 mW at a 3.3 V supply.
 
Article
Using a conventional 0.8 μm CMOS process a voltage controlled oscillator (VCO) is developed which operates properly from 500 MHz up to over 2 GHz at 3 V supply voltage. Circuit optimization for higher oscillation frequency and a biasing scheme suitable for the optimized circuit enable the high frequency operation
 
Article
The ISO/MPEG phases 1 and 2 audio compression are receiving a wide range of applications. In the MPEG encoding process, the psychoacoustic model exploits the audio irrelevancy which has the key role in achieving a high compression ratio without losing the audio quality. However, the Fourier transform (FT) which has been used by the two psychoacoustic models suggested in the draft standard requires a high computational complexity, and hence leads to high hardware and software cost for real-time applications. This paper presents a new design named the hybrid filter bank to replace the FT. The hybrid filter bank can be integrated with the psychoacoustic models and provides a much lower complexity than the FT. Also, this paper shows that the hybrid filter is more suitable for stereo coding and hence can provide a better quality for the intensity stereo coding, which is the key technology for the MPEG 1 to achieve a near transparent quality lower than 96×2 kbits for two stereo channels
 
Conference Paper
In this paper, a 1.0 Gb/s multi-channel optical interface transmitter (Tx) and receiver (Rx) chip set is presented. For a high resolution liquid crystal display (LCD) operating up to SXGA (1280×1024) pixels) grade, we present a high speed serial digital video I/O scheme with low EMI, skew-tolerant and long transmission distance. The interface chip set has a data recovery system with ±1 bit skew compensation and a 8B9B encoding/9B8B decoding for dc balancing. The analog front ends of the optical interface such as laser driver in Tx and PD current detector in Rx are fully integrated in the chip set. The Tx consists of an encoder, a pipelined high speed serializer, and a vertical cavity surface emitting laser (VCSEL) driver. The Rx consists of a transimpedance amplifier for PD input, a deserializer, and a decoder for each channel. Fully integrated low jitter PLLs are implemented for clocking in the chip set. With a single 2.5 V supply operating at 1.0 Gb/s, the power consumption of the Tx is 150 mW and that of the Rx is 230 mW. They were implemented in a 0.5 um, 3-metal BiCMOS process and occupy an active area of 3,170*3,440 mm<sup>2 </sup> each
 
Article
A 1.0 Gb/s multi-channel optical interface transmitter (Tx) and receiver (Rx) chip set is presented. We propose a new high speed serial digital video I/O scheme for high resolution liquid crystal displays (LCD) operating up to the SXGA(1280*1024 pixels) grade. By using an optical fiber as a channel, it is possible to implement the optical interface with a low EMI, high skew-tolerance, and long transmission distance. All the analog front ends such as a laser driver in the Tx and a PD current detector in the Rx are fully integrated in the chip set. The interface chip set has a data recovery system with ±1 bit skew compensation and an encoder/decoder for DC balancing. With a single 2.5 V supply operating at 1.0 Gb/s, the power consumption of the Tx is 150 mW and that of the Rx is 230 mW, respectively. They were implemented in a 0.5 μm, 3-metal BiCMOS process and occupy an active area of 3170*3440 mm<sup>2</sup>, each
 
Article
A front-end IC for a 1.1-V, VHF paging receiver has been developed. Using a novel low-noise, low-distortion amplifier, it achieves a high sensitivity of -130 dBm and a low intermodulation sensitivity of -20 dBm while consuming only 1.98 mW. A 2.93-dB noise figure and a +5.0-dBm third-order intercept point are achieved under 50-Ω matching
 
Article
The UPnP™ 1.0 peer-2-peer home networking architecture is an important step towards interoperability of networked consumer devices, realizing the connected home experience. This paper describes how the UPnP 1.1 device architecture improves the UPnP 1.0 device architecture in a backwards-compatible way, improving discovery and compatibility with referenced standard.
 
Article
A single chip driver system for a passive matrix organic electroluminescent display (PMOELD) with resolution of 128×80 plus 20 icons, has been developed for low cost and small size mobile phone applications. The developed OELD driving single chip comprises a novel current programmable data driver circuit with high voltage current mirror, a scan driver circuit with level shifted high voltage outputs, embedded RAMs, a DC-DC converter that generates a maximum 16 V from a single battery, whose voltage is typically 3.3 V, and digital control circuits that are used for handling display data from an external MCU and control signals. The chip has been fabricated using 0.6 μm CMOS technology with 20 V high voltage devices and it has been attached to the PMOELD panel in a commercial mobile phone by COF (chip on film) technology. The measured minimum power conversion efficiency of the integrated DC-DC converter is 82% and the measured maximum channel-to-channel current variation of the data driver circuit is 5% for a full green image under various luminance conditions. The measured peak luminance of the OELD is 500 cd/m<sup>2</sup> at the panel power consumption of 0.53 W and the full green image pattern with over 100:1 contrast ratio
 
Article
This paper describes the implementation and potential applications of a sigma-delta A/D-converter. A second-order low-pass approach with a single-bit quantization is used. Test ICs using a 20 GHz f<sub>T</sub> Si bipolar technology were fabricated and proven functional
 
Article
Two newly developed digital ICs have been able to enhance remarkably the operability and reliability of the HDTV camera. Many kinds of fine adjustments, such as the color fidelity, color saturation, and the image quality, are possible by the attachment of a remote control unit. A prototype HDTV camera with a 2/3" image format and a 1.3 M pixel FIT-CCD image sensor, has been made using these ICs
 
Article
A single chip PLL IC for digital tuning application up to 1.3 GHz is described. It is part of a new family of analog and digital TV-ICs, which are functionally controlled via a common 2-wire bi-directional I2C Bus (Inter-Integrated Circuit Bus) by a single chip microcomputer.
 
Article
A 1-in. format 1.5-million pixel IT (interline transfer) CCD (charge coupled device) image sensor has been developed for an HDTV (high-definition television) camera system. To achieve a low smear ratio while maintaining a high level of sensitivity, the authors have developed a new impurity profile of a buried P <sup>+</sup>-layer and an on chip microlens array whose material is a deep-UV resist. Using this sensor, a high-fidelity picture with a horizontal resolution of 820 TV lines has been obtained. The IT-CCD sensor has achieved a smear ratio of less than -90 dB, a sensitivity level of 80 nA/Lx, and a maximum charge handling capacity of 1.2×10<sup>5</sup> electrons
 
Article
In recent years, digital speech processing techniques have made revolutionary advances. One of the techniques that has lead to the improvement of voice-controlled toys, multimedia sound effects, and mobile, including satellite, phones is low-bit-rate speech coding. We present an ASIC architecture for speech synthesis at 1.6 kbps. The processing algorithm is formulated from the hardware-oriented viewpoint. Based on the proposed speech synthesizer, the developed architecture consumes fewer hardware resources but still attains satisfactory quality. It is therefore suitable for hardware implementation.
 
Article
This paper presents an all digital 1.62 Mb/s quadrature phase-shift keying (QPSK) burst-mode transceiver for fiber-to-the-curb/very-high-rate digital subscriber line (FTTC/VDSL) application. In a point-to-multipoint FTTC/VDSL network architecture, a time division multiple access (TDMA) scheme is used to connect multiple user devices to the network device. We discuss the design and implementation of an all-digital burst-mode QPSK system for transmission of 1.62 Mb/s upstream data over FTTC/VDSL channel environment. All operations of the QPSK system, including power detection, demodulation, box-car filtering, fast/slow-mode carrier and timing recovery, have been realized digitally without multiplication. It is shown by theoretical and computer simulation results that the proposed QPSK transceiver operates on up to 2.5 kft (about 762 m) of 26 gauge cable with a comfortable noise margin
 
Article
A clock and data recovery (CDR) for the physical layer of DisplayPort at sink side is described. A 1/5-rate linear phase detector (PD) compares the phase of the incoming data with that of sampling clock to recover a clean clock and data. A pattern based frequency detector (PBFD) reduces frequency error to be in the pullin-range of the 1/5-rate linear PD. The PBFD reduces the frequency error down to 3.2% before the linear PD starts its operation. The CDR implemented in a 0.13 m CMOS process shows 29-ps rms and 154-ps peak-to-peak jitter in the recovered clock and 10<sup>-7</sup> bit error rate (BER) for 2<sup>31</sup>-1 pseudorandom binary-sequence (PRBS) input while consuming 87mW from a 1.2-V supply.
 
Article
A 3.3-inch 1.9 M-pixel poly-Si TFT-LCD for high-definition and computer-data projectors has been developed. This LCD is able to display both full-band HD signals and computer data. This unique applicability is realized by adapting novel CMOS decoder circuits integrated on the substrate. By arranging these decoder circuits on both sides of the panel, effective redundancy is also realized. An oxidation thinning process and a low-resistance tungsten-polycide gate electrode are used in fabricating the poly-Si TFTs, and n-channel MOS-TFT mobility of 160 cm<sup>2</sup>/Vs was realized. A horizontal resolution of 1000 TV lines mid a contrast ratio of 200:1 is achieved
 
Article
Harmonic content of the line current of mains-connected equipment destined for use in Europe is regulated by IEC 1000-3-2. This standard defines four different classes for electronic equipment (class A, B, C, D). These classes establish different current harmonic limits depending on the use of the electronic equipment. Class A and class D are applied to equipment classified in the field of consumer electronics such as television receivers, personal computers, home electrical appliance, audio equipment, etc. This paper presents the analysis and design procedure of the input section of electronic equipment classified as class A. This novel analysis describes how to select the values for the filter in order to improve the margin of compliance.
 
Article
To realize a single display system for all types of TV image information with different scanning-lines and indicating-channels, a new single-scanning technology with a scan conversion method has been studied by response analysis and by experimental evaluation of the picture quality. This study confirmed that a minimum deterioration of a vertical response and no degradation of the motion of an image can be obtained and that the aliasing and flickering effects caused by the use of a conventional interlaced scanning can be eliminated. These advantages are due to a newly developed scan conversion method which employs a double field-rate and wobbling interlaced scanning within four fields. New multimedia such as the ATV, HDTV, digital TV, and 3D-TV can be displayed in the single display system. Furthermore, in the new platform using this technology, it is easy to interface with the HD and 3D package media and image-sensing media
 
Article
This paper presents a newly developed concept of digital clock generation and corresponding data processing suitable for highly integrated video upconversion systems. To increase flexibility and reliability, a single master clock source is used to derive all clocks both of locked and unlocked types. Critical analog PLLs are obsolete. Now the first IC of the next generation of low cost, high performance single-chip upconversion ICs for flicker-free TV has been designed in a 0.18 μm copper eDRAM technology. All processing stages between tuner output (CVBS) and RGB processor input are integrated, requiring only a few external components
 
Article
The 1024-QAM demodulator we developed for cable television networks uses a modified symbol-decision region to reduce the effects of phase noise due to set-top-box tuners. The symbol-decision region is optimized by analysis of phase noise distribution. Simulation results show that good demodulation characteristics of a 1024-QAM signal are achieved under typical phase-noise conditions. The results are verified in a field trial with a prototype demodulator and an off-the-shelf tuner.
 
Article
In an MPEG (Motion Pictures Experts Group) video coding system, a color component downsampling from 1050 2:1 60 Hz to 525 1:1 30 Hz line scan formats must be carried out on the U and V color component source signals. One scheme presently used to accomplish the required U and V downsampling, called frame-based color subsampling, is thoroughly analyzed. In addition, field-based color downsampling is analyzed and compared with the frame-based color downsampling. The maximum vertical and temporal resolution of the original U, V signals is 1050 tvl and 30 Hz. An analysis in the vertical-temporal Fourier-transform domain shows that the best possible vertical and temporal resolution of the frame-based approach is 525 tvl and 15 Hz. For the field-based approach the maximum possible vertical and temporal resolution is 265.5 tvl and 30 Hz. The fact that the temporal resolution is reduced by one half in the frame-based approach leads to blurring of horizontal edges on moving objects, although in quasi-stationary picture sequences this approach performs well in the sense that vertical aliasing artifacts can be reduced by the use of a proper vertical filter
 
Article
Existing in-home telephone wire can be used to create a 10Base-T (10 Mbps Ethernet) customer premises network (CPN) that may be used to connect consumer electronic devices to a hub or to a residential gateway (RG). This paper presents measurements of attenuation and crosstalk performance at 10Base-T frequencies made on four different types of in-home telephone cables, including quad and twisted-pair. Computer simulations use the measured response of the cables to determine the performance of 10Base-T transmitted over them. Simulations are verified by experimental transmission tests using a LAN analyzer. It is found that some of the in-home telephone cables have good performance, which actually exceeds that of the Category 3 wiring specified for 10Base-T use. Some of the cables are not so good and do not even come close to meeting Category 3 specifications. Even so, 10Base-T was able to transmit error-free over 100 meters (328 ft) of the worst cable tested here with no bridged taps. Tree-and-branch wiring has unterminated branches connected to the cable between the transmitter and receiver. These branches are called bridged taps. It was found that 10 Base-T can function with bridged taps shorter than about 8 ft, but bridged taps longer than about 12 ft generally cause 10 Base-T to fail
 
Article
There is continued and growing interest in using low voltage power networks to realize "the last mile". It is necessary and important for any communication system to study the noise characteristics of the communication channel. This paper presents noise measurements on three typical low voltage networks in the frequency range of (500 k∼10 M) Hz. The noise measurements include: power-line background noise, appliance noise and noise sampled over a 24-hour period The conclusion that has been reached is that the noise level in the (500 k∼10 M) Hz is much lower than that in the (10 k-450 k) Hz ranges. Finally the paper gives a rough estimate of the channel capacity.
 
Article
In this paper, we propose a wide range PLL (phase locked loop) for 64X speed CD-ROMs and 10X speed DVD-ROMs. In order to develop a PLL with a wide locking range we designed a dual loop scheme which consists of a frequency detection loop and phase detection loop. The PLL has a locking range of 75 MHz-370 MHz A new V-I converter and a differential delay cell are used in a 3-stage ring VCO to reduce jitters. In addition, we propose a new charge pump which has perfect current matching characteristics for sourcing/sinking currents. This new charge pump improves the phase offset that reduces the locking range of the PLL. Implemented in a 0.25 μm, 1-poly 5-metal CMOS process. It occupies an active area of 1.8 mm*1.1 mm
 
Article
In this paper digital videophone experiments via the Orbital Test Satellite (OTS) in the 14/11 GHz band are described.
 
Article
30AX is a new in-line color TV display system with 110 deflection angle and interchangeable tubes and yokes. It is based on the production experience gained with the 20AX system introduced in 19741,2,3) and the results of further investigation in the field of tube technology and deflection yoke design. For the tube, this meant a new reference system, an internal magnetic correction ring and an improved gun design. For the yoke, the most important elements are a new "flangeless" winding technology, a change in the shape of the windings at the screen side of the line deflection coil and the use of field shapers embedded in the deflection coil.
 
Article
Social demand for energy and material saving has been increasing since the oil crisis of 1973. This is not an exception even in the color TV receiver industry.
 
Conference Paper
Six advanced television (ATV) transmission systems are being tested. These systems provide video signal inputs in the form of red (R), green (G), and blue (B) in analog form. One system requires 1125-line, 60-field/s interlaced video, two require 1050-line, 59.94-field/s interlaced video, two require 787.5-line 59.94-field/s noninterlaced video, and one requires 525-line, 59.94-field/s noninterlaced video. Digital video tape recording of RGB video in all proposed ARV formats has been implemented on the digital video tape recorder (DVTR), which was designed for the SMPTE-240-M video format. This required the development of a format converter, which is described
 
Article
A sigma-delta (ΣΔ) audio digital-to-analog converter (DAC) for CD and digital versatile disk (DVD) application is presented. The converter uses a 6-bit modulator and a segmented noise-shaped scrambling technique to achieve a 113 dB dynamic-range over a 20 kHz bandwidth. A continuous-time output stage is used to achieve a high signal-to-noise (SNR) in a small die area. This output stage employs a dual return-to-zero scheme to eliminate errors caused by inter-symbol interference (ISI). The converter is fabricated in a 0.6 μm double-poly double-metal CMOS process. The chip occupies 3.1×3.2 squared mm and operates from a single 5 V supply
 
Article
In the past single chip frequency synthesizer tuning systems have been developed which are suitable for simple radio sets, but bring problems if designed into more sophisticated radios. Separation of the control and display functions from the tuning function allow the PLL circuit to be situated near the tuners and the control and display function near the front of the receiver. This minimises internal radiation as well as the number and length of internal interconnections.
 
Article
The popularity of personal computers have created a greater need for more efficient and inexpensive communication methods between computers. The existence of different protocols made the problem more complex. This paper recommends a solution by using an IC modem device that supports the three major 1200 bps protocols. This paper also discusses the design flexibility achieved by using such a modem device.
 
Article
Electrophotographic printing is one of the most attractive non-impact printing methods because it can be fast, compact, and of high quality. All electrophotographic technics need a light source of some kind, for instance a laser source or an LED array. The loser illuminates one point at a time and, therefore, requires a scanner to print a line serially. In contrast a linear LED array prints a whole line at a time. Due to the combination of active emission and parallel printing capability an LED-bosed printing unit can be made very compact and power efficient.
 
Article
A recently : developed two integrated circuit speech synthesis system represents a significant advance in large scale integration in both random logic and data storage functions.
 
Article
Digital video coding for extended-quality television (EQTV) distribution over a broadband integrated services digital network (B-ISDN) at a payload rate of approximately 135 Mb/s is considered. The contribution signal will be either the CCIR Recommendation 601 signal or a minor modification of it to maximize horizontal resolution, and the scanning parameters will be the same as NTSC so that the same monitor can be used to display either EQTV or NTSC TV. A compatible vertical improvement can be added initially, or in the future, that will provide additional vertical resolution beyond the capability of the present NTSC TV or Recommendation 601. Several coding techniques for video distribution are presented to maximize horizontal resolution, given the above constraints. Two of these video coding techniques allow extra bandwidth by using sub-Nyquist sampling techniques together with comb filtering
 
Article
This paper proposes a new histogram equalization method, called RSWHE (recursively separated and weighted histogram equalization), for brightness preservation and image contrast enhancement. The essential idea of RSWHE is to segment an input histogram into two or more sub-histograms recursively, to modify the sub-histograms by means of a weighting process based on a normalized power law function, and to perform histogram equalization on the weighted sub-histograms independently. RSIHE (recursive sub-image histogram equalization) and RMSHE (recursive mean separate histogram equalization) are some methods similar to RSWHE, but they do not carry out the above weighting process. We show that compared to other existent methods, RSWHE preserves the image brightness more accurately and produces images with better contrast enhancement.
 
Article
This paper presents the IEEE 1394/UPnP software bridge for representing legacy IEEE 1394 devices to UPnP devices. UPnP devices must provide SSDP discovery, SOAP control, and GENA event processes. To represent the legacy IEEE1394 devices to UPnP devices, there have to be the IEEE 1394/UPnP software bridge to provide those functionalities on behalf of IEEE 1394 devices. The bridge can provide additional functions such as A/V data transferring with format converting between IEEE 1394 and UPnP devices. With those functionalities, the bridge makes UPnP control points recognize IEEE 1394 devices as UPnP devices, and makes possible exchange the A/V data between IEEE 1394 legacy devices and normal UPnP devices. Based on the general structure of the bridge, it can be easily extended to support a new IEEE 1394 device type.
 
Article
The goal of the cycle time synchronization and its specific implementation described in this article is to ensure a sufficient accuracy and fidelity of the streamed multimedia contents transmitted between networked IEEE 1394 clusters via UWB (ultra wide band) over coaxial cable in HANA (HIGh definition audio video network alliance) and AV/C (IEEE 1394 audio/video control protocol) consumer's home digital multimedia networks. The implementation of this synchronization mechanism, based on the standard "Networking IEEE 1394 Clusters via UWB over coaxial cable", solves two specific potential problems, which would arise without a proper synchronization method and which otherwise would damage the quality of streamed content enough to avoid the success of the HANA networks in its just and only target, the consumer electronics market. This mechanism avoids buffer under- and overruns in sink's clusters as well as prevents phase difference artifacts when transmitting streaming data through the consumer's home network.
 
Article
The 1394-to-coax bridge described here has been developed to enable digital multimedia home networks using the existing coax infrastructures as backbone for networking HANA (high-definition audio-video network alliance) devices as well as legacy IEEE 1394 AV/C digital multimedia devices which are connected to different 1394 clusters widespread over the consumer's home. The implementation is based in the future standard "networking IEEE 1394 clusters via UWB over coaxial cable", currently in development by the 1394 Trade Association (1394TA). One of our main goals was to provide a platform which verifies this standard.
 
Article
We propose a residential HDTV distribution system that is composed of UWB and IEEE 1394. This system converts multi-channel MPEG TS broadcasting data into IEEE 1394 packets or UWB packets based on IEEE802.15.3 WPAN. Any distributed UWB packets are again converted into MPEG TS data through a UWB-to-IEEE1394 bridge. Moreover, this system can also transmit IPTV packets encapsulated with IEEE 1394 packets from a home gateway or home server to a home UWB network. We implement UWB MAC and physical layer chips using CMOSASICs.
 
Top-cited authors
Sung-Jea Ko
  • Korea University
Joonki Paik
  • Chung-Ang University
Soong Der Chen
  • Universiti Tenaga Nasional (UNITEN)
Haidi Ibrahim
  • Universiti Sains Malaysia
Athanassios Skodras
  • University of Patras