IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications

Published by Institute of Electrical and Electronics Engineers
Online ISSN: 1057-7122
Publications
Article
Construction of all rational positive real functions with a given denominator is described. Examples showing how to respect various requirements on the degrees of the resulting polynomials are given
 
Article
The objective of this work is to develop a general method for the synthesis of a solution to the problem of designing positive real functions of a prefixed Hurwitz denominator polynomial. Such a synthesis problem is reduced to the calculation of the solution of an equivalent algebraic system of linear equations. The dual problem of designing the denominator polynomial for a prefixed given numerator polynomial is also focused on. The problem is first solved for rational realizable functions and extended in a natural way to nonrational ones by simply addition of single derivative blocks of positive gain. The possibility that common factors can appear “a prior” in the decomposition of the numerator polynomial in its real and imaginary parts is considered in the given synthesis procedure and it is then theoretically solved
 
Article
This paper presents a 1.5 V BiCMOS dynamic logic circuit using a “BiPMOS pull-down” structure, which is free from race problems, for VLSI implementation of full adders. Using the 1.5 V BiCMOS dynamic logic circuit, a 16-bit full adder circuit, which is composed of half adders and a carry look-ahead circuit, shows a 1.7 times improvement in speed as compared to the CMOS static one
 
Article
This brief reports comparison of the charge sharing problems between BiCMOS and the CMOS dynamic logic circuits for both 5 V and 1.5 V operations. In addition, a 1.5 V BiCMOS dynamic logic circuit free from charge sharing problems is reported. Based on the analysis, the 1.5 V full-swing BiCMOS dynamic logic gate circuit without charge sharing problems shows a more than 1.5 times improvement in speed as compared to the CMOS one
 
Article
This paper presents the design of BiCMOS dynamic logic circuits that are capable of full-swing operation from low supply voltages down to 1.5 V. Basic full-swing low-voltage BiCMOS cells are introduced. These include emitter-follower complementary n-type cell, quasi-complementary n-type cell and a p-type cell based on the transiently saturated full-swing technique. The propagation delay, power consumption and the full-swing capability of such cells have been studied both at the cell level and in a 4 b CLA design. The results clearly show the validity of the proposed circuits for high-speed low-voltage operation
 
Article
This paper reports a 1.5-V bootstrapped pass-transistor-based Manchester carry chain circuit suitable for implementing low-voltage carry look-ahead adders. As verified by the experimentally measured data from a test chip fabricated using a 0.8-μm single-poly double-metal CMOS technology, with the bootstrapped pass-transistor-based Manchester carry chain circuit technique, the speed performance of a 16-bit carry look-ahead adder circuit is enhanced by 56% at a supply voltage of 1.5 V as compared to the adder using the conventional Manchester carry chain circuit
 
Article
Pass transistor logic (PTL) has advantages over standard CMOS designs in terms of layout density, circuit delay, and power consumption and is well suited for pipelined circuits. In this paper we develop a decision-diagram-based model, the 123-decision diagram, which can he used to efficiently synthesize PTL circuits, and we investigate multilevel logic synthesis techniques for complex, pipelined PTL networks using this model. Experiments on a large number of benchmark circuits show that PTL networks synthesized using our techniques are significantly more economic in terms of silicon area compared to those using existing techniques
 
Article
In this work, the effect of sampling clock jitter on the SNR of an analog-to-digital (AD) conversion is investigated from a practical perspective. Aperture jitter analyses have been dealing up to now with white spectrum jitter. This assumption does not hold for the output of phase-locked loops (PLL)-like frequency synthesizers, where the spectrum is shaped by the loop transfer function. Based on a linear approximation, a powerful expression for the SNR is derived, applicable to a jitter process with a generic autocorrelation function and generic input signal. A lot of different definitions of jitter are available in the literature; this work addresses also the problem of identifying correctly among them the "effective" jitter for a given SNR. This can be profitably used in the specification as well as verification of the jitter requirements of a frequency synthesizer used as sampling clock generator in the AD converter systems. The results have been checked through numerical simulation.
 
Article
This paper is devoted to the analysis of the impact of chaos-based techniques on block encryption ciphers. We present several chaos based ciphers. Using the well-known principles in the cryptanalysis we show that these ciphers do not behave worse than the standard ones, opening in this way a novel approach to the design of block encryption ciphers
 
Article
In this work, dynamic multilayer neural networks are used for nonlinear system online identification. The passivity approach is applied to access several stability properties of the neuro identifier. The conditions for passivity, stability, asymptotic stability, and input-to-state stability are established. We conclude that the commonly-used backpropagation algorithm with a modification term which is determined by offline learning may make the neuro identification algorithm robustly stable with respect to any bounded uncertainty.
 
Article
The L(2,1)-labeling of a graph is an abstraction of the problem of assigning (integer) frequencies to radio transmitters, such that transmitters that are "close", receive different frequencies, and those that are "very close" receive frequencies that are further apart. The least span of frequencies in such a labeling is referred to as the λ-number of the graph. Let n be odd ≥5, k=(n-3)/2 and let m<sub>0</sub>,...,m<sub>k-1</sub>, m<sub>k</sub> each be a multiple of n. It is shown that λ(Cm<sub>0</sub>&square;···&square;Cm<sub>k-1</sub>) is equal to the theoretical minimum of n-1, where C<sub>r</sub> denotes a cycle of length r and "&square;" denotes the Cartesian product of graphs. The scheme works for a vertex partition of Cm<sub>0</sub>&square;···&square;Cm<sub>k-1</sub>&square;Cm<sub>k</sub> into smallest (independent) dominating sets.
 
Article
The inherent properties of carry-free operations, parallelism and fault-tolerance have made the residue number system a promising candidate for high-speed arithmetic and specialized high-precision digital signal-processing applications. However, the reverse conversion from the residues to the weighted binary number has long been the performance bottleneck, particularly when the number of moduli set increases beyond 3. In this paper, we present an elegant residue-to-binary conversion algorithm for a new 4-moduli set {2<sup>n</sup> $1, 2<sup>n</sup>, 2<sup>n</sup> + 1, 2<sup>2n</sup> + 1}. The new Chinese remainder theorem introduced recently has been employed to exploit the special properties of the proposed moduli set where modulo corrections are done without resorting to the costly and time consuming modulo operations. The resulting architecture is notably simple and can be realized in hardware with only bit reorientation and one multioperand modular adder. The new reverse converter has superior area-time complexity in comparison with the reverse converters for several other 4-moduli sets.
 
Article
In this paper, the passivity-based approach is used to derive a tuning algorithm for a class of dynamic neural networks. Several stability properties, such as passivity, asymptotic stability, input-to-state stability and bounded input-bounded output stability, are guaranteed in certain senses
 
Article
A fast terminal dynamics is proposed and used in the design of the sliding-mode control for single-input single-output nonlinear dynamical systems. The inherent dynamic properties of the fast terminal sliding modes are explored and conditions to ensure its applicability for control designs are obtained
 
Article
Discrete linear repetitive processes are a distinct class of two-dimensional (2-D) linear systems with applications in areas ranging from long-wall coal cutting through to iterative learning control schemes. The feature which makes them distinct from other classes of 2-D linear systems is that information propagation in one of the two independent directions only occurs over a finite duration. This, in turn, means that a distinct systems theory must be developed for them. In this paper a complete characterization of stability and so-called pass controllability (and several resulting features), essential building blocks for a rigorous systems theory, under a general set of initial, or boundary, conditions is developed. Finally, some significant new results on the problem of stabilization by choice of the pass state initial vector sequence are developed
 
Article
In the above paper [see ibid., vol. 45, p. 998-1002, 1998] Bharadwaj et al, have suggested two changes for Piestrak's technique [1995]. It may be recalled that the first stage in Piestrak's converter contains two levels of 2n bit carry-save adders each comprising of 2n full adders since four inputs need to be added. Interestingly, Dhurkadas's modification [1998] of Pieshak' s technique reduces the four addends to three, thus needing one level of carry-save adders only. We would like to make some observations on this modification. The authors' reply is included
 
Article
This work presents a high speed realization of a residue to binary converter for the (2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1), moduli set, which improves upon the best known implementation by almost twice in terms of overall conversion delay. This significant speedup is achieved by using just three extra two input logic gates. Interestingly, by exploiting certain symmetry in operands, we also reduce the hardware requirement of the best known implementation by n-1 full adders. Finally, the proposed converter eliminates the redundant representation of zero using no extra logic
 
Article
A model of the linear R-2R ladder digital-to-analog converter (DAC) is developed in terms of the ratios of the effective resistances at the nodes of the ladder. This formulation demonstrates clearly why an infinite number of different sets of resistors can produce the same linearity error and shows how this error can be reduced by trimming. The relationship between the weights of the bits and the resistor ratios suggests appropriate trimming, design, and test strategies
 
Article
A new full-swing BiCMOS dynamic carry look-ahead (CLA) circuit with carry skip is presented. The test circuit with a 3.3 V supply has been implemented in a BiCMOS technology featuring 0.8 μm design rules. It shows an operation speed about 3 times higher than that of the CMOS one. Moreover, the circuit has no problems of static power dissipation, race, and charge redistribution
 
a Power spectral density of noise in 16-channel cochlear lter bank with C = 5 :0 pF and other parameters as earlier deened, and b RMS noise as a function of center frequency. 
Article
We detail the design of multiresolution analog filter banks, linear models of cochlear function, with power dissipation being a prime engineering constraint. We propose that a reasonable goodness criterion is the information rate through the system, per watt of power dissipated. Speech applications requiring filter banks with a wide frequency tuning range, from 20 Hz to 20 kHz, and low power consumption make the transconductance-C integrator in subthreshold CMOS the preferable integrator structure. As an example, the dynamic range of a lowpass filter is computed and subsequently used to design a filter bank that models faithfully cochlear micro-mechanics. The power consumption of the entire filter bank is computed from analytical expressions and is estimated as 355 nW, at 68 kb/s overall information rate at the output of the system
 
Article
A two's complement bit-serial arithmetic unit (AU) that operates at very high clock rates is presented in this paper. It is designed for a bit-serial SIMD data-path architecture and can perform several different arithmetic operations; for example sum-of-two-products. In order to attain a very high clock rate, the AU circuitry employs the true single-phase clocking (TSPC) technique, which encourages a high degree of pipelining. A 5-bit AU chip on an active area of 0.073 mm<sup>2</sup> has been fabricated in a 1.0-μm standard CMOS process. Tests have verified correct chip operation up to a clock rate of 470 MHz at V<sub>dd</sub>=5 V. At this frequency the AU power consumption is 11.5 mW
 
Article
The reduction of the supply voltage forces one to develop system and circuit solutions able to achieve the same performance previously obtained with higher supply voltage. In this paper, a second-order low-pass continuous-time filter operating at a 3 V power supply is presented. The prototype filter is implemented using a highly linear pseudo-differential transconductor. The input common-mode signal is canceled at the transconductor level using a feed-forward path. The output common mode voltage is controlled at the filter level using lossy integrators. A prototype cell has been realized in 1.2 μm BiCMOS technology. The pole frequency can be tuned in the range 12-55 MHz. A THD of -40 dB is achieved for signals up to 1 V<sub>pp</sub> at 10 MHz. The dynamic range is approximately 60 dB
 
Article
A process variation tolerant silicon carbide CMOS operational amplifier intended for high-temperature operation with a tunable phase margin and unity-gain bandwidth is presented. A novel bias circuit is provided such that the voltage gain of the operational amplifier is insensitive to large threshold voltage and mobility variations. An output stage along with an adaptive biasing technique is developed to produce a full rail-to-rail output voltage swing and a low output resistance. To achieve a large phase margin in the presence of large process variations, a compensation structure using a tunable external voltage is also proposed
 
Article
We introduce a limiting case of a nonlinear dynamical optical system one of which we have shown in previous publications the possibility of self-synchronization. A static synchronization scheme permits us to prove the synchronization and to realize a very simple setup. A chaos switching modulation scheme is proposed. Experimental results on synchronization are presented and discussed
 
Article
The problem of evaluating matrix polynomial I+A+A<sup>2</sup>+···+A<sup>N-1</sup>, has been considered. The proposed algorithms require at most 3·[log<sub>2 </sub> N] and 2·[log<sub>2</sub> N]-1 matrix multiplications, respectively. If the binary representation of N is (i<sub>t</sub>i<sub>t-1</sub>···i<sub>1</sub>i <sub>0</sub>)<sub>2</sub>, then the number of the matrix multiplication for the evaluation of this polynomial is at least 2·[log<sub>2 </sub> N]-2+i<sub>t-1</sub>. In the present communication the authors prove that for many values of N there exists an algorithm requiring a fewer number of matrix multiplications, thus disproving Lei-Nakamura's conjecture
 
Article
A new implementation for a floating controlled resistance operating in class AB is introduced. This uses a new translinear mixed loop of eight bipolar transistors. The circuit has been biased with DC current in such a way that it works effectively in class AB. A new building block, the third-generation controlled current conveyor (CCCIII) is then implemented. This has been obtained simply by adding a supplementary output terminal Z to duplicate the current flowing through the controlled resistance above. Simulation results, using the nominal parameters of the ALA200 bipolar arrays from ATT, demonstrate the high possibilities of the circuit. With ±1.5 V supply voltage, the power consumption of this wideband conveyor (-3 dB bandwidths greater than 30 MHz) is less than 7 mW as soon as the controlled resistance becomes lower than 250 Ω. An application example, consisting of a sinusoidal controlled oscillator, implemented from a transimpedance operational amplifier, is finally given to illustrate the versatility of the circuit
 
Article
In this brief, a new method for analytically evaluating the harmonic distortion (HD) in class-AB stages is introduced. It is based on modeling each push-pull device in the stage with a different third-order polynomial. The coefficients of these polynomials are then evaluated by straightforward computations or by pencil-and-paper analysis on the transcharacteristic of the stage. The resulting theory was validated by simulations and is able to predict the HD behavior of a class-AB stage over a wide range of input values. An example of the use of the theory for pencil-and-paper analysis is also given.
 
Article
A new CMOS programmable rail-to rail transconductor is presented. A linear V-I characteristic is obtained by using the principle of nonlinearity cancellation of matched MOS transistors operating in the ohmic region. Rail-to-rail operation is achieved by using two complementary blocks. The circuit is suitable for low voltage as it can operate from supply voltages down to ±1.5 V. PSpice simulations show that the transconductance gain can be electronically tuned from 13 to 90 μ A/V with bandwidth of about 40 MHz
 
Article
An analytical study of the transient response of a CMOS class AB opamp operating in a voltage follower configuration is presented. As with class A opamps, we identify nonlinear and linear regions of operation corresponding to slewing and settling periods in the transient response. But in contrast with class A opamps, it is shown that the feedback configuration should be considered for the entire duration of the transient response. It is shown that doublets (pole-zero pairs) have significant impact on the transient response of the class AB opamps in both nonlinear and linear regions of operation. One result is that in order to prevent overshoot in the transient response due to the doublets, the pole of the double should be located at a frequency higher than about four times the unity-gain bandwidth. The proposed analytical model is valid for any location of the doublets. It agrees well with the results of HSPICE computer simulations, and has the advantage over the latter of providing circuit designers with a clear relationship between the design goals and the device parameters
 
Article
The authors investigate the absolute exponential stability (AEST) of neural networks with a general class of partially Lipschitz continuous (defined in Section II) and monotone increasing activation functions. The main obtained result is that if the interconnection matrix T of the network system satisfies that -T is an H-matrix with nonnegative diagonal elements, then the neural network system is absolutely exponentially stable (AEST); i.e., that the network system is globally exponentially stable (GES) for any activation functions in the above class, any constant input vectors and any other network parameters. The obtained AEST result extends the existing ones of absolute stability (ABST) of neural networks with special classes of activation functions in the literature
 
Article
This paper studies the problem of robust absolute stability of a class of nonlinear discrete-time systems with time-varying matrix uncertainties of polyhedral type and multiple time-varying sector nonlinearities. By using the variational method and the Lyapunov second method, criteria for robust absolute stability are obtained in different forms for the class of systems under consideration. Specifically, we determine the parametric classes of Lyapunov functions which define the necessary and sufficient conditions of robust absolute stability. We apply the piecewise-linear Lyapunov functions of the infinity vector norm type to derive an algebraic criterion for robust absolute stability in the form of solvability conditions of a set of matrix equations. Some simple sufficient conditions of robust absolute stability are given which become necessary and sufficient for several special cases. An example is presented as an application of these results to a specific class of systems with time-varying interval matrices in the linear part.
 
Article
This letter presents a proof of Kaszkurewicz and Bhaya's conjecture (1995) on the absolute stability of neural networks in the two-neuron case. The conjecture states that the necessary and sufficient condition for absolute stability of neural networks with an n×n interconnection matrix T is T∈I<sub>0</sub>, where I<sub>0</sub> denotes the class of matrices T such that matrix (T-D<sub>1</sub>)D<sub>2</sub> has all eigenvalues with negative real parts for arbitrary positive diagonal matrices D<sub>1</sub> and D<sub>2 </sub>. A characterization condition for the I<sub>0</sub> class of matrices in the two-dimensional (2-D) case n=2 is also obtained
 
Article
This letter points out that a statement in the above letter [see ibid., vol.42, p.497-9, 1995] saying that the sufficiency part of absolute stability result on neural networks includes the sufficiency part of the absolute stability result in Forti et al. [see Proc. 1994 IEEE Int. Symp. Circuits Systems, p.241-4, April 1994], is not correct under the stated conditions. On the other hand, it is shown that the sufficiency part of absolute stability result in Forti et al. is included by the sufficiency part of a conjecture stated in the above letter
 
Article
We consider the problem of absolute stability of linear feedback systems in which the control is a sector-bounded time-varying nonlinearity. Absolute stability entails not only the characterization of the "most destabilizing" nonlinearity, but also determining the parametric value of the nonlinearity that yields instability of the feedback system. The problem was first formulated in the 1940s, however, finding easily verifiable necessary and sufficient conditions for absolute stability remained an open problem all along. Recently, the problem gained renewed interest in the context of stability of hybrid dynamical systems, since solving the absolute stability problem implies stability analysis of switched linear systems. In this paper, we introduce the concept of generalized first integrals and use it to characterize the "most destabilizing" nonlinearity and to explicitly construct a Lyapunov function that yields an easily verifiable, necessary and sufficient condition for absolute stability of second-order systems.
 
Article
This letter points out that a new majorization of the derivative of the Lyapunov function used in the above letter [E. Kaszkurewicz and A. Bhaya, Comments on “Necessary and sufficient condition for absolute stability of neural networks”, IEEE Trans. Circuits Syst., I, Fundam. Theory Appl. 42, No. 8, 497-499 (1995; Zbl 0850.93698)] gives a new, weaker condition on the interconnection matrix that is sufficient for the global asymptotic stability (GAS) of the equilibrium point for dynamical neural networks. The result also includes some earlier results derived in the literature.
 
Article
Proposes to study the absolute periodicity of delayed neural networks. A neural network is said to be absolutely periodic, if for every activation function in some suitable functional set and every input periodic vector function, a unique periodic solution of the network exists and all other solutions of the network converge exponentially to it. Absolute stability of delayed neural networks is also studied in this paper. Simple and checkable conditions for guaranteeing absolute periodicity and absolute stability are derived. Simulations for absolute periodicity are given
 
Article
This letter points out that a Liapunov function used by the present authors in an earlier publication on absolute and structural stability of neural circuits easily proves a stronger version of the sufficient part of the result contained in the paper by Forti, Manetti and Marini (1994) as well as in a subsequent publication. Comments are made on the set of interconnection matrices that determine necessary and sufficient conditions for absolute stability of the class of neural circuits considered and as a consequence a conjecture is formulated.< >
 
Article
This paper presents new results on the absolute exponential stability (AEST) of neural networks with a general class of partially Lipschitz continuous and monotone increasing activation functions under a mild condition that the interconnection matrix T of the network system is additively diagonally stable; i.e., for any positive diagonal matrix D<sub>1</sub>, there exists a positive diagonal matrix D<sub>2</sub> such that D<sub>2</sub> (T-D<sub>1</sub>)+(T-D<sub>1</sub>)<sup>T</sup>D <sub>2</sub> is negative definite. This result means that the neural networks with additively diagonally stable interconnection matrices are guaranteed to be globally exponentially stable for any neuron activation functions in the above class, any constant input vectors and any other network parameters. The additively diagonally stable interconnection matrices include diagonally semistable ones and H-matrices with nonpositive diagonal elements as special cases. The obtained AEST result substantially extends the existing ones in the literature on absolute stability (ABST) of neural networks. The additive diagonal stability condition is shown to be necessary and sufficient for AEST of neural networks with two neurons. Summary and discussion of the known results about ABST and AEST of neural networks are also given
 
Article
In this brief, a linear-matrix inequality (LMI) based strictly-positive-real (SPR) characterization and its application to absolute stability problem for discrete-time descriptor systems is addressed. After giving the definition of SPR, the Cayley transformation is used to establish formulas bridging the admissible descriptor form realizations for SPR and strictly-bounded-real transfer matrices. Based on these, an LMI-based necessary and sufficient condition for a descriptor system to be, simultaneously, admissible and SPR is derived. The obtained result is further applied to the absolute stability problem involving a linear time-invariant descriptor system and a memoryless time-varying nonlinearity. Numerical tractability of the results are illustrated by two examples.
 
Article
The main result obtained in this paper is that for a neural network with interconnection matrix T, if -T is quasi-diagonally row-sum or column-sum dominant, then the network system is absolutely stable. The above two sufficient conditions for absolute stability are independent of the existing sufficient ones in the literature. Under either of the above two sufficient conditions for absolute stability, the vector field defined by the network system is also structurally stable
 
Article
In this paper, we present a sufficient condition for absolute stability of a larger class of dynamical neural networks. It is shown that the H-matrix condition on the interconnection matrix ensures the existence, uniqueness and global asymptotic stability (GAS) of the equilibrium point with respect to slope-limited activation functions
 
Article
The main result that for a neural circuit of the Hopfield type with a symmetric connection matrix T, the negative semidefiniteness of T is a necessary and sufficient condition for absolute stability was obtained and proved by rather complex procedures by Forti et al. [1994]. This brief gives a very simple proof of this result, using only the well-known total stability result about Hopfield type neural circuits with a symmetric connection matrix and the basic algebraic properties of real symmetric matrices
 
Article
The switch-mode DC-to-AC inverter using a DC-to-DC converter configuration has many advantages over the traditional bridge-type inverter. The previously presented circuit with nonlinear robust control works only for resistive load and its output voltage has considerable distortion near the zero-crossing point. A novel bidirectional circuit with nonlinear robust control is proposed in this paper to overcome those drawbacks. This inverter can dynamically stabilize the output voltage, i.e., the output voltage of the inverter remains dynamically unchanged when subjected to large disturbances in the input voltage or output load. The stability analysis is presented. The closed-loop control system under P control, PI control, PD control, and PID control of the voltage loop for different types of loads are investigated. The results show that the PD control is the best choice. The performance of the circuit is also studied. Computer simulation and experimental results are provided
 
Article
This paper first addresses the power system stability issue involving the regular generator-angle transient stability and load-driven voltage instability. Transient stabilization of simplified power systems equipped with the flexible AC transmission system (FACTS) device, the thyristor-controlled series capacitor (TCSC), is studied with consideration of unknown loads. With some off-line time-optimal trajectories computed based on the switching-times-variation method (STVM), some techniques are developed to synthesize robust near-time-optimal neural controllers. The theoretical support for these techniques is presented. The simulations illustrate the performance of the synthesized neural controllers. Furthermore, the results developed can be readily generalized to more general nonlinear systems
 
Article
This paper addresses the problem of worst-case tolerance analysis of steady states in linear DC and AC electric circuits. The statement of the problem considered is in the form of linear algebraic equations whose elements are, in the general case, nonlinear functions of a given set of independent interval parameters. Three kinds of solutions are considered: 1) outer solution; 2) inner solution and 3) exact solution. A direct method for computing an outer solution and an iterative method for finding an inner solution are suggested. The inner and outer solutions thus found provide a tight two-sided bound on the exact solution of the tolerance problem investigated. The exact solution can be determined if certain monotonicity conditions are fulfilled. The verification of the conditions involves solving several associated outer solution problems. The computational efficiency of the methods suggested is demonstrated by a numerical example.
 
Article
A feasibility study of Σ-Δ modulation as a control mechanism for low-frequency DC-AC power inverters with sinusoidal output voltage is presented. The sinusoidal DC-AC inverter, composed of a Σ-Δ 1-bit A/D converter and a half-bridge inverter, was built and tested. Measured Bode plots of the closed-loop response are given and the output voltage waveform observed at 50 Hz is shown
 
Article
Presents analytical results, numerical simulations, and experiments that quantify effects of low-switching frequency in ac drives supplied by pulsewidth modulated (PWM) power electronic inverters. Specifically, the paper re-examines models of PWM inverters in cases when the switching frequency is only an order of magnitude higher than the fundamental of the ac waveform being synthesized. While the case of permanent magnet synchronous motor is studied in detail, the presented modeling procedure is applicable to other ac drives. Analytical results derived in the paper build on related results for do converters, and address the case of the PWM switching policy denoted as space vector modulation in industrial practice. Conventional modeling procedures assume that the PWM switching frequency is high enough so that the resulting waveform can be replaced by its first harmonic in control-oriented models. This paper provides analytical formulas in terms of the system parameters that quantify the deviations introduced by a slow PWM switching frequency
 
Top-cited authors
Leon O. Chua
  • University of California, Berkeley
Guanrong Chen
  • City University of Hong Kong
Michael Peter Kennedy
  • University College Dublin
Tao Yang
  • Chongqing University of Posts and Telecommunications
Jun Wang
  • The Chinese University of Hong Kong