# IEEE Transactions on Circuits and Systems

Published by Institute of Electrical and Electronics Engineers

Online ISSN: 0098-4094

Published by Institute of Electrical and Electronics Engineers

Online ISSN: 0098-4094

Publications

Article

This paper considers the local state model proposed by Givonne-Rosser Ill. It is shown that this model has a natural 1-D state variable realization which is independent of any scanning procedure. While attention is focused on the m = 2 case, extensions to m > 2 are readily available.

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Article

The structure of the reachability problem for

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Article

Design and experimental evaluation of a sixth-order fully integrated continuous-time 10.7-MHz bandpass filter are presented. Circuit performance is stabilized through on-chip tuning by a dual-loop master-slave control scheme that locks center frequency and bandwidth to an external reference signal. Difficulties in design and performance are discussed and corrections suggested where appropriate.

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Article

The paper describes the development of microelectronic active- RC 4-kHz-spaced channel bandpass filters (CBFls) for the frequency range 60-108 kHz, suitable for the formation and decomposition of the 12-channel bank (primary group) in direct-modulation-type FDM SSB telephone systems. The active filters are designed by simulation (essentially by Gorski-Popiel's method) of low-sensitivity LC filters which are the duals of some LC CBF's currently used in FDM systems in the U.K. Our circuit development is firmly based on the microelectronic technology adopted by us, in which naked-chip dual- or quad-operational amplifiers, laser-adjustable thick- or thin-film resistors, and NPO ceramic-chip capa- th p citors are used. In order to minimize cost, the circuits are designed to accept, as far as possible, capacitors with preferred (and preferably also equal) nominal values, and a resistor adjustment procedure has been developed which permits wide capacitor manufacturing tolerances of pm 10 percent. This adjustment procedure also provides compensation for the nonideal characteristics of the amplifiers, leading to near-perfect simulation of the nominal dissipationless LC prototype filters. Microelectronic models of channel 12 CBF (60-64 kHz) and channel 1 CBF (104-108 kHz) have been built (size of each filter: 50 mm times 30mm times 5mm ; dc power 400 mW). Channel 12 CBF meets the loss-frequency specification over the required temperature range 10-40°C. For channel 1 CBF the specification is met at ambient temperature (25°C) but not at 10°C or 4O°C; this will be remedied when amplifiers with higher f_{T} 's and/or lower f_T -temperature coefficients become available. Neither filter requires a channel equalizer (whereas their LC counterparts do), and preliminary nonlinearity, noise, and intermodulation tests had promising results.

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Article

A.D. Culhane et al. (1989) proposed a fast technique for computing
discrete Hartley and Fourier transforms using a Tank and Hopfield linear
programming neural network. It was proved mathematically that the
network is stable under some conditions. The network can also be used
for solving linear least squares error (LSE) problems. It is shown that
the stability of the network is guaranteed even under weaker conditions.
The author also provides a more accurate solution for the network
relaxation constants and discusses the accuracy of computation

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Article

In this paper new circuits for realizing actively compensated finite gain amplifiers (FGA's) using operational amplifiers (OA's) and resistors are given. In IC technology, as the characteristics of the OA's and the resistor ratios track closely with each other with temperature and other variations of ambient conditions, the compensation should hold under such varying conditions. An application is considered in active-RC filters. Experimental results confirm the theoretical predictions. These results show that one can expect a substantial improvement in the operating frequency range of the circuits that employ the new amplifiers over the conventional amplifiers or the existing ones using two OA's.

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Article

In the above-titled paper (see ibid., vol. CAS-34, p.1191-1198,
Oct. 1987) there are some errors in Tables I and II. Unfortunately, the
computer outputs for the original designs were not saved, and to be able
to correct the error, new designs were carried out for certain
functions. The new designs are slightly different from the original ones
owing to differences in the initialization of the optimization
algorithms. Consequently, the data given in Table II and the 3-D plots
are also revised

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Article

A novel realization of a switched-capacitor (SC) integrator is
proposed. The integrator attenuates the input during both clock phases,
so that the time constant of the integrator is realized with the product
of two capacitance ratios instead of a single capacitance ratio. The
capacitance spread only increases as the square root of the time
constant. This integrator is stray-insensitive. The influence of the
finite DC-amplifier gain and dynamic settling is the same as in
conventional SC integrators. A low-pass notch SC biquad is presented as
an example to show the capacitance advantage of the integrator. The
example also shows that the increase of amplifier offset is small if the
total offset of the entire SC filter is considered. It is shown that the
SC low-pass notch biquad reduces the total capacitance by a factor of
more than three

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Article

It is shown that the general gain-sensitivity product
Γ<sup>T</sup><sub>A</sub> does not change after performing
complementary transformation in a linear feedback system with a single
op amp

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Article

The authors show how a modification of their approach (see ibid., vol.36, p.1168-74, 1989) leads to the stability edges, correctly identified in the above-named work (see ibid., vol.38, p.1370-3, 1991) by K.I. Kang et al., for a diamond of complex polynomials. The feasibility of reduction from 32 to 16 distinguished edges is facilitated via use of Foster's (complex) reactance theorem in network theory

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Article

Switched-capacitor finite-impulse-response (FIR) low-pass filters
that can act as the first stage of the noise filter for a
delta-sigma-modulation-based digital-to-analog converter are presented.
The output of the filter can be generated at a reduced sampling rate
without increasing the noise in the baseband. The lower output sampling
rate relaxes the settling requirements of the operational amplifier. The
filters have the properties that the coefficients are symmetric and take
only integer values. These properties make them especially suitable for
MOS switched-capacitor implementation. A symmetric implementation that
has low sensitivity to capacitor mismatch is presented. The authors
focus on the decimation filter for a second-order delta-sigma modulator,
although extension to other order loops is possible

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Article

The capacitance ratio constraint for equal op-amp dynamic range is derived in this paper for a collection of important biquad configurations of all filter types. This completes the set of explicit design constraints for the determination of capacitance values. The relations between the total capacitance and design parameters such as omega_{0}T, Q and peak gain are then transparent to the designer. Computer simulation is no longer a necessity for achieving optimal dynamic range for the biquad. By analyzing a design example of [1], three observations are made with regard to the capacitor area efficiency of a biquad. These observations help the designers to quickly determine the capacitor area efficiencies of available biquad configurations. Different techniques are proposed to improve the capacitor area efficiency of existing biquads. It is shown that simply rearranging the clock phases and input capacitors according to these observations can result in new configurations that improve the total capacitance significantly. Another technique proposed in this paper splits the integrating capacitor of a biquad for different clock phases. In doing so, capacitors unnecessarily linked up with big integrating capacitors can be sealed down and significant saving in total capacitance is achieved. Influence of this technique on the error due to op-amp gain being finite is discussed. Comparisons of the new techniques with the published examples show that 30 to 40-percent savings in total capacitance can be achieved.

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Article

The implementation of a 16×16 discrete cosine transform
(DCT) chip using a concurrent architecture is presented. The chip
contains 32 processing elements working in parallel and a random-access
memory (RAM) which performs a 16×16 matrix transposition. The
structure is highly regular and modular, and thus very efficient for
VLSI implementation. The chip was designed for real-time processing of
14.3-MHz sample video data. It performs an equivalent of a half billion
multiplications and accumulations per second. Fabricated in 2-μm
double-metal CMOS technology, the chip contains approximately 73000
transistors which occupy a 7.2×7.0-mm<sup>2</sup> area. The 68-pad
die size is 8.3×8.1 mm<sup>2</sup>. It is fully functional and is
the first working 16×16 DCT chip. The architecture and accuracy
studies for finite-wordlength processing are presented. The circuit
design and layout using the symbolic design tool MULGA are described in
detail. Possible variations are also discussed for multipurpose
(variable transform sizes, forward-inverse transform) applications

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Article

Delta modulation (DM) is an attractive method of analog-to-digital (A/D) conversion in applications where simple and economical designs must be realized without sacrificing conversion quality. This paper describes a new single-chip, bipolar integrated circuit delta modulator that maintains a high conversion resolution over a wide range of sampling frequencies and ambient conditions. Its high-speed operation (maximum sampling rates greater than 15 Mbit/s) is achieved with lower power requirements than with comparable discrete realizations. Low sensitivities to power supply and ambient temperature variations, achieved with a novel logic design, make this circuit useful in a telephone switching office environment and as a building block for other linear and companded analog-to-PCM converters.

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Article

A synthesis procedure for arbitrary symmetrical four-port networks
is presented. It is based on the use of four frequency-invariant
180° hybrids. An experimental realization which uses four flatpack
180° hybrids is described. Some 3-dB lumped element 90° hybrids
are synthesized

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Article

Key developments in the teaching of circuit theory are traced over the past half century at the graduate and undergraduate levels.

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Article

This paper presents a framework for Fiding efficient multiprocessor realizations of digital filters. Based on simple graph-theoretic concepts, a method is derived for determining the minimal sampling period of a given digital filter structure when the speed of arithmetic operations is given but the number of processing units Is unlimited. It Is shown how realistic hardware implementations can be found and evaluated by using the timing diagram of this maximal rate realization as a starting point. The minimal sampling periods of several common digital filter structures are given in terms of addition and multiplication times.

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Article

For original paper see ibid., vol.36, p.1153-58 (1989). The
commenter claims that the proof that M <sub>12</sub>= M
<sub>21</sub> based on stored energy is correct. He briefly reviews the
author's arguments and conventional proofs. In his reply, P.M. Lin
disagrees with the commenter

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Article

If only a segment of a function f (t) is given, then its Fourier spectrum F(omega) is estimated either as the transform of the product of f(t) with a time-limited window w(t) , or by certain techniques based on various a priori assumptions. In the following, a new algorithm is proposed for computing the transform of a band-limited function. The algorithm is a simple iteration involving only the fast Fourier transform (FFT). The effect of noise and the error due to aliasing are determined and it is shown that they can be controlled by early termination of the iteration. The proposed method can also be used to extrapolate bandlimited functions.

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Article

A multiple-feedback universal active filter is presented and evaluated on the basis of its sensitivity performance. This canonic realization provides, simultaneously, second-order low-pass, bandpass, and highpass outputs that may be combined to implement generalized biquadratic transfer functions. Additionally, it features the capability of local positive feedback to allow Q -enhancement with the ensuing advantages of sensitivity minimization and reduction in RC -element spread. A new analysis technique is developed for the evaluation of omega_0 and Q sensitivities to operational-amplifier (OA) dc gain and gain-bandwidth product. This technique is extended to modify the figure of merit, introduced for sensitivity minimization purposes by Fleischer, and thus leads to easily obtainable expressions for optimum Q -enhancement factor and the corresponding value of Q in the absence of positive feedback. Making use of this sensitivity analysis technique, the new design is compared to two other high- Q filter configurations widely known for their excellent sensitivity characteristics. It is concluded that the new filter exhibits comparable performance especially in higher tolerance applications using wide-bandwidth OA's.

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Article

Theoretical and experimental results of the clock-feedthrough
phenomenon (charge injection) in sample-and-hold circuits using minimum
feature size transistors of a self-aligned 3-μm CMOS technology are
compared. The lumped RC model of the conductive channel has
been used and verified in different switch configurations, including
variable input voltages. Special emphasis is laid on the feasibility and
limits of charge cancellation techniques using dummy switch
designs

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Article

A relationship between a lossless discrete integrator (LDI) transformed inductor and a bilinear transformed inductor is presented. By applying this simple relationship, switched-capacitor (SC) filters using LDI structures can be used to realize bilinear transformed transfer functions, thus eliminating termination errors that usually exist in SC filters.

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Article

A general noise analysis procedure for single-amplifier feedback systems Is presented and applied to second-order active networks. Noise power spectral density and broad-band noise at the output terminal are calculated using a noise transfer function (NTF). The frequency dependence of the NTF is governed by the poles of the signal transfer functions and is independent of its transmission zeros. It is shown that the noise performance can be optimized by proper design of the passive network. A circuit classification based on the configuration of the feedback network is used for noise comparison and simple formulas applicable to many practical filter applications are presented.

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Article

A method is presented for the design of switched-capacitor bandpass filters using the bilinear z -transform. The filters are realized in low-sensitivity coupled-biquad structures and employ biquad circuits which are completely insensitive to stray capacitances between any node and ground. Geometrically symmetric (both all-pole and finite-transmissionzeros) as well as general-parameter filters are treated.

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Article

A parallel-in-parallel-out systolic array and a
serial-in-serial-out systolic array are proposed for fast multiplication
in finite fields GF (2<sup>m</sup>) with the standard basis
representation. Both of the architectures possess features of
regularity, modularity, concurrency, and unidirectional data flow. As a
consequence, they have high throughput rates and are well suited to VLSI
implementation with fault-tolerant design. As compared to the related
multipliers presented by C.S. Yeh et al. (see IEEE Trans. Comput.,
vol.C-33, p.357-360, Apr. 1984), the proposed parallel implementation
makes it easier to incorporate fault-tolerant design, and the proposed
serial implementation requires only one control signal instead of two

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Article

A novel systolic array for the implementation of a second-order IIR (infinite-impulse response) transfer function expressed in terms of Z <sup>-N</sup> is presented. The array is suitable for any value of N greater than or equal to two. The major advantages of this systolic array include nearest-neighbour interconnection and a requirements of only three identical basic cells

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Article

An expression is derived for the output resistance of a switched R -2R ladder.

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Article

A finite-difference method for finding the finite-power solution phi of nabla^{2} phi - c^{2} phi = g in a semi-infinite medium with an irregular boundary is established. The method is radically different from the customary approach of simply truncating the medium in that the semiinfinite medium outside a strip that contains the irregular boundary is characterized by an operator-valued driving-point resistance and thereby removed from the first stage of the method. The solution within the strip is then determined by exploiting the theory of operator-valued finite ladder networks. Finally, the solution for the medium outside the strip is obtained by using the theory of infinite operator-valued ladder networks. This method is applied to a two-dimensional study of the minority-carrier density in the base region of a lateral bipolar transistor on a chip that is effectively infinitely deep so far as the transistor's behavior is concerned. The method is quite conservative of computer time.

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Article

The Volterra-Wiener series is used to obtain an analytical formula for slew-induced distortion (SID) in single-amplifier active filters. It is shown that the relative change of the transfer function caused by SID depends on the parameters of the operational amplifier (OA) and on the method of frequency compensation applied to it. This change also depends on the transfer function to be realized, on the amplitude of the input signal and on the gain-sensitivity product (GSP). It is shown that reducing the GSP also reduces the SID. The corresponding relationship was verified experimentally.

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Article

We describe how several optimization problems can be rapidly solved by highly interconnected networks of simple analog processors. Analog-to-digital (A/D) conversion was considered as a simple optimization problem, and an A/D converter of novel architecture was designed. A/D conversion is a simple example of a more general class of signal-decision problems which we show could also be solved by appropriately constructed networks. Circuits to solve these problems were designed using general principles which result from an understanding of the basic collective computational properties of a specific class of analog-processor networks. We also show that a network which solves linear programming problems can be understood from the same concepts.

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Article

A new approach for extending the useful operating frequency range of linear active networks realized using operational amplifiers (OA's) has been reported [1]. The extension in bandwidth (BW) is achieved by replacing each of the single OA's in the active realization by a suitable composite OA (CNOA) that has been constructed using N OA's. The use of the CNOA's to realize inverting integrators and active filters is presented here. The considerable performance improvement of these realizations is demonstrated both theoretically and experimentally. Their comparison with state-of-the-art designs is also given.

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Article

This paper presents a method for the analysis of switched-capacitor (SC) networks in the frequency and time domains by the use of general-purpose circuit simulation programs such as SPICE. It is shown how the z -domain equivalent circuit can be modeled exactly in the continuous-time domain using the lossless transmission line element of the simulation program to implement the required one-port storage element (storistor). The resulting continuous-time equivalent circuit retains the sample-data characteristics of the SC networks and is not restricted to frequencies below the Nyquist rate. It is also shown that the transmission line element can be used to simulate the (sin x)/x effect on the frequency response of the SC network due to the sample-and-hold process. Examples of the simulation of simple SC networks with and without op amps using SPICE are given.

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Article

The problem of wiring an arbitrary knock-knee layout (in a square
grid with an arbitrary number of modules) in three and two layers using
a small number of vias is investigated. A technique is proposed for
transforming a knock-knee layout into a three-layer wirable layout by
replacing knock-knees with 45° wires. A 45° replacing algorithm
to achieve three-layer wirability is introduced. An efficient stretching
technique to ensure two-layer wirability using 45° wires is
described. Conversion of an abstract layout into a corresponding
physical layout is discussed. Experimental results are presented

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Article

This paper describes an algorithm and its hardware implementation which converts the 3 moduli (2^{n} - 1,2^{n}, 2^{n} + 1) residue numbers into their binary representation. The given technique requires only binary adders, and no look-up tables. antages of this approach are two-fold: 1) It enables an extremely wide, fixed-point dynamic range, since its upper bound is not limited by a memory size. 2) The Integrated Circuit area required for its realization can be directly traded off with conversion speed. As a result, a 66-bit convertor with a conversion time of 120 ns, or a 36-bit one with 40 ns, may be implemented as single CMOS chips with 3 mu m geometries.

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Article

The design, fabrication, and preliminary testing of an integrated
circuit implementing neural network (NN) models with 256 on-chip, fully
interconnected neurons and programmable analog synapses are reported.
The integrated circuit was built using a
charge-coupled-device-(CCD)-based architecture. A study of the current
efforts to develop NN hardware reveals that the conventional electronic
approach suffers from two major problems: (1) a tradeoff between the
complexity of the synapse and the number of synapses per chip; and (b)
the I/O (input/output) problem, namely, the slow communication between
the chip and the surrounding environment. This approach circumvents the
problems by using CCD arrays and/or a spatial light modulator as a
short-term memory for the device. The preliminary results presented
serve to validate the assumptions on which the CCD approach is based and
to reassess the potential of this approach. The CCD architecture is
based on two main assumptions: (a) the revolving charge packets in the
CCD rings can complete several full cycles without substantial decay,
(thus the required refresh of the matrix from an external memory will
not significantly degrade the overall operation speed) and (b) the
multiplication process, namely, the nondestructive sensing of the
W<sub>ij</sub> packets revolving in the CCD rings and their accumulation
(provided the respective V <sub>j</sub> is on) can be
accomplished accurately and quickly. It is now clear that both these
assumptions are valid

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Article

The different nonlinear distortion measures in single-amplifier active filters are discussed and the relationships between these measures given. The analysis presented is based on the Volterra-Wiener series approach used in many articles to model nonlinear circuits and systems with mild nonlinearities. Examples of active RC filters illustrate the relationships developed.

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Article

The synthesis of fan filters [1] is approached using a procedure developed by Hirano and Aggarwal [4] and an index transformation given by Chang and Aggarwal [5] which rotates the prototype frequency response 45° . A polynomial factorization reduces the realization algorithm to a series-parallel combination of four one-dimensional all-pass filters. A simplified structure for digital all-pass filters is indicated. An efficient method of approximating zero phase shift is indicated. The associated numerical synthesis procedure consists of evaluating a single equation for a number of arguments. The realization of a fan filter based on an M th-order one-dimensional prototype requires M - 1 multiplications per point.

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Article

The transfer function of a fan filter is derived in [1] using transformations on a prototype Butterworth filter. We present an alternate derivation which is much simpler than that of [1] and provides a useful insight leading to more efficient fan filters.

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Article

The general configuration of a delay line/90° phase difference network having a single input and two outputs is defined. The group delay from the input to each output is specified over a frequency range as well as the phase difference between the two outputs. A procedure is outlined for obtaining the singularities associated with this type of configuration. The general procedure for realizing active networks corresponding to the singularities is discussed. The actual active network realizations are obtained in a form that is easily implemented as a thickfilm hybrid circuit.

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Article

A new design method is developed for 90 ° phase-splitting networks which have arbitrary single-sideband suppression characteristic. The proposed method is based on the insertion loss filter design approach. Characteristic function of a 90 ° phase-splitting network is defined, and Its properties are investigated. The investigation leads to the development of a design procedure by which a computer program can be readily used with minor modification of subprograms in an automatic filter synthesis procedure. Several examples show versatility of the proposed method.

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Article

For the original article see ibid., vol.ASSP-26, P.334-8 (1978). The commenter states that the improved sufficient condition given by W.L. Mills et al., first suggested by K. Meerkotter (Proc. ISCAS p.295-8, 1976), was also explicitly shown by the commenter (Proc. Int. Conf. on Acoustics, Speech and Signal Processing, p.517-20, Apr. 1986), who applied it to the design of novel second-order structures, such as the modified Agarival-Burrus structure.< >

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Article

On the basis of a theorem of Barkin, a number of criteria are derived which give sufficient conditions for the absence of zero-input limit cycles in discrete-time and especially digital systems. These criteria are formulated in the frequency domain and provide a possibility of investigating the absence of a zero-input limit cycle of a specific length N . Depending on the particular characteristics of the nonlinearities and the number of nonlinearities in the system, different criteria are obtained. Application of the criteria results in most cases in a linear programming problem. The solutions to this problem for the case of a second-order digital filter with one and with two quantization nonlinearities are discussed.

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