IEEE Electron Device Letters

Published by Institute of Electrical and Electronics Engineers
Print ISSN: 0741-3106
Publications
High performance n- and p-channel thin-film transistors (TFTs) have been fabricated in polycrystalline silicon films using a self-aligned-gate process without exceeding 550 degrees C. This process features the use of polycrystalline Si/sub 0.5/Ge/sub 0.5/ for the gate material and high-dose H/sup +/ implantation for grain-boundary passivation so that shorter process times can be used. Low threshold voltages of 2.8 and -0.2 V, and high field-effect mobilities of 35 and 28 cm/sup 2//V-s, where achieved by the NMOS and PMOS devices, respectively. The performance of these devices is comparable to that of previously reported devices fabricated using process temperatures up to 600 degrees C, and is adequate for large-area-display peripheral driver circuits. The significant reduction in maximum process temperature makes this process advantageous for the fabrication of CMOS circuits on large-area glass substrates.< >
 
We have developed high-performance enhancement-mode InP-based modulation-doped field-effect transistors with 0.03 /spl mu/m gate-length. A record high current gain cutoff frequency exceeding 300 GHz has been achieved, and the maximum extrinsic transconductance is as high as 2 S/mm with an associated drain current of 0.5 A/mm at a drain bias of 1 V. This high performance is a result of the reduction or gate length, the use of the high barrier metal Pt as gate electrodes, and most importantly the employment of the well-developed wet-etching technology that allows the formation of a very deep gate groove while retaining small side etching. The excellent E-MODFET performance opens up the possibility of implementing ever faster high-speed circuits based on direct-coupled FET logic.
 
AlGaAs/InGaAs/GaAs P-n-p heterojunction bipolar transistors (HBTs) have been fabricated using a dual selective etch process. In this process, a thin AlGaAs surface passivation layer surrounding the emitter is defined by selective etching of the GaAs cap layer. The InGaAs base is then exposed by selective etching of the AlGaAs emitter. The resulting devices were very uniform, with current gain varying by less than +or-10% for a given device size. Current gain at a given emitter current density was independent of device size, with gains of over 200 obtained at current densities above 5*10/sup 4/ A/cm/sup 2/.< >
 
Current-voltage characteristics of ultrashallow p+-n and n+-p diodes, obtained using very low-energy (<500 eV) implantation of B and As, are presented. P+-N junctions were formed by implanting B+ ions into n-type Si (100) at 200 eV and at a dose of 6 x 1014 cm-2, and n+-p were obtained by implanting As+ ions into p-type (100) Si at 500 eV and at a dose of 4 x 1012 cm-2. A rapid thermal annealing (RTA) of 800°C/10 s was performed before I- V measurements. Using secondary ion mass spectrometry (SIMS) on samples in-situ capped with a 20-nm 28Si isotopic layer grown by low-energy (40 eV) ion-beam deposition (IBD) technique, the depth profiles of these junctions were estimated to be 40 and 20 nm for p +-n and n+-p junctions, respectively. These are the shallowest junctions reported in the literature. The results show that these diodes exhibit excellent I-V characteristics, with ideality factor of 1.1 and a reverse bias leakage current at -6 V of 8 x 10-12 and 2 x 10-11 A for p+-n and n+-p diodes, respectively, using a junction area of 1.96 x 10 -3 cm2.
 
A novel Ti self-aligned silicide (salicide) process using a combination of low dose molybdenum and preamorphization (PAI) implants and a single rapid-thermal-processing (RTP) step is presented, and shown to be the first Ti salicide process to achieve low sheet resistance at ultrashort 0.06-/spl mu/m gate lengths (mean=5.2 /spl Omega//sq, max=5.7 /spl Omega//sq at 0.07 /spl mu/m; mean=6.7 /spl Omega//sq, max=8.1 /spl Omega//sq at 0.06 /spl mu/m, TiSi/sub 2/ thickness on S/D=38 nm), in contrast with previous Ti salicide processes which failed below 0.10 /spl mu/m. The process was successfully implemented into a 1.5 V, 0.12-/spl mu/m CMOS technology achieving excellent drive currents (723 and 312 /spl mu/A//spl mu/m at I/sub OFF/=1 nA//spl mu/m for nMOS and pMOS, respectively).
 
We report room-temperature 0.07-/spl mu/m CMOS inverter delays of 13.6 ps at 1.5 V and 9.5 ps at 2.5 V for an SOI substrate; 16 ps at 1.5 V and 12 ps at 2.5 V for a bulk substrate. This is the first room-temperature sub-10 ps inverter ring oscillator delay ever reported. PFETs with very high drive current and reduction in parasitic resistances and capacitances for both NFETs and PFETs, realized by careful thermal budget optimization, contribute to the fast device speed. Moreover, the fast inverter delay was achieved without compromising the device short-channel characteristics. At V/sub dd/=1.5 V and I/sub off//spl sim/2.5 nA//spl mu/m, minimum L/sub eff/ is about 0.085 /spl mu/m for NFETs and 0.068 /spl mu/m for PFETs. PFET I/sub on/ is 360 /spl mu/A//spl mu/m, which is the highest value ever reported at comparable V/sub dd/ and I/sub off/. The SOI MOSFET has about one order of magnitude higher I/sub off/ than a bulk MOSFET due to the floating-body effect. At around 0.07 /spl mu/m L/sub eff/, the NFET cut-off frequencies are 150 GHz for SOI and 135 GHz for bulk. These performance figures suggest that subtenth-micron CMOS is ready for multi-gigahertz digital circuits, and has good potential for RF and microwave applications.
 
The authors have investigated the reliability performance of G-band (183 GHz) monolithic microwave integrated circuit (MMIC) amplifiers fabricated using 0.07-/spl mu/m T-gate InGaAs-InAlAs-InP HEMTs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel on 3-in wafers. Life test was performed at two temperatures (T/sub 1/ = 200 /spl deg/C and T/sub 2/ = 215 /spl deg/C), and the amplifiers were stressed at V/sub ds/ of 1 V and I/sub ds/ of 250 mA/mm in a N/sub 2/ ambient. The activation energy is as high as 1.7 eV, achieving a projected median-time-to-failure (MTTF) /spl ap/ 2 /spl times/ 10/sup 6/ h at a junction temperature of 125 /spl deg/C. MTTF was determined by 2-temperature constant current stress using /spl Delta/G/sub mp/ = -20% as the failure criteria. The difference of reliability performance between 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel and 0.1-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with In/sub 0.6/Ga/sub 0.4/As channel is also discussed. The achieved high-reliability result demonstrates a robust 0.07-/spl mu/m pseudomorphic InGaAs-InAlAs-InP HEMT MMICs production technology for G-band applications.
 
Thermal stability and strain relaxation temperature of strained Si/sub 0.91/Ge/sub 0.09/ layers has been investigated using double crystal x-ray diffraction (DCXRD). High quality gate oxynitride layers rapid thermally grown on strained Si/sub 0.91/Ge/sub 0.09/ using N/sub 2/O and the split N/sub 2/O cycle technique below the strained relaxed temperature is reported. A positive fixed oxide charge density was observed for N/sub 2/O and split-N/sub 2/O grown films. The O/sub 2/ grown films exhibit a negative fixed oxide charge. The excellent improvements in the leakage current, breakdown field and charge-to-breakdown value of the N/sub 2/O or split-N/sub 2/O grown films were achieved compared to pure O/sub 2/ grown films.
 
The electron velocity overshoot phenomenon in the inversion layer is experimentally investigated using a novel thin-film silicon-on-insulator (SOI) test structure with channel lengths down to 0.08 /spl mu/m. The uniformity of the carrier density and tangential field is realized by employing a lateral asymmetric channel (LAC) profile. The electron drift velocity observed in this work is 9.5/spl times/10/sup 6/ cm/s for a device with L/sub eff/=0.08 /spl mu/m at 300 K. The upward trend in electron velocity can be clearly noticed for decreasing channel lengths.
 
In this work, the thermal annealing at 720/spl deg/C for 2 hr (called boron uphill treatment) with an SiO/sub 2/-capped layer was applied after source/drain extensions (SDE) implantation to improve the short channel characteristics of a 0.1-/spl mu/m PMOSFET with an ultra-low temperature nitride spacer. The influence and the mechanism of the capped layer on this uphill treatment were investigated. The results show that the capped layer treatment indeed leads to a shallower junction, improved V/sub th/ roll-off characteristic, and added immunity against subsurface punchthrough.
 
The temporal response of a GaAs metal-semiconductor- metal (MSM) photodetector with a finger spacing of 0.1 µm has been analyzed. The intrinsic detector has been found to have a minor effect (25-percent increase) on the full width at half-maximum (FWHM) of the temporal response of the device and its parasitic circuit elements. The analysis indicates that a long time constant due to the decay of holes is solely responsible for this increase. The smallest FWHM for this detector is estimated to be less than 2.5 ps.
 
High-speed complementary metal-oxide semiconductor (CMOS)-inverter ring oscillators with the shortest gate length of 0.17 μm were fabricated by a conventional large-scale integrated (LSI) technology. The propagation delays were 21 ps / stage (2.0 V) at room temperature and 17 ps / stage (2.0 V) at 80 K. These results are the fastest records reported for bulk CMOS devices as of today. The results were obtained by reducing effective drain junction capacitances with “double-finger gates,” and devices will probably be faster if the areas are completely proportionally reduced to the feature size. Though it is important for CMOS devices to increase drain currents, a silicidation technique for source and drain was not necessary for the tested devices to reduce series resistance
 
A self-consistent Monte Carlo (MC) simulator is employed to investigate and compare hot electron phenomena in three competing design strategies for 0.1 /spl mu/m SOI n-MOSFETs operating under low voltage conditions, i.e., V/sub d/ considerably less than the Si-SiO/sub 2/ injection barrier height /spl phi//sub b/. Simulations of these designs reveal that non-local carrier transport effects and two-dimensional current how play a significant role in determining the relative rate and location of hot electron injection into both the front and back oxides. Specifically, simulations indicate that electron-electron interactions near the drain edge are a main source of electron energies exceeding /spl phi//sub b/. The hot electron injection distributions are then coupled with an empirical model to generate interface state distributions at both the front and back oxide interfaces. These interface states are incorporated into a drift-diffusion simulator to examine relative hot-electron-induced device degradation for the three 0.1 /spl mu/m SOI designs. Simulations suggest that both the Si layer thickness and doping distribution affect device sensitivity to hot-electron-induced interface states. In particular, the simulations show that a decrease in the channel doping results in increased sensitivity to back oxide charge. In the comparison of the heavily-doped designs, the design with a thinner T/sub Si/ experiences significantly more hot-electron-induced oxide damage in the back oxide and more degradation from the charged states at the back interface.
 
We report a new method of forming nickel silicide (NiSi) on n-Si with low contact resistance, which achieves a Schottky barrier height of as low as 0.074 eV. Antimony (Sb) and nickel were introduced simultaneously and annealed to form NiSi on n-Si (100). Sb dopant atoms were found to segregate at the NiSi/Si interface. The devices with Sb segregation show complete nickel monosilicide formation on n-Si (100) and a close-to-unity rectification ratio. The rectification ratio R<sub>c</sub> is defined to be the ratio of the forward current to the reverse current, where the forward and reverse currents are measured using forward and reverse bias voltages, respectively, having the same magnitude of 0.5 V. This process is also compatible and easily integrated in a CMOS fabrication process flow.
 
A superconducting field-effect transistors (FET) with a 0.1- mu m-length gate electrode was fabricated and tested at liquid-helium temperature. Two superconducting electrodes (source and drain) were formed on the same Si substrate surface with an oxide-insulated gate electrode by a self-aligned fabrication process. Superconducting current flowing through the semiconductor (Si) between the two superconducting electrodes (Nb) was controlled by a gate-bias voltage.< >
 
Fabrication of state-of-the-art W-band 0.1- mu m T-gate pseudomorphic (PM) InGaAs high electron mobility transistors (HEMTs) is reported. This device achieved a noise figure of 2.1 dB with an associated gain of 6.3 dB at 93.5 GHz. The device has a maximum gain of 9.6 dB at 94 GHz, which extrapolates to an F/sub max/ of 290 GHz. This noise figure is claimed to be the lowest ever reported for HEMTs fabricated on GaAs substrates at this frequency range.< >
 
This work investigates the floating body effect (FBE) on the partially depleted SOI devices at various temperatures for high-performance 0.1 /spl mu/m MOSFET. The thermal effect on the device's characteristics was investigated with respect to the body contacted MOSFET (BC-SOI) and floating body MOSFET without body contacted (FB-SOI). It is found that the threshold voltage (Vth) and the off state drain current (I/sub OFF/) of the BC-SOI devices are more temperature sensitive than those of the FB-SOI devices. For operation at higher temperatures, there is no apparent difference in driving capability between the BC-SOI and FB-SOI MOSFETs.
 
We proposed counter doping into a heavily and uniformly doped channel region of SOI MOSFETs. This enabled us to suppress the short channel effects with proper threshold voltage V/sub th/ and to eliminate parasitic edge or back gate transistors. We derived a model for V/sub th/ as a function of the projected range, Rp and dose, /spl Phi//sub D/, of the counter doping, and showed that V/sub th/ is invariable even when the as-implanted counter doping profile redistributes. Using this technology, we demonstrated a V/sub th/ roll-off free 0.075 /spl mu/m-L/sub Geff/ nMOSFET with low off-state current.
 
The conventional, 1-D definition of "effective channel length" (L/sub eff/) is examined in light of the spatial dependence of channel sheet resistance in 0.1-/spl mu/m MOSFETs calculated from a 2-D device model. For short-channel devices, the sheet resistance deviates significantly from the uniform, long-channel behavior that L/sub eff/ in general is different from the "metallurgical channel length", L/sub met/. While geometrical (charge-sharing) effects tend to make L/sub eff/ slightly shorter than L/sub met/, lateral source-drain doping gradients, especially when coupled with retrograde channel doping, can make L/sub eff/ substantially longer than L/sub met/. The latter might help explain the apparent "excess" short channel effect often observed in 0.1-/spl mu/m CMOS devices.< >
 
High-performance 0.1-μm In<sub>0.4</sub>AlAs/In<sub>0.35</sub>GaAs metamorphic high-electron mobility transistors (MHEMTs) on GaAs substrate have been successfully fabricated with Ar plasma treatment. Before the gate Schottky metallization, the devices were treated with Ar plasma, which might clean and improve the surface of exposed barrier layer. The devices fabricated with Ar plasma treatment exhibited the excellent characteristics such as 50% reduction of the reverse gate leakage currents, the improved Schottky ideality factor of 1.37, high extrinsic transconductance of 700 mS/mm, and high maximum drain current density of 780 mA/mm. And the cutoff frequency f<sub>T</sub> as high as 210 GHz was achieved. To our knowledge, this is the best reported cutoff frequency for a 0.1-μm MHEMT with an indium content of 35% in the channel.
 
The millimeter-wave performance is reported for Al/sub 0.48/In/sub 0.52/As-Ga/sub 0.47/In/sub 0.53/As high-electron-mobility transistors (HEMTs) with 0.2- mu m and 0.1- mu m-long gates on material grown by molecular-beam epitaxy on semi-insulating InP substrates. Devices of 50- mu m width exhibited extrinsic transconductances of 800 and 1080 mS/mm, respectively. External f/sub T/ (maximum frequency of oscillation) of 120 and 135 GHz, respectively, were measured. A maximum f/sub T/ of 170 GHz was obtained from a 0.1*200- mu m/sup 2/ device. A minimum noise figure of 0.8 dB and associated gain of 8.7 dB were obtained from a single-stage amplifier at frequencies near 63 GHz.< >
 
We show that by making full use of the features of electrochemical etching in InAlAs/InGaAs heterostructures, deep gate grooves with small side etching can be fabricated. The most important advantage of this technology is that the vertical etching in the small gate openings will be remarkably enhanced by a self-organized process. Therefore the electrochemical etching provides a what we call "self-compensation" of the short channel effects. The effectiveness of this technology is evidenced by the excellent performance combined with the alleviation of the threshold-voltage shift and suppression of transconductance degradation in MODFET's with gate lengths below 0.1 /spl mu/m.
 
Transport properties are investigated in self-aligned NMOS devices with gate lengths down to 0.07 mu m. Velocity overshoot was observed in the form of the highest transconductances measured to date in Si FETs, as well as in the trend of the transconductance with gate length. The measured transconductance reached 910 mu S/ mu m at liquid-nitrogen temperature and 590 mu S/ mu m at room temperature. Velocity overshoot, by making such transconductances possible, should extend the value of miniaturization to dimensions that are smaller than what was commonly assumed to be worthwhile to pursue.< >
 
The behaviors of the substrate current and the impact ionization rate are investigated for deep submicron devices in a wide temperature range. New important features are shown for the variations of the maximum substrate current as a function of applied biases and temperature. It is found that the gate voltage V/sub gmax/, corresponding to the maximum impact ionization current conditions, is quasi-constant as a Function of the drain bias for sub-0.1 /spl mu/m MOSFET's in the room temperature range. At low temperature, a substantial increase of V/sub gmax/ is observed when the drain voltage is reduced. It is also shown that, although a significant enhancement of hot carrier effects is observed by scaling down the devices, a strong reduction of the impact ionization rate is obtained for sub-0.1 /spl mu/m MOSFET's operated at liquid nitrogen temperature in the low drain voltage range.< >
 
Very-high-transconductance 0.1 mu m surface-channel pMOSFET devices are fabricated with p/sup +/-poly gate on 35 AA-thick gate oxide. A 600 AA-deep p/sup +/ source-drain extension is used with self-aligned TiSi/sub 2/ to achieve low series resistance. The saturation transconductances, 400 mS/mm at 300 K and 500 mS/mm at 77 K, are the highest reported to date for pMOSFET devices.< >
 
A new technique, using optical lithography, has been developed to produce very thick submicron gates. This technique has produced Al gates 900Å long and 1.7µm thick, for an aspect-ratio (gate thickness/gate length) of ∼ 19. Using this high aspect-ratio gate structure, GaAs MESFET's have been fabricated with gate lengths as short as 0.1µm and widths as wide as 300µm. Gate resistances of 17Ω/mm and 37Ω/mm of gate width have been measured for half-micron and quarter-micron long Al gates, respectively.
 
The authors have measured and analyzed the performance characteristics of 0.1- mu m gate InAs/In/sub 0.52/Al/sub 0.48/ MODFETs grown by molecular beam epitaxy. The transistors are characterized by measured g/sub m/(max)=840 mS/mm, f/sub T/=128 GHz, and a very high current carrying capability, e.g. I/sub dss/=934 mA/mm at V/sub gs/=0.4 V and V/sub ds/=2.7 V. The value of f/sub T/ is estimated from extrapolation of the current gain (H/sub 21/) at a -6 dB/octave rolloff. This is the first report on the microwave characteristics of an InAs-channel MODFET and establishes the superiority of this heterostructure system.< >
 
The first device performance results are presented from experiments designed to assess FET technology feasibility in the 0.1-µm gate-length regime. Low-temperature device design considerations for these dimensions lead to a 0.15-V threshold and 0.6-V power supply, with a forward-biased substrate. Self-aligned and almost fully scaled devices and simple circuits were fabricated by direct-write electron-beam lithography at all levels, with gate lengths down to 0.07 µm. Measured device characteristics yielded over 750-mS/mm transconductance, which is the highest value obtained to date in Si FET's.
 
AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistors (HEMT's) with a gate length of 0.1 μ m have been successfully fabricated. The HEMT's exhibit a maximum transconductance of 540 mS/mm with excellent pinch-off characteristics. A maximum stable gain (MSG) as high as 18.2 dB was measured at 18 GHz. At 60 GHz the device has demonstrated a minimum noise figure of 2.4 dB with an associated gain of ~6 dB. These are the best gain and noise results reported to date for HEMT's. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.
 
In this letter, we demonstrate a high-performance 0.1 /spl mu/m dynamic threshold voltage MOSFET (DTMOS) for ultra-low-voltage (i.e., <0.7 V) operations. Devices are realized by using super-steep-retrograde indium-channel profile. The steep indium-implanted-channel DTMOS can achieve a large body-effect-factor and a low V/sub th/ simultaneously, which results in an excellent performance for the indium-implanted DTMOS.
 
The realization of high-performance 0.1-mum gate AlGaN/GaN high-electron mobility transistors (HEMTs) grown on high-resistivity silicon substrates is reported. Our devices feature cutoff frequencies as high as f<sub>T</sub> = 75 GHz and f<sub>MAX</sub> = 125 GHz, the highest values reported so far for AlGaN/GaN HEMTs on silicon. The microwave noise performance is competitive with results achieved on other substrate types, such as sapphire and silicon carbide, with a noise figure F = 1.2-1.3 dB and an associated gain G<sub>ass</sub> = 8.0-9.5 dB at 20 GHz. This performance demonstrates that GaN-on-silicon technology is a viable alternative for low-cost millimeter-wave applications.
 
This letter describes the material characterization and device test of InAlAs/InGaAs high electron mobility transistors (HEMTs) grown on GaAs substrates with indium compositions and performance comparable to InP-based devices. This technology demonstrates the potential for lowered production cost of very high performance devices. The transistors were fabricated from material with room temperature channel electron mobilities and carrier concentrations of /spl mu/=10000 cm/sup 2//Vs, n=3.2/spl times/10/sup 12/ cm/sup -2/ (In=53%) and /spl mu/=11800 cm/sup 2//Vs, n=2.8/spl times/10/sup 12/ cm/sup -2/ (In=60%). A series of In=53%, 0.1/spl times/100 /spl mu/m/sup 2/ and 0.1/spl times/50 /spl mu/m/sup 2/ devices demonstrated extrinsic transconductance values greater than 1 S/mm with the best device reaching 1.074 S/mm. High-frequency testing of 0.1/spl times/50 /spl mu/m/sup 2/ discrete HEMT's up to 40 GHz and fitting of a small signal equivalent circuit yielded an intrinsic transconductance (g/sub m,i/) of 1.67 S/mm, with unity current gain frequency (f/sub T/) of 150 GHz and a maximum frequency of oscillation (f/sub max/) of 330 GHz. Transistors with In=60% exhibited an extrinsic g/sub m/ of 1.7 S/mm, which is the highest reported value for a GaAs based device.
 
This letter investigates hot-carrier-induced degradation on 0.1 /spl mu/m partially depleted silicon-on-insulator (SOI) nMOSFETs at various ambient temperatures. The thermal impact on device degradation was investigated with respect to body-contact nMOSFETs (BC-SOI) and floating-body SOI nMOSFETs (FB-SOI). Experimental results show that hot-carrier-induced degradation on drive capacity of FB-SOI devices exhibits inverse temperature dependence compared to that of BC-SOI devices. This is attributed to the floating-body effect (FBE) and parasitic bipolar transistor (PBT) effect.
 
The I SUB =I DS characteristics of the two ISRC nMOSFET's (ISRC) with the different effective channel length and the conventional nMOSFET (CNV) versus drain voltage with the variation of gate voltage. 
The simulation results of three structures using TSUPREM4, MEDICI. The drain voltage is 2.0 V and gate voltage is 1.0 V. (a) Conventional nMOSFET. (b) ISRC nMOSFET. (c) Recessed channel nMOSFET with uniform channel doping profile. 
To investigate the substrate current characteristics of a recessed channel structure with graded channel doping profile, we have fabricated and simulated the Inverted-Sidewall Recessed-Channel (ISRC) nMOSFET and compared it with a conventional planar nMOSFET. Experimentally, the ISRC nMOSFET shows about 30% reduction of substrate current, even though the drain current is almost the same. At 0.12-/spl mu/m channel length, the I/sub SUB//I/sub DS/ value of the conventional nMOSFET is measured to be 1.68 times higher than that of the ISRC nMOSFET. Also, using simulation, it is verified that the reduction of electric field at the drain junction of ISRC nMOSFET results from the graded channel doping profile, not from the recessed channel structure.
 
(a) Variations of effective gate length L (open symbols, left scale) and maximum capacitance (filled triangles, right scale) with gate length L m as obtained from C (V ) data. Also shown L data obtained with standard I (V ) based methods assuming a constant mobility versus L. (b) Variations of (Q = 0:4 C=cm ) with gate length as obtained from split C-V data for devices with and without pocket implants.
Variations of with the inversion charge Q as obtained from (top) C (V ) raw data ((4)) for various gate lengths and (bottom) from fully corrected C (V ) data and after further R correction (dashed lines) for Si p-MOSFETs. In insert C (V ) curves before and after correction of the inner
The feasibility of split capacitance-voltage (C-V) measurements in sub-0.1 μm Si MOSFETs is demonstrated. Based on the split C-V measurements, an improved methodology to extract accurately the effective channel length and the effective mobility is proposed. Unlike conventional I<sub>d</sub>(V<sub>g</sub>)-based extraction techniques, this new approach does not assume the invariance of the effective mobility with gate length (assumption proved to be false in this paper). This method is relevant to study transport limitations in ultimate MOSFETs as illustrated with the study of pocket implant influence on 50-nm p-MOSFETs.
 
To solve the problems of trade-off between the short channel effect and the performance enhancement of sub-quartermicrometer MOSFETs, we have developed a recessed channel MOSFET structure called ISRC (Inverted-Sidewall Recessed-Channel). The oxide thickness is 4 nm and the effective channel length is 0.1 /spl mu/m, which is the smallest Si-MOSFET ever reported in the recessed channel structures. The maximum saturation transconductance at V/sub D/=2 V is 446 mS/mm for the 0.1 /spl mu/m n-channel device. The threshold voltage roll-off is kept within 64 mV when the gate length varies from 1.4 /spl mu/m to 0.1 /spl mu/m and good subthreshold characteristics are achieved for 0.1 /spl mu/m channel device.
 
We report high switching performance of 0.1-μm metamorphic high-electron mobility transistors (HEMTs) for microwave/millimeter-wave monolithic integrated circuit (MMIC) resistive mixer applications. Very low source/drain resistances and gate capacitances, which are 56 and 31% lower than those of conventional pseudomorphic HEMTs, are due to the optimized epitaxial and device structure. Based on these high-performance metamorphic HEMTs, a 94-GHz MMIC resistive mixer was designed and fabricated, and a very low conversion loss of 8.2 dB at a local oscillator power of 7 dBm was obtained. This is the best performing W-band resistive field-effect transistor mixer in terms of conversion loss utilizing GaAs-based HEMTs reported to date.
 
A MODFET with two 30-nm-long gates (separated by 40 nm) has been fabricated using ultrahigh-resolution electron-beam lithography. The proximity of the two gate fingers along with the ability to independently bias them results in the following features: (a) tunability of the threshold voltage, (b) enhancement of the transconductance, especially at low current levels, (c) reduction in short-channel effects, and (d) high-voltage gain and cutoff frequency.< >
 
The drain-induced-barrier-lowering (DIBL) considerations of the extended drain structure were studied using two-dimensional (2-D) device simulations in the tenth-micrometer regime. We found that the drain extension length must be kept at a minimum in order to reduce the transistor cell area and to improve the device transconductance, G/sub m/. However, without decreasing the deep source/drain junction depth, the minimum value of which is basically limited by the ability to form a good low resistive silicide contact, charge sharing associated with a small extension length deteriorates the short channel behavior of the device, via DIBL, even if aggressive scaling of the gate oxide thickness and the junction depth of the drain extension were used. The solution to this dilemma would be elevating the source/drain area by selective epitaxy to form a shallow, low resistive silicided junction. We propose here a novel device structure using the elevated silicide-as-a-diffusion-source (E-SADS), which improves the DIBL-G/sub m/ tradeoff, eliminates the contact problem, and maintains a minimal cell areal increase.
 
0.1- mu m CMOS devices using low-impurity-channel transistors (LICTs) with dual-polysilicon gates have been fabricated by nondoped epitaxial growth technology, high-pressure oxidation of field oxide, and electron-beam lithography. These devices, with gate lengths of 0.135 mu m, achieved normal transistor operation at both 300 and 77 K using 1.5-V supply voltage. Maximum transconductances are 203 mS/mm for nMOS transistors and 124 mS/mm for pMOS transistors at 300 K. Low-impurity channels grown on highly doped wells provide low threshold voltages of about 0.35 V for nMOS transistors and about -0.15 V for pMOS transistors at 77 K, and preserve good turn-offs with subthreshold swings of 25 mV/decade at 77 K. LICTs suppress short-channel effects more effectively, compared with conventional devices with nearly uniform dopings.< >
 
We report the experimental results of the first MOSFET's ever fabricated using a laser plasma-source X-ray stepper. The minimum gate length of these transistors is 0.12 /spl mu/m with an effective channel length of 0.075 /spl mu/m. These transistors were patterned using a mix-and-match lithography scheme where the gate level was printed using a 1.4 nm plasma-source X-ray stepper while the other layers were patterned using optical lithography.< >
 
This letter proposes a new device structure which is called the "partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET." The PGP SOI MOSFET minimizes the short-channel effect (SCE) compared to the conventional single-gate (SG) SOI MOSFET because the gate-induced field in the SOI layer is held high by the PGP region. This results in a lower stand-by leakage current. The PGP SOI MOSFET also shows much better switching performance and extremely high analog performance because of its smaller parasitic capacitance compared to the conventional ground-plane (GP) device. Thus, it is shown that the PGP SOI MOSFET is a promising candidate for future deep-sub-0.1-/spl mu/m mixed-mode LSIs.
 
Very high performance sub-0.1 /spl mu/m channel nMOSFET's are fabricated with 35 /spl Aring/ gate oxide and shallow source-drain extensions. An 8.8-ps/stage delay at V/sub dd/=1.5 V is recorded from a 0.08 /spl mu/m channel nMOS ring oscillator at 85 K. The room temperature delay is 11.3 ps/stage. These are the fastest switching speeds reported to date for any silicon devices at these temperatures. Cutoff frequencies (f/sub T/) of a 0.08 /spl mu/m channel device are 93 GHz at 300 K, and 119 GHz at 85 K, respectively. Record saturation transconductances, 740 mS/mm at 300 K and 1040 mS/mm at 85 K, are obtained from a 0.05 /spl mu/m channel device. Good subthreshold characteristics are achieved for 0.09 /spl mu/m channel devices with a source-drain halo process.< >
 
The Schottky-collector resonant tunneling diode (RTD) is an RTD with the normal N+ collector and ohmic contact replaced by a Schottky contact, thereby eliminating the associated parasitic resistance. With submicron Schottky contact dimensions, the remaining components of the parasitic series resistance can be greatly reduced, resulting in an increased maximum frequency of oscillation, f/sub max/. AlAs/GaAs Schottky-collector RTDs were fabricated using 0.1 /spl mu/m T-gate technology developed for high electron mobility transistors. From their measured dc and microwave parameters, and including the effect of the quantum well lifetime, f/sub max/=900 GHz is computed.< >
 
MOSFETs in the sub-0.1- mu m regime were investigated using a nonplanar device simulator CADDETH-NP. It was found that even in this regime, the short-channel effect can be suppressed in grooved gate MOSFETs because of the concave corner of the gate insulator. MOSFETs with a gate length of 0.05 mu m or less with no threshold voltage lowering can be made by optimizing the concave corner radius, junction depths, and channel doping.< >
 
Scanning electron microscopy micrograph. (a) Conventional e-beam resist and its 0.25-m T-gate. (b) The resist after shrinking by thermally reflow and its 0.1-m T-gate.  
Transconductance of the 0:1 m 2 160 m MHEMT.
Typical current gain H , MAG/MSG, and unilateral gain U as a function of frequency of the 0:1 2 160 m MHEMT.  
A 0.1-μm T-gate fabricated using e-beam lithography and thermally reflow process was developed and applied to the manufacture of the low-noise metamorphic high electron-mobility transistors (MHEMTs). The T-gate developed using the thermally reflowed e-beam resist technique had a gate length of 0.1 μm and compatible with the MHEMT fabrication process. The MHEMT manufactured demonstrates a cutoff frequency f<sub>T</sub> of 154 GHz and a maximum frequency f<sub>max</sub> of 300 GHz. The noise figure for the 160 μm gate-width device is less than 1 dB and the associated gain is up to 14 dB at 18 GHz. This is the first report of a 0.1 μm MHEMT device manufactured using the reflowed e-beam resist process for T-gate formation.
 
The correlation between gate and substrate currents in NMOSFET's with effective channel length, L/sub eff/, down to 0.1 /spl mu/m is investigated within the general framework of the lucky-electron model. It Is found that the correlation coefficient, /spl Phi/b//spl Phi//sub i/, decreases with decreasing L/sub eff/ in the 0.1 /spl mu/m regime, where /spl Phi//sub b/ is the effective Si-SiO/sub 2/ barrier height for channel hot-electrons, and /spl Phi//sub i/ is the effective threshold potential for impact ionization. Furthermore, this effect becomes stronger in NMOSFET's with shorter L/sub eff/. These experimental results suggest the need for further investigation on specific assumptions in the lucky-electron model to understand hot-electron behavior and impact ionization-mechanisms in 0.1 /spl mu/m-scale NMOSFET's.< >
 
We report on the DC and RF performance of HEMTs based on the Al-free material system InP/InGaAs/InP. These structures were grown by LP-MOCVD using a nitrogen carrier. The influence of gate length and channel composition on the performance of these devices is investigated. We demonstrate that optimum DC and RF performance using highly strained channels can be obtained only if additional composite channels are grown. The cutoff frequencies f/sub T/=160 GHz and f/sub max/=260 GHz for a 0.1-/spl mu/m T-gate device indicate the suitability of our devices for W-band applications.
 
The authors have fabricated 0.10- mu m gate-length CMOS devices that operate with high speed at room temperature. Electron-beam lithography was used to define 0.10- mu m polysilicon gate patterns. Surface-channel type p- and n-channel MOSFETs were fabricated using an LDD structure combined with a self-aligned TiSi/sub 2/ process. Channel doping was optimized so as to suppress punchthrough as well as to realize high transconductance and low drain junction capacitance. The fabricated 0.10- mu m CMOS devices have exhibited high transconductance as well as a well-suppressed band-to-band tunneling current, although the short-channel effect occurred somewhat. The operation of a 0.10- mu m gate-length CMOS ring oscillator has been demonstrated. The operation speed was 27.7 ps/gate for 2.5 V at room temperature, which is the fastest CMOS switching ever reported.< >
 
Top-cited authors
Chenming hu
  • University of California, Berkeley
U.K. Mishra
  • University of California, Santa Barbara
K.J. Chen
  • The Hong Kong University of Science and Technology
Tsu-Jae King Liu
  • University of California, Berkeley
David B Tuckerman
  • Tuckerman & Associates, Inc.