Electronics

Published by MDPI

Online ISSN: 2079-9292

Articles


FIG. 1: (Color online) Scaled electron energy spectrum ε(k)/(˜ vF kSAW ) in the absence of electron traps as a function of the normalized SAW amplitude A/(˜ vF kSAW ) for semiconducting nanoribbons subjected to an acoustically induced SAW potential. In this figure, we choose ∆/(˜ vF kSAW ) = 1.0 (upper panel) and 1.5 (lower panel). Only the eigen-spectra arising from the two lowest dispersion curves in the absence of a SAW are displayed. Higher subbands contribute significantly at larger SAW amplitude. The lighter shaded regions arise from the lowest energy dispersion curves, whereas the darker shaded regions are associated with the energy dispersions of the next subband.
FIG. 3: (Color online) Minigap spectrum ε(k)/(˜ vF kc), induced by a corrugation potential, as a function of the normalized modulation amplitude Ckc. In this figure, the two plots correspond to the two lowest values of the quantized transverse wave number k (m) y  
Effects of Localized Trap-States and Corrugation on Charge Transport in Graphene Nanoribbons
  • Article
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December 2012

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74 Reads

Oleksiy Roslyak

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We investigate the role played by electron traps on adiabatic charge transport for graphene nanoribbons in the presence of an acoustically induced longitudinal surface acoustic wave (SAW) potential. Due to the weak longitudinal SAW-induced potential as well as the strong transverse confinement by a nanoribbon, minibandsof sliding tunnel-coupled quantum dots are formed so that by varying the chemical potential to pass through the minigaps, quantized adiabatic charge transport may be obtained. We analyze the way that the minigaps may be closed, thereby destroying the likelihood of current quantization in a nanoribbon. We present numerical calculations showing the effects due to electron traps which lead to localized-trap energy levels within the minigaps. Additionally, for comparison, we present results for the minibands of a corrugated nanoribbon in the absence of a SAW.
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Figure 2. Transistor-level schematic of the proposed VCO-based CTDSM.
Figure 7. Measured SNDR/SNR/THD with different DC offsets and 10 mVpp sine wave (single channel).
High-level modulator design parameters.
A 0.00426 mm2 77.6-dB Dynamic Range VCO-Based CTDSM for Multi-Channel Neural Recording

October 2022

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76 Reads

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Driven by needs in neuroscientific research, future neural interface technologies demand integrated circuits that can record a large number of channels of neural signals in parallel while maintaining a miniaturized physical form factor. Using conventional methods, it is challenging to reduce circuit area while maintaining the high dynamic range, low noise, and low power consumption required in the neural application. This paper proposes to address this challenge using a VCO-based continuous-time delta-sigma modulator (CTDSM) circuit, which can record and digitize neural signals directly without the need for front-end instrumentation amplifiers and anti-aliasing filters, which are limited by the abovementioned circuit-area performance tradeoff. Thanks to the multi-level quantization and intrinsic mismatch-shaping capabilities of the VCO-based approach, the proposed first-order CTDSM can achieve comparable electrical performance to a higher-order CTDSM while offering further area and power reductions. We prototyped the circuit in a 22-channel test chip and demonstrate, based on the chip measurement results, that the proposed modulator occupies an area of 0.00426 mm2 while achieving input-referred noise levels of 6.26 and 3.54 µVrms in the action potential (AP) and local field potential (LFP) bands, respectively. With a 77.6 dB wide-dynamic range, the noise and total harmonic distortion meet the requirements of a neural interface with up to 149 mVpp input AC amplitude or up to ±68 mV DC offsets. We also validated the feasibility of the circuit for multi-channel recording applications by examining the impact of cross-channel VCO oscillation interferences on the circuit noise performance. The experimental results demonstrate the proposed architecture is an excellent candidate to implement future multi-channel neural-recording interfaces.

Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors

October 2018

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1,346 Reads

In this paper, we extensively analyzed the drain-induced barrier lowering (DIBL) and leakage current characteristics of the proposed partial isolation field-effect transistor (PiFET) structure. We then compared the PiFET with the conventional planar metal-oxide semiconductor field-effect transistor (MOSFET) and silicon on insulator (SOI) structures, even though they have the same doping profile. Two major features of the PiFET are potential condensation and potential modulation by a buried insulator. The potential modulation near the drain region can control the electric field in the overlapped region of the drain and gate, because it causes a high gate-fringing field. Therefore, we suggest guidelines with respect to the optimal PiFET structure.


Figure 1. Traditional BGR structure.
Performance under different process concerns of the proposed BGR circuit.
Performance comparison.
A 3.95 ppm/°C 7.5 μW Second-Order Curvature Compensated Bandgap Reference in 0.11 μm CMOS

September 2022

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45 Reads

In order to meet the requirements of modern portable electronics for high accuracy and low power consumption of bandgap reference circuits, a new low-voltage bandgap reference with a second-order compensated circuit at 1.8 V is proposed. It features a new self-biased fully symmetric differential operational amplifier circuit with the help of split transistors for achieving low power consumption and high accuracy; by adding a new sub-threshold compensated circuit. The results of simulation show that the temperature coefficient of the second-order circuit is 3.95 ppm/°C in the temperature range of −40 to 125 °C, and the power consumption is only 7.5 μW; this meets both the requirements of high precision and low power consumption. At the same time, the output noise voltage of the design is less than 30 μV/sqrt (Hz) at a frequency of 100 Hz, and the low-frequency supply voltage rejection ratio is −103 dB@100 Hz; these are acceptable for bandgap reference circuits.

Performance summary and comparison with other published works.
Design of a Ka-Band U-Shaped Bandpass Filter with 20-GHz Bandwidth in 0.13-μm BiCMOS Technology

October 2020

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79 Reads

In this work, the design of a novel Ka-band miniaturized bandpass filter with broad bandwidth is demonstrated by using inversely coupled U-shaped transmission lines. In the proposed filter, two transmission zeros can be generated within a cascaded U-shaped structure and it can also be proven that, by inversely coupling two stacked U-shaped transmission lines, the notch frequency at the upper stopband can be shifted to a lower frequency, which results in a smaller chip size. The key parameters affecting the performance of the proposed filter are investigated in detail with the effective lumped-element circuit illustrated. Fabricated in a 0.13-μm SiGe BiCMOS process, the proposed filter achieves an insertion loss of 3.6 dB at a frequency of 28.75 GHz and the measured bandwidth is from 20.75 GHz to 41 GHz. The return loss is better than −10 dB from 20.5 GHz to 39 GHz. The lower transmission zero is located at 11.75 GHz with a suppression of 54 dB while the upper transmission zero is around 67 GHz with an attenuation of 34.6 dB. The measurement agrees very well with the simulation results and the overall chip size of the proposed filter is 176 × 269 μm2.

Figure 1. Back-end-of-the-line (BEOL) cross section of the 130-nm SiGe BiCMOS technology.
Figure 2. The connection between the active device and the passive device.
Figure 3. Device model of the HBTs (Heterojunction Bipolar Transistors).
Figure 6. (a) Block diagram of the input buffer circuit. (b) Block diagram of the frequency multiplication circuit.
A 130-to-220-GHz Frequency Quadrupler with 80 dB Dynamic Range for 6G Communication in 0.13-μm SiGe Process

March 2022

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57 Reads

This paper presents a broadband frequency quadrupler (FQ) implemented with a standard 130-nm SiGe BiCMOS process. Two broadband push-push frequency doublers (×2) operate at an input frequency of 32.5–55 GHz and 65–110 GHz, respectively. To properly drive the two doublers with enough input power and bandwidth, two transformer coupled power amplifiers (PAs) have been adopted. The former power amplifier is based on a neutralized capacitor structure and the latter is based on a transformer topology. A nonlinear device model and a systematic methodology to generate maximum power at second harmonic are proposed. By manipulating the device nonlinearity and optimizing the magnetically and capacitively coupled resonator (MCCR) matching networks, optimum conditions for harmonic power generation are provided. The measurement results show that the proposed quadrupler provides a 90-GHz bandwidth with an 80-dB dynamic range and a high energy efficiency η of 3.7% at 210 GHz.

An Area-Efficient and Programmable 4 × 25-to-28.9 Gb/s Optical Receiver with DCOC in 0.13 µm SiGe BiCMOS

June 2020

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650 Reads

In this paper, we present an area-efficient noise-optimized programmable 4 × 25-to-28.9 Gb/s optical receiver. Both high- and low-power modes are available for the receiver to meet different requirements. Emitter degeneration provides the input transimpedance amplifier (TIA) stage with improved stability. The noise of the TIA with emitter degeneration is analyzed, and an improved noise optimization method for the TIA is proposed. A sink current source with emitter degeneration in a DC offset cancellation (DCOC) loop reduces the noise introduced by the DCOC circuit. Moreover, with parasitic capacitor utilization in the DCOC loop and capacitive emitter degeneration in the variable-gain amplifier (VGA) stage, the chip area is minimized. Fabricated in a 0.13 µm SiGe BiCMOS technology, the receiver achieved a small area of 0.54 mm2 per lane. The measured bit error rate (BER) is 10−12 with input signal varying from 110 μApp to 1150 μApp. The one-lane power dissipation values in the low-power and high-power modes are 84.97 mW and 123.75 mW, respectively.

Figure 2. Block diagram of PLL.
Figure 3. Schematic of VCO.
Figure 7. Schematic of phase-adjusting circuit.
Summary and comparison with different articles.
A 500 kHz to 150 MHz Multi-Output Clock Generator Using Analog PLL and Open-Loop Fractional Divider with 0.13 μm CMOS

July 2022

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59 Reads

Clocks are widely used in multimedia and electronic devices, and they usually have different frequency demands. This paper presents the design of a multi-output clock generator using an analog integer-N phase-locked loop (PLL) and open-loop fractional dividers. The PLL based on a three-stage ring voltage-controlled oscillator (VCO) is used to transform the lower frequency reference into a high-frequency intermediate clock (600 MHz–900 MHz). Then, relying on the open-loop fractional divider, a wide frequency range of 500 kHz to 150 MHz can be generated. Due to the open-loop control characteristic, the clock generator has instantaneous frequency switching capability. In addition, phase-adjusting circuits added to the divider greatly improved the jitter performance of the output clock; its RMS jitter is 5.2 ps. This work was conducted with 0.13 μm CMOS technology. The open-loop divider occupies an area of 0.032 mm2 and consumes 7.7 mW from a 1.2 V supply.

Figure 1. Traveling-wave amplifier (TWA): (a) concept and (b) small-signal model.
Figure 4. Traveling-wave amplifier chip simulation and measurement results: (a) TWA1 with off-chip termination gate SP simulation and measurement results, (b) TWA1 with off-chip gate termination HB simulation results.
Figure 5. Traveling-wave amplifier chip simulation and measurement results: (a) TWA2 with on-chip gate termination SP simulation and measurement results, (b) TWA2 with on-chip gate termination HB simulation results.
Reported TWA parameter summary.
Designed TWA output power and efficiency measurement summary.
0.13 μm CMOS Traveling-Wave Power Amplifier with On- and Off-Chip Gate-Line Termination

January 2020

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616 Reads

Broadband amplifiers are essential building blocks used in high data rate wireless, radar, and instrumentation systems, as well as in optical communication systems. Only a traveling-wave amplifier (TWA) provides sufficient bandwidth for broadband applications without reducing modern linearization techniques. TWA requires gate-line and drain-line termination, which can be implemented on- and off-chip. This article compares the performance of identical 0.13 μm CMOS TWAs, differing only in gate-line termination placement. Measurement results revealed that the designed TWAs with on- and off-chip termination have a bandwidth of 10 GHz with a maximum gain of 15 dB and a power-added efficiency (PAE) of 5%–22% in the whole operating frequency range. Placing the gate-line termination off-chip results in an S21 flatness reduction, compared to the gain of a TWA with on-chip termination. Gain fluctuation over frequency is reduced by 4–8 dB when the termination resistor is placed as an external circuit.

Figure 11. Simulation results of 3
Performance comparison with published front end.
A Linearity Improvement Front End with Subharmonic Current Commutating Passive Mixer for 2.4 GHz Direct Conversion Receiver in 0.13 μm CMOS Technology

August 2020

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99 Reads

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

Figure 2. Circuit implementation of the proposed PAM-4 driver.
A 0.17 pJ/bit 28 Gb/s/pin Single-Ended PAM-4 Transmitter for On-Chip Short-Reach Unterminated Channels

August 2022

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36 Reads

This paper presents the design of a single-ended four-level pulse-amplitude modulation (PAM-4) transmitter for an on-chip short-reach unterminated channel. To achieve multi-output generation, a local voltage buffer consisting of a diode-connected device and a leaker transistor is introduced. By charge-sharing between a local reservoir capacitor and an unterminated channel, the proposed transmitter generates mid-level output voltages without using the DC current, thereby realizing multi-level signaling without significantly increasing the static current. A prototype chip was fabricated by 28 nm CMOS process, and the transmitter exhibits an energy efficiency of 0.17 pJ/bit at 28 Gb/s/pin, which is state-of-the-art energy efficiency as a multi-level transmitter having a data rate beyond 20 Gb/s.

A 0.18-ns Response Time Digital LDO Regulator with Adaptive PI Controller in 180-nm CMOS

July 2021

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207 Reads

Digital low drop-out regulator (D-LDO) with fast settling time and superior transient response is gaining increasing attention to make up for the deficiency of analog LDO. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. In this paper, a multi-bit conversion technique is proposed to improve the transient response speed. The multi-bit conversion technique is achieved by an error detector with adaptive regulation of proportion and integration parameters in the digital controller before pass devices. Besides, a voltage sensor and a time-to-digital converter are employed to convert the output voltage to digital codes. Implemented in a 180-nm CMOS process, the proposed D-LDO features under 36/33 mV of undershoot/overshoot at VOUT = 0.95 V as the load current steps up with 40 mA/1 ns on a 0.5 nF load capacitor. The simulated response time is 0.18-ns, the figure-of-merit of speed FOM1 is 0.65 ps and FOM2 achieves 0.068 pF.

A 5 V-to-32 V Input PVT-Robust Charge-Pump Circuit with Adjustable Output in a 0.18 μm BCD Process

September 2022

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102 Reads

In this paper, a new closed-loop charge-pump circuit with adjustable output voltage and an on-chip compensation technique is proposed. The environmental temperature and process corner can be detected with an on-chip detection circuit and automatically feedback an adjusted reference voltage. With this, the magnitude of the charge-pump output voltage with Pulse-Width Modulation (PWM) can be compensated. The charge-pump circuit is designed and verified with a 180 nm Bipolar-CMOS-DMOS (BCD) process, and its output voltage at different process, voltage, and temperature (PVT) is controllable with low ripple. There are three selections for adjusting the output voltage: +5 V/+7 V/+10 V shifts, with the supply voltage ranging from 5 V to 32 V. It can remain tunable and stable at any shifts. The maximum deviation is ±0.265%, and the maximum load current can reach 30 mA. The ripple voltage is less than 0.3% (Δ Vripple/Vout) underthe maximum load. The Monte Carlo simulation results show that the worst case of the process sensitivity (σ/μ) is 0.1%. The charge-pump core area is 0.308 mm2, and the power consumption is 4.753 mW. The circuit can produce high-precision output and is suitable for high-side driving IC applications.

Figure 1. Scheme of a GPON network with an indication of how the distribution of contents from the OLT to the different ONTs using the carriers at 1310 nm and 1490 nm is carried out.
Figure 2. Scheme of the structure of a GPON to implement triple-play services using the third lambda at 1550 nm.
Figure 4. Block diagram of the reconfigurable RF converter RFID-II, formed by two variable frequency synthesizers, two passive mixers, and auxiliary circuitry.
Figure 6. Circuit diagram of the mixers.
Performance summary of the fabricated prototypes (RFID-II).
A reconfigurable radio-frequency converter IC in 0.18 µm CMOS

October 2019

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1,300 Reads

This work presents a reconfigurable RF converter for DVB-T television applications using triple-play over GPON. The system takes the DVB-T input, a wavelength division multiplexing (WDM) signal with spectral inversion in the range from 47 M Hz –1000 M Hz , up-converts its frequency to the band-pass of a highly selective surface-acoustic wave (SAW) filter centered at 1 . 3 G Hz , and then down-converts it so that it is compatible with the antenna input of conventional television sets. The designed RF converter incorporates two pairs of frequency synthesizer and mixer, based, respectively, on an integer-N phase-locked loop (PLL) with two LC-tank VCOs with 128 coarse tuning bands in the range from 1.35 G Hz –2.7 G Hz , and a double-balanced Gilbert cell, modified for better impedance matching and improved linearity. It is fed with regulated supplies compensated in temperature and programmed by an I 2 C interface operating on five 16-bit registers. This work presents the experimental characterization of the whole system plus selected cells for stand-alone testing, which have been fabricated in a 0 . 18 m CMOS process.

Implementation results.
Comparison with other chaotic stream ciphers.
A 1 Gbps Chaos-Based Stream Cipher Implemented in 0.18 μm CMOS Technology

June 2019

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108 Reads

In this work, a novel chaos-based stream cipher based on a skew tent map is proposed and implemented in a 0.18 μm CMOS (Complementary Metal-Oxide-Semiconductor) technology. The proposed ciphering algorithm uses a linear feedback shift register that perturbs the orbits generated by the skew tent map after each iteration. This way, the randomness of the generated sequences is considerably improved. The implemented stream cipher was capable of achieving encryption speeds of 1 Gbps by using an approximate area of ~ 20 , 000 2-NAND equivalent gates, with a power consumption of 24.1 mW. To test the security of the proposed cipher, the generated keystreams were subjected to National Institute of Standards and Technology (NIST) randomness tests, proving that they were undistinguishable from truly random sequences. Finally, other security aspects such as the key sensitivity, key space size, and security against reconstruction attacks were studied, proving that the stream cipher is secure.

Floating Active Inductor Based Trans-Impedance Amplifier in 0.18 μm CMOS Technology for Optical Applications

December 2019

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192 Reads

In this paper, a transimpedance amplifier (TIA) based on floating active inductors (FAI) is presented. Compared with conventional TIAs, the proposed TIA has the advantages of a wider bandwidth, lower power dissipation, and smaller chip area. The schematics and characteristics of the FAI circuit are explained. Moreover, the proposed TIA employs the combination of capacitive degeneration, the broadband matching network, and the regulated cascode input stage to enhance the bandwidth and gain. This turns the TIA design into a fifth-order low pass filter with Butterworth response. The TIA is implemented using 0.18 μ m Rohm CMOS technology and consumes only 10.7 mW with a supply voltage of 1.8 V. When used with a 150 fF photodiode capacitance, it exhibits the following characteristics: gain of 41 dB Ω and −3 dB frequency of 10 GHz. This TIA occupies an area of 180 μ m × 118 μ m.

Figure 9. (a) Chip microphotograph; (b) power breakdown.
Figure 10. Measurement setup.
Performance summary and comparison.
A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

December 2019

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94 Reads

This paper presents a 20 GS/s four-channel time-interleaved sample-and-hold amplifier (SHA), which aims to improve the harmonic distortion performance, eliminate the common-mode voltage fall in track-to-hold transition, and solve the difficulty of timing mismatch calibration among different sampling channels. In data path, the harmonic distortion of the track-hold switch is optimized by introducing a distortion-improving resistor into the switched emitter follower. The common-mode voltage fall is eliminated by an inserted delay-regulating resistor. Additionally, broadband data buffers are utilized to further guarantee a wide bandwidth. In clock path, an interpolator-based phase regulator in analog domain is implemented to calibrate the timing mismatch, hence avoiding the large area cost and complicated algorithm in the digital domain. Fabricated in a 0.18 μm SiGe BiCMOS process, the experimental results show that the SHA achieves a bandwidth of 16 GHz and a total harmonic distortion of −39.6 to approximately −51.8 dB with a −3 dBm input. By applying the proposed sampling phase regulator, the timing mismatch can be optimized to satisfy the requirement of 6-bit resolution at a 4 × 5 GS/s sampling rate. The proposed SHA shows prominent performance on both bandwidth and linearity, which makes it suitable for ultra-high-speed communication networks.

Design of Differential Variable-Gain Transimpedance Amplifier in 0.18 µm SiGe BiCMOS

June 2020

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748 Reads

This paper presents two new inductorless differential variable-gain transimpedance amplifiers (DVGTIA) with voltage bias controlled variable gain designed in TowerJazz’s 0.18 µm SiGe BiCMOS technology (using CMOS transistors only). Both consist of a modified differential cross-coupled regulated cascode preamplifier stage and a cascaded amplifier stage with bias-controlled gain-variation and third-order interleaving feedback. The designs have wide measured transimpedance gain ranges of 24.5–60.6 dBΩ and 27.8–62.8 dBΩ with bandwidth above 6.42 GHz and 5.22 GHz for DVGTIA designs 1 and 2 respectively. The core power consumptions are 30.7 mW and 27.5 mW from a 1.8 V supply and the input referred noise currents are 10.3 pA/√Hz and 21.7 pA/√Hz. The DVGTIA designs 1 and 2 have a dynamic range of 40.4 µA to 3 mA and 76.8 µA to 2.7 mA making both suitable for real photodetectors with an on-chip photodetector capacitive load of 250 fF. Both designs are compact with a core area of 100 µm × 85 µm.

Figure 3. B1 field contour and three-dimensional plots of an eight-leg low-pass birdcage coil for mode 1. Reprinted from [34].
Figure 10. Examples of image quality at 0.55 T and 1.5 T breath-held, cine-steady, state-free precession: (a) short axis and (b) long axis slices from a patient with a nonischemic cardiomyopathy. Reprinted from [48].
Radiofrequency Coils for Low-Field (0.18–0.55 T) Magnetic Resonance Scanners: Experience from a Research Lab–Manufacturing Companies Cooperation

December 2022

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77 Reads

Low-field magnetic resonance imaging (MRI) has become increasingly popular due to cost reduction, artifact minimization, use for interventional radiology, and a better safety profile. The different applications of low-field systems are particularly wide (muscle–skeletal, cardiac, neuro, small animals, food science, as a hybrid scanner for hyperthermia, in interventional radiology and in radiotherapy). The low-field scanners produce lower signal-to-noise ratio (SNR) images with respect to medium- and high-field scanners. Thus, particular attention must be paid in the minimization of the radiofrequency (RF) coil losses compared to the sample noise. Following a short description of the coil design and simulation methods (magnetostatic and full-wave), in this paper we will describe how the choice of electrical parameters (such as conductor geometry and capacitor quality) affects the coil’s overall performance in terms of the quality factor Q, ratio between unloaded and loaded Q, and coil sensitivity. Subsequently, we will summarize the work carried out at our electromagnetic laboratory in collaboration with MR-manufacturing companies in the field of RF coil design, building, and testing for 0.18–0.55 T magnetic resonance (MR) clinical scanners by classifying them between surface-, volume-, and phased-array coils.

A Sub-6G SP32T Single-Chip Switch with Nanosecond Switching Speed for 5G Applications in 0.25 μm GaAs Technology

June 2021

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199 Reads

This paper presents a single-pole 32-throw (SP32T) switch with an operating frequency of up to 6 GHz for 5G communication applications. Compared to the traditional SP32T module implemented by the waveguide package with large volume and power, the proposed switch can significantly simplify the system with a smaller size and light weight. The proposed SP32T scheme utilizing tree structure can dramatically reduce the dc power and enhance isolation between different output ports, which makes it suitable for low-power 5G communication. A design methodology of a novel transmission (ABCD) matrix is proposed to optimize the switch, which can achieve low insertion loss and high isolation simultaneously. The average insertion loss and the isolations are 1.5 and 35 dB at 6 GHz operating frequency, respectively. The switch exhibits the measured input return loss which is better than 10 dB at 6 GHz. The 1 dB input compression point of SP32T is 15 dBm. The prototype is designed in 5 V 0.25 μm GaAs technology and occupies a small area of 12 mm2.

Figure 3. Cont.
Figure 3. Temperature dependences of the relative permittivity ε/ε 0 and loss tangent tgσ for APs Bi 3−x Nd x Ti 1.5 W 0.5 O 9 (x = 0.25, 0.5, 0.75, 1.0) at a frequency from 100 kHz to 1 MHz: Bi 2.75 Nd 0.25 Ti 1.5 W 0.5 O 9 , Bi 2.5 Nd 0.5 Ti 1.5 W 0.5 O 9 , Bi 2.25 Nd 0.75 Ti 1.5 W 0.5 O 9 , Bi 2 NdTi 1.5 W 0.5 O 9 . For Bi 3−x Nd x Ti 1.5 W 0.5 O 9 (x = 0.25, 0.5, 0.75), the ε(T) dependences are clearly pronounced. The intensity ε(T) in the range of 0.25-0.75 drops almost two times, while the dielectric loss decreases almost ten times. The temperature dependence of the relative permittivity ε/ε 0 for the AP Bi 3−x Nd x Ti 1.5 W 0.5 O 9 (x = 1.0) at a frequency from 100 kHz to 1 MHz has a strongly diffuse transition, which is usually typical of ferroelectric relaxors. The obtained values of the activation energy E a of charge carriers in Bi 3−x Nd x Ti 1.5 W 0.5 O 9 (x = 0.25, 0.5, 0.75) at frequency of 100 kHz are presented in Table 2. The activation energy E a was determined from the Arrhenius equation:
The Structural and Dielectric Properties of Bi3−xNdxTi1.5W0.5O9 (x = 0.25, 0.5, 0.75, 1.0)

January 2022

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61 Reads

A new series of layered perovskite-like oxides Bi3−xNdxTi1.5W0.5O9 (x = 0.25, 0.5, 0.75, 1.0) was synthesized by the method of high-temperature solid-state reaction, in which partial substitution of bismuth (Bi) atoms in the dodecahedra of the perovskite layer (A-positions) by Nd atoms takes place. X-ray structural studies have shown that all compounds are single-phase and have the structure of Aurivillius phases (APs), with close parameters of orthorhombic unit cells corresponding to space group A21am. The dependences of the relative permittivity ε/ε0 and the tangent of loss tgσ at different frequencies on temperature were measured. The piezoelectric constant d33 was measured for Bi3−xNdxTi1.5W0.5O9 (x = 0.25, 0.5, 0.75) compounds of the synthesized series.

A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL

August 2022

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50 Reads

A delay locked loop (DLL) based on a Phase Detector, which Measures the Delay of the Voltage-controlled delay line (PD-MDV), which is tVCDL, with efficient and stable locking performance was proposed. In contrast to conventional phase detectors, the PD-MDV measures tVCDL more accurately; thus, it can always generate the correct up/down (UP/DN) pulses. The proposed technique prevents becoming stuck in the fastest operation, in which UP pulses continue to appear even when tVCDL < tREF, where tREF is the reference time, which is an input of the DLL. In the reverse case, the PD-MDV prohibits DN pulses from continuing to appear under the condition tVCDL > tREF, thereby freeing the DLL from harmonic locking and becoming stuck in the slowest operation. The proposed phase detection scheme was verified under various conditions, including process corners, temperature variations, and abrupt changes in tREF. The proposed 1.2 V, 20~200 MHz DLL with the PD-MDV was designed using the 65 nm process, with a power consumption of 0.4 mW at 200 MHz.

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

March 2021

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423 Reads

This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μμm CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μμW, which makes it highly suitable for a multi-channel neural signal recording system.

0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

June 2021

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189 Reads

Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at ultra-low voltage thanks to forward body bias are presented, analyzed, and compared. The first considered architecture exploits nType and pType divide-by-two building blocks (DIV2s) without level shifters, whereas the second one is based on the cascade of nType DIV2s with input level shifter. Both the architectures have been previously proposed by the same authors with higher supply voltages, but are able to work at a supply voltage as low as 0.5 V due to the threshold lowering allowed by forward body bias. For each architecture, analytical design strategies to optimize the divider under different operation scenarios are considered and a comparison among all the treated case studies is presented. Simulation results considering a commercial 28 nm FDSOI CMOS process are reported to confirm the advantages and features of the different architectures and design strategies. The analysis show that the use of the forward body bias allows to design frequency dividers which have the best efficiency. Moreover, we have found that the frequency divider architecture based on nType and pType DIV2s without level shifter provides always better performance both in terms of speed and power consumption approaching about 17 GHz of maximum operating frequency with less than 30 μW power consumption.

Figure 7. Schematic view of the auxiliary LV-comparator.
Figure 8. Micrograph of the proposed voltage reference with the layout aligned and superimposed in order to show the devices and interconnections that would be otherwise hidden below the planarization dummies. The dimensions and the main blocks are indicated.
Sizing of LV-VR transistors.
Sizing of LV-VR passive components.
Performance summary and comparison of state-of-the-art LV VRs.
A Low-Power CMOS Bandgap Voltage Reference for Supply Voltages Down to 0.5 V

August 2021

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174 Reads

A voltage reference is strictly required for sensor interfaces that need to perform nonratiometric data acquisition. In this work, a voltage reference capable of working with supply voltages down to 0.5 V is presented. The voltage reference was based on a classic CMOS bandgap core, properly modified to be compatible with low-threshold or zero-threshold MOSFETs. The advantages of the proposed circuit are illustrated with theoretical analysis and supported by numerical simulations. The core was combined with a recently proposed switched capacitor, inverter-like integrator implementing offset cancellation and low-frequency noise reduction techniques. Experimental results performed on a prototype designed and fabricated using a commercial 0.18 μm CMOS process are presented. The prototype produces a reference voltage of 220 mV with a temperature sensitivity of 45 ppm/°C across a 10–50 °C temperature range. The proposed voltage reference can be used to source currents up to 100 μA with a quiescent current consumption of only 630 nA.

A 40 nW CMOS-Based Temperature Sensor with Calibration Free Inaccuracy within ±0.6 ∘C

November 2019

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346 Reads

In this study, a temperature equivalent voltage signal was obtained by subtracting output voltages received from two individual temperature sensors. These sensors work in the subthreshold region and generate the output voltage signals that are proportional and complementary to the temperature. Over the temperature range of −40 ∘C to +85 ∘C without using any calibration method, absolute temperature inaccuracy less than ±0.6 ∘C was attained from the measurement of five prototypes of the proposed temperature sensor. The implementation was done in a standard 0.18 μ m CMOS technology with a total area of 0.0018 mm 2. The total power consumption is 40 nW for a supply voltage of 1.2 V measured at room temperature.

Figure 2. Schematic of the proposed wideband multi-section coupled-line balun. 
Table 2 . Performance comparison of the proposed balun with recent works. 
A 0.8–8 GHz Multi-Section Coupled Line Balun

April 2015

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313 Reads

In this work, we propose a wideband multi-section transforming coupled-line balun using near equal length transmission line elements. The resulting design is realized by cascading several coupled-lines with minimal discontinuities. The multi-section Chebyshev matching optimizes bandwidth at the expense of passband ripple. The proposed design delivers good impedance matching and consistent 180° phase shift over 0.8-8 GHz frequency spectrum. Furthermore, the need for vias in conventional balun designs is relaxed by replacing the short-circuited (SC) terminal by its equivalent dual open-circuited (OC) element. The proposed design is simulated, fabricated, and measured. Both simulated and measured results are in a good agreement, and show an input port matching of below −9.7 dB over the design bandwidth, with a maximum phase and amplitude imbalance of 2.1° and 0.9 dB, respectively.

A 350-GHz Coupled Stack Oscillator with −0.8 dBm Output Power in 65-nm Bulk CMOS Process

July 2020

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90 Reads

This paper presents a push-push coupled stack oscillator that achieves a high output power level at terahertz (THz) wave frequency. The proposed stack oscillator core adopts a frequency selective negative resistance topology to improve negative transconductance at the fundamental frequency and a transformer connected between gate and drain terminals of cross pair transistors to minimize the power loss at the second harmonic frequency. Next, the phases and the oscillation frequencies between the oscillator cores are locked by employing an inductor of frequency selective negative resistance topology. The proposed topology was implemented in a 65-nm bulk CMOS technology. The highest measured output power is −0.8 dBm at 353.2 GHz while dissipating 205 mW from a 2.8 V supply voltage.

Design of Soft-Switching Hybrid DC-DC Converter with 2-Phase Switched Capacitor and 0.8nH Inductor for Standard CMOS Process

February 2020

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728 Reads

A soft-switching hybrid DC-DC converter with a 2-phase switched capacitor is proposed for the implementation of a fully-integrated voltage regulator in a 65 nm standard CMOS process. The soft-switching operation is implemented to minimize power loss due to the parasitic capacitance of the flying capacitor. The 2-phase switched capacitor topology keeps the same resonance value for every soft-switching operation, resulting in minimizing the voltage imbalance of the flying capacitor. The proposed adaptive timing generator digitally calibrates the turn-on delay of switches to achieve a complete soft-switching operation. The simulation results show that the proposed soft-switching hybrid DC-DC converter with a 2-phase 2:1 switched capacitor improves the efficiency by 5.1% and achieves 79.5% peak efficiency at a maximum load current of 250 mA.

Ten-Bit 0.909-MHz 8-Channel Dual-Mode Successive Approximation ADC for a BLDC Motor Drive

March 2021

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99 Reads

This paper presents a 10-bit 0.909-MHz 8-channel dual-mode successive approximation (SAR) analogue-to-digital converter (ADC) for brushless direct current (BLDC) motor drive, using a Taiwan Semiconductor Manufacturing (TSMC) 0.25 μm 1P3M Complementary Metal Oxide Semiconductor (CMOS) process. The sample-and-hold (S/H) circuit operates with two sampling modes. One is individually sampling eight channels in sequence with an S/H circuit and the other is sampling four channels simultaneously with four S/H circuits. All sampled data will be digitized with high-speed SAR ADC in time division multiplexing (TDM). A dynamic latch-type comparator is utilized to latch the output at an upper or lower level. The advantage of the designed comparator is that it performs with positive feedback to quickly complete the latch function. The double-tail latch-type architecture is utilized to mitigate the significant kickback effect by separating the pre-amplifier stage from the latch. By integrating an input NMOSFET with an input PMOSFET, the designed latch-type comparator can perform with full-swing input voltage. Measurements show that the signal-to-noise ratio (SNR), signal-to-noise-and-distortion ratio (SNDR), effective number of bits (ENOB), power consumption, and chip area are 50.56 dB, 57.03 dB, 8.11 bits, 833 μW, and 1.35 × 0.98 mm2, respectively. The main advantages of the proposed multichannel dual-mode SAR ADC are its low power consumption of 833 μW and high measured resolution of 8.11 bits.

Polynomial Algorithm for Minimal (1,2)-Dominating Set in Networks

January 2022

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46 Reads

Dominating sets find application in a variety of networks. A subset of nodes D is a (1,2)-dominating set in a graph G=(V,E) if every node not in D is adjacent to a node in D and is also at most a distance of 2 to another node from D. In networks, (1,2)-dominating sets have a higher fault tolerance and provide a higher reliability of services in case of failure. However, finding such the smallest set is NP-hard. In this paper, we propose a polynomial time algorithm finding a minimal (1,2)-dominating set, Minimal_12_Set. We test the proposed algorithm in network models such as trees, geometric random graphs, random graphs and cubic graphs, and we show that the sets of nodes returned by the Minimal_12_Set are in general smaller than sets consisting of nodes chosen randomly.

High Precision Multiplier for RNS {2n−1,2n,2n+1}

May 2021

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87 Reads

The Residue Number System (RNS) is a non-weighted number system. Benefiting from its inherent parallelism, RNS has been widely studied and used in Digital Signal Processing (DSP) systems and cryptography. However, since the dynamic range in RNS has been fixed by its moduli set, it is hard to solve the overflow problem, which can be easily solved in Two’s Complement System (TCS) by expanding the bit-width of it. For the multiplication in RNS, the traditional way to deal with overflow is to scale down the inputs so that the result can fall in its dynamic range. However, it leads to a loss of precision. In this paper, we propose a high-precision RNS multiplier for three-moduli set 2n−1,2n,2n+1, which is the most used moduli set. The proposed multiplier effectively improves the calculation precision by adding several compensatory items to the result. The compensatory items can be obtained directly from preceding scalers with little extra effort. To the best of our knowledge, we are the first one to propose a high-precision RNS multiplier for the moduli set 2n−1,2n,2n+1. Simulation results show that the proposed RNS multiplier can get almost the same calculation precision as the TCS multiplier with respect to Mean Square Error (MSE) and Signal-to-Noise Ratio(SNR), which outperforms the basic scaling RNS multiplier about 2.6–3 times with respect to SNR.

Optical and Surface Characterization of Radio Frequency Plasma Polymerized 1-Isopropyl-4-Methyl-1,4-Cyclohexadiene Thin Films

June 2014

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1,448 Reads

Low pressure radio frequency plasma-assisted deposition of 1-isopropyl-4-methyl-1,4-cyclohexadiene thin films was investigated for different polymerization conditions. Transparent, environmentally stable and flexible, these organic films are promising candidates for organic photovoltaics (OPV) and flexible electronics applications, where they can be used as encapsulating coatings and insulating interlayers. The effect of deposition RF power on optical properties of the films was limited, with all films being optically transparent, with refractive indices in a range of 1.57-1.58 at 500 nm. The optical band gap (Eg) of ~3 eV fell into the insulating Eg region, decreasing for films fabricated at higher RF power. Independent of deposition conditions, the surfaces were smooth and defect-free, with uniformly distributed morphological features and average roughness between 0.30 nm (at 10 W) and 0.21 nm (at 75 W). Films fabricated at higher deposition power displayed enhanced resistance to delamination and wear, and improved hardness, from 0.40 GPa for 10 W to 0.58 GPa for 75 W at a load of 700 μN. From an application perspective, it is therefore possible to tune the mechanical and morphological properties of these films without compromising their optical transparency or insulating property.

A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

August 2021

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526 Reads

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a –40 to 120°C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off.

AERO: A 1.28 MOP/s/LUT Reconfigurable Inference Processor for Recurrent Neural Networks in a Resource-Limited FPGA

May 2021

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83 Reads

This study presents a resource-efficient reconfigurable inference processor for recurrent neural networks (RNN), named AERO. AERO is programmable to perform inference on RNN models of various types. This was designed based on the instruction-set architecture specializing in processing primitive vector operations that compose the dataflows of RNN models. A versatile vector-processing unit (VPU) was incorporated to perform every vector operation and achieve a high resource efficiency. Aiming at a low resource usage, the multiplication in VPU is carried out on the basis of an approximation scheme. In addition, the activation functions are realized with the reduced tables. We developed a prototype inference system based on AERO using a resource-limited field-programmable gate array, under which the functionality of AERO was verified extensively for inference tasks based on several RNN models of different types. The resource efficiency of AERO was found to be as high as 1.28 MOP/s/LUT, which is 1.3-times higher than the previous state-of-the-art result.

Figure 13. Illustration of the tuning gain capability for the HCF mode.
Figure 14. Illustration of the tuning gain capability for the LCF mode.
Fabricated device's sizing.
Summary of the LNA's simulated and experimental results.
A Tunable Gain and Bandwidth Low-Noise Amplifier with 1.44 NEF for EMG and EOG Biopotential Signal
  • New
  • Article
  • Full-text available

June 2023

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46 Reads

This paper presents a low-noise inverter-based current-mode instrumentation amplifier with tunable gain and bandwidth for electromyogram (EMG) and electrooculogram (EOG) biopotential signals, targeting low input noise while maintaining low power consumption. The gain tuning method is based on pseudo-resistors, whereas the bandwidth is tunable due to a varactor system that is controlled by the same control voltage that tunes the gain. The circuit was designed and manufactured using the 110 nm UMC CMOS technology node, occupying an area of 0.624 mm2. The circuit presents a functioning mode for each biopotential signal with different characteristics, for the EMG a gain of 34.7 dB and a bandwidth of 1412 Hz was measured, with an input referred noise of 1.407 μV which matches a noise efficiency factor of 1.44. The EOG mode achieves a 39.5 dB gain and a 22.4 Hz bandwidth while presenting an input-referred noise of 0.829 μV corresponding to a noise efficiency factor of 6.37. For both modes, the supply voltage is 1.2 V and the circuit consumes 1 μA.

Spectrum Values in Suburban/Urban Environments above 1.5 GHz

December 2018

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364 Reads

Frequency bands higher than 3 GHz will be allocated for 5G telecommunication services. Therefore, investigating the spectrum values at these frequency bands is important for developing an appropriate deployment strategy. In this paper, spectrum values above 1.5 GHz are investigated in suburban and urban environments. In the suburban environment, the relative spectrum values at different positions in a cell are analyzed for frequencies ranging from 500 MHz to 1.5 GHz, 1.5 GHz to 3 GHz, and 3 GHz to 11 GHz. In the urban environment, the maximum achievable capacity of users is calculated for frequencies ranging from 500 MHz to 40 GHz. Numerical results show that spectrum values at lower frequency bands below 5 GHz present higher values at the cell-edge in the suburban environment and in non-line-of-sight (NLoS) situations in the urban environment. However, higher frequency bands have nearly the same impact as low frequency bands at the cell center in suburban environments above 5 GHz but show advantages in outdoor urban environments with line-of-sight (LoS) above 20 GHz. It should be noted that 3.5 GHz shows the highest value in NLoS situations and the indoor domain environment in UMi scenarios, while 28 GHz gives the optimum value at the cell-center and indoor areas with LoS in UMa scenarios. When considering the spectrum value for different frequency bands, the primary consideration should be whether the environment is NLoS or LoS, and the secondary consideration should be whether the environment is indoor or outdoor.

Figure 1. The top-level architecture of the proposed four-lane TX with on-chip PLL.
A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

August 2021

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144 Reads

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

K-Shaped Silicon Waveguides for Logic Operations at 1.55 μm

November 2022

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40 Reads

Silicon has properties that make it the preferable semiconductor material for realizing a wide suite of electronic devices. In this paper, all basic optical logic operations, including XOR, AND, OR, NOT, NOR, XNOR, and NAND, are demonstrated by means of simulation using K-shaped compact silicon waveguides operated at the 1.55 μm telecommunications wavelength. This waveguide comprises three waveguide strips, all made of silicon printed on silica. By adjusting the phase of the incident beams, the pursued logic operations can be realized. To evaluate how well the considered operations are performed, the contrast ratio (CR) is employed as a figure of merit. Compared to other reported waveguides, the suggested K-shaped waveguide achieves higher CRs and a speed of the order of 120 Gb/s.

A Flexible and Pattern Reconfigurable Antenna with Small Dimensions and Simple Layout for Wireless Communication Systems Operating Over 1.65–2.51 GHz

March 2021

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473 Reads

This research article proposes a compact frequency and pattern reconfigurable flexible antenna for heterogeneous applications. A triangular monopole antenna with a semicircular stub is made frequency and pattern tunable by connecting and disconnecting two inverted L‐shaped stubs utilizing diodes. When either of the stubs is connected to the radiator, a relative phase difference happens at both ends of the radiator that changes the direction of the electromagnetic radiations, consequently pattern reconfigurability can be obtain. Besides that, because of the reactive load introduced by the stubs, the antenna’s effective length has changed and, as a result, the frequency reconfigurability can be attained. The antenna features a compact size of 40 × 50 × 0.254 mm³ corre-sponding to 0.22λo × 0.27λo × 0.001λo, where λo is free‐space wavelength at 1.65 GHz, while its opera-tional bandwidth is from 1.65 GHz to 2.51 GHz, with an average gain and radiation efficiency of better than 2.2 dBi and 80%, exhibiting a pattern reconfigurability of 180° in the E‐plane. The frequency of the proposed antenna can be switched from 2.1 GHz to 1.8 GHz by switching the state of both diodes in OFF and ON‐state, respectively. The fabricated prototype of the antenna is tested to verify its performance parameters. In addition, to validate the proposed design, it has been compared with prior arts in terms of the overall size, reconfigurability type, flexibility, radio frequency (RF) switch type used for reconfigurability, and frequency bandwidth. The proposed antenna provides smaller size with a large bandwidth coverage alongside with discrete RF switch type with the advantages of flexibility and both frequency and pattern reconfigurability. As a result, the proposed compact flexible and pattern reconfigurable antenna is a promising candidate for heterogeneous applications, including the global system for mobile (GSM) band (1800 and 1900 MHz) and industri-al, scientific and medical (ISM) band (2.4 GHz) along with well‐known cellular communication bands of 3G, 4G, and long term evolution (LTE) bands ranging from 1700–2300 MHz around the globe.

Figure 2. (a) Traditional source follower; (b) Traditional super source follower.
Fully Integrated 1.8 V Output 300 mA Load LDO with Fast Transient Response

March 2023

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404 Reads

Based on an 0.18 μm process, this paper proposes a fully integrated 1.8 V output 300 mA load low-dropout linear regulator (LDO) with a fast transient response. By inserting a transient-enhanced biased Class AB super source follower at the gate of the output power transistor, this LDO can quickly adjust the gate voltage of the power transistor without additional power consumption. By adding an active capacitor circuit composed of a fast comparator with offset voltage at the output point, this LDO can quickly charge/discharge the transient current and accelerate the transient response without reducing the circuit stability. Simulation results show that the proposed LDO has an output voltage of 1.8 V, when the input voltage is 2 V to 5 V while consuming 66.4 μA of quiescent current. The proposed capless LDO has a 1.94 µV/mA load regulation, a 0.55 mV/V linear regulation, and a −60 dB@1 kHz power supply rejection. When the load current steps from 3 mA to 300 mA in 300 ns, the LDO settles in 400 ns with an overshoot and undershoot of 67 mV and 86 mV, respectively.

Figure 1. Negative resistance circuit: (a) schematic; (b) simplified equivalent circuit used for impedance calculations; (c) complete equivalent circuit with neglected parameters.
Figure 3. Schematic of the designed 2nd order active filter without biasing.
Performances comparison for different filters.
A Second Order 1.8–1.9 GHz Tunable Active Band-Pass Filter with Improved Noise Performances

September 2022

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47 Reads

In this paper, a novel active tunable band-pass filter with improved noise performances is presented. This filter is based on a negative resistance circuit (or active capacitance), where the gain obtained with a transistor is used to compensate for inductor losses. Moreover, the capacitance of the resonator is obtained through a voltage-controlled reverse-biased varactor, which allows for frequency tuning. Despite the active component, the proposed filter also has good noise performance. Measurements show a tunability range from 1.816 GHz to 1.886 GHz, with a bandwidth of 38 MHz. The insertion loss maximum value is 0.4 dB, while the noise figure value has a minimum value of 2.5 dB at the center frequency within the tunability range.

Table 1 . Components size information.
Table 2 . Performance comparison with prior works.
Figure 9. Isolation-Monte Carlo simulation results: (a) Rx mode; and (b) Tx mode.
40 dB-Isolation, 1.85 dB-Insertion Loss Full CMOS SPDT Switch with Body-Floating Technique and Ultra-Small Active Matching Network Using On-Chip Solenoid Inductor for BLE Applications

November 2018

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192 Reads

In the IoT/wearable devices, the antenna is shared with the receiver and transmitter of the transceiver. This requires the control of the switch between the antenna and the control circuitry to achieve both low insertion loss and high isolation. This paper presents a low insertion loss and high isolation switch based on Single Pole Double Throw (SPDT) switch for 2.4 GHz Bluetooth low power (BLE) transceiver. The body-floating technique is used to improve the insertion loss’s performance. An ultra-small on-chip matching network with high Q-factor is proposed. The shunt transistors are used as active shunt capacitors that create the active matching network to improve isolation characteristics. The proposed SDPT switch was designed using 55 nm CMOS process with the total area of 110 μm × 210 μm. The insertion loss and isolation characteristics of the proposed SPDT switch observed at 2.4 GHz are 1.85 dB and 40 dB, respectively.

Figure 3. Simulated power-supply rejection ratio (PSRR) of (a) VDD PU regulator and (b) VDD PD regulator across regulator segment configuration.
Figure 7. Return loss specification of PCIe Gen4 transmitter and measured return loss from the prototype chip.
Performance comparison.
A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

January 2021

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1,026 Reads

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

Small Group Delay Variation and High Efficiency 3.1–10.6 GHz CMOS Power Amplifier for UWB Systems

January 2022

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81 Reads

A two-stage cascaded power amplifier (PA) employing a proposed Resistor-Capacitor (RC) interstage was provided and simulated. The current-reuse topology is employed at the first stage to lower the power consumption, while the RC interstage helps to enrich the gain flatness and the wideband matching. The shunt peaking topology in a common source configuration is adopted at the second stage to enhance the power gain. The postlayout simulation is performed using the TSMC 65 nm CMOS process operating in a frequency band of 3.1 GHz to 10.6 GHz. The postlayout simulation results indicate that a high flat gain of approximately 22.8 ± 1.2 dB, small group delay variation of ±50 ps, and good input and output matching of less than −10 dB are achieved over the desired working band. Moreover, a saturated output power of 10 dBm and maximum power-added efficiency (PAE) of 29.5% is achieved at 6 GHz. The proposed PA consumes the low power of 15.5 mW from 1.2 V supply voltage.

A Low Power 1024-Channels Spike Detector Using Latch-Based RAM for Real-Time Brain Silicon Interfaces

December 2021

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124 Reads

High-density microelectrode arrays allow the neuroscientist to study a wider neurons population, however, this causes an increase of communication bandwidth. Given the limited resources available for an implantable silicon interface, an on-fly data reduction is mandatory to stay within the power/area constraints. This can be accomplished by implementing a spike detector aiming at sending only the useful information about spikes. We show that the novel non-linear energy operator called ASO in combination with a simple but robust noise estimate, achieves a good trade-off between performance and consumption. The features of the investigated technique make it a good candidate for implantable BMIs. Our proposal is tested both on synthetic and real datasets providing a good sensibility at low SNR. We also provide a 1024-channels VLSI implementation using a Random-Access Memory composed by latches to reduce as much as possible the power consumptions. The final architecture occupies an area of 2.3 mm2, dissipating 3.6 µW per channels. The comparison with the state of art shows that our proposal finds a place among other methods presented in literature, certifying its suitability for BMIs.

A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications

September 2019

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980 Reads

This paper describes a fourth-order cascade-of-integrators with feedforward (CIFF) single-bit discrete-time (DT) switched-capacitor (SC) delta-sigma modulator (DSM) for high-resolution applications. This DSM is suitable for high-resolution applications at low frequency using a high-order modulator structure. The proposed operational transconductance amplifier (OTA), used a feedforward amplifier scheme that provided a high-power efficiency, a wider bandwidth, and a higher DC gain compared to recent designs. A chopper-stabilization technique was applied to the first integrator to remove the 1/f noise from the transistor, which is inversely proportional to the frequency. The designed DSM was implemented using 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The oversampling ratio (OSR) was 128, and the sampling frequency was 128 kHz. At a 500 Hz bandwidth, the signal-to-noise ratio (SNR) was 100.3 dB, the signal-to-noise distortion ratio (SNDR) was 98.5 dB, and the dynamic range (DR) was 103 dB. The measured total power dissipation was 99 µW from a 3.3 V supply voltage.



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